Saturday, February 13, 2016

ALD HfO2 HKMG FETs on CVD mono layer graphene channels on 200 mm glass wafers by Samsung

Samsung Advanced Institute of Technology and Samsung-SKKU Graphene/2D Center showcases ALD HfO2 high-k transistors on mono layer graphene channels using 200 mm glass wafers. The ALD Process is TEMAHf/H2O running at 200 C and they achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors.
Check out the free to down load Nature Scientific Report below.

SAIT (Samsung Advanced Institute of Technology)

Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors. 

Seong-Jun Jeong, Yeahyun Gu, Jinseong Heo, Jaehyun Yang, Chang-Seok Lee, Min-Hyun Lee, Yunseong Lee, Hyoungsub Kim, Seongjun Park & Sungwoo Hwang
Sci. Rep. 6, 20907; doi: 10.1038/srep20907 (2016).

(a) Optical image of the MOG-FET arrays fabricated on a 6″ Si wafer and a schematic illustration showing the structure of the MOG-FET device. (b) Optical microscope image of a fabricated MOG-FET unit device. (c) Cross sectional TEM image showing the HfO2 gate dielectric layer with a thickness of ~5 nm (including the seed layer converted to a HfO2 layer) on monolayered graphene. (d) Statistical distribution of the sheet resistance of a monolayered graphene before and after the ALD of HfO2 with and without an e-beam-evaporated Hf seed layer. Representative electrical characteristics measured from the fabricated MOG-FET devices: (e) gate dielectric leakage current, (f) gate capacitance as a function of the frequency, and (g) transfer curve (ID-VG). (Sci. Rep. 6, 20907; doi: 10.1038/srep20907 (2016)., Creative Commons Attribution 4.0 International License)

The downscaling of the capacitance equivalent oxide thickness (CET) of a gate dielectric film with a high dielectric constant, such as atomic layer deposited (ALD) HfO2, is a fundamental challenge in achieving high-performance graphene-based transistors with a low gate leakage current. Here, we assess the application of various surface modification methods on monolayer graphene sheets grown by chemical vapour deposition to obtain a uniform and pinhole-free ALD HfO2 film with a substantially small CET at a wafer scale. The effects of various surface modifications, such as N-methyl-2-pyrrolidone treatment and introduction of sputtered ZnO and e-beam-evaporated Hf seed layers on monolayer graphene, and the subsequent HfO2 film formation under identical ALD process parameters were systematically evaluated. The nucleation layer provided by the Hf seed layer (which transforms to the HfO2 layer during ALD) resulted in the uniform and conformal deposition of the HfO2 film without damaging the graphene, which is suitable for downscaling the CET. After verifying the feasibility of scaling down the HfO2 thickness to achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors, we fabricated graphene heterojunction tunnelling transistors with a record-low subthreshold swing value of <60 mV/dec on an 8″ glass wafer.

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