Tuesday, February 9, 2016

Sub 20nm DRAM High-k from NaMLab, RWTH, KU Leuven and Samsung

NaMLab in Dresden, RWTH Aachen,Germany, KU Leuven, Belgium and Samsung has quite successfully since some years been collaborating on further high-k development for sub 20 nm DRAM. The research is lead by Uwe Schröder (ex-Qimonda High-k Principal) and Kyhyo Cho from Samsung. Here is a recent paper on how to push the ZrO2 based high-k further to even lower CET and leakage performance by introducing SrO inter layer high-k. Please enjoy this open source publication - abstract is given below.

Instead of STO based high-k that is physically too thick to fit in a sub 20nm DRAM cell, two different new approaches to develop a new ZrO based DRAM capacitor stack are presented:

1) by changing the inter-layer material from AlO to SrO 
2) the exchange of the top electrode material from TiN to Pt 

Low leakage ZrO based capacitors for sub 20 nm dynamic random access memory technology nodes

Milan Pešić, Steve Knebel, Maximilian Geyer, Sebastian Schmelzer, Ulrich Böttger, Nadiia Kolomiiets, Valeri V. Afanas'ev, Kyuho Cho, Changhwa Jung, Jaewan Chang, Hanjin Lim, Thomas Mikolajick and Uwe Schroeder
J. Appl. Phys. 119, 064101 (2016); http://dx.doi.org/10.1063/1.4941537
 
 
 

During dynamic random access memory (DRAM) capacitor scaling, a lot of effort was put searching for new material stacks to overcome the scaling limitations of the current material stack, such as leakage and sufficient capacitance. In this study, very promising results for a SrTiO based capacitor with a record low capacitance equivalent thickness value of 0.2 nm at target leakage current are presented. Due to the material properties of SrTiO films (high vacancy concentration and low band gap), which are leading to an increased leakage current, a physical thickness of at least 8 nm is required at target leakage specifications. However, this physical thickness would not fit into an 18 nm DRAM structure. Therefore, two different new approaches to develop a new ZrO based DRAM capacitor stack by changing the inter-layer material from AlO to SrO and the exchange of the top electrode material from TiN to Pt are presented. A combination of these two approaches leads to a capacitance equivalent thickness value of 0.47 nm. Most importantly, the physical thickness of <5 nm for the dielectric stack is in accordance with the target specifications. Detailed evaluation of the leakage current characteristics leads to a capacitor model which allows the prediction of the electrical behavior with thickness scaling.