SiCarrier Seeks $2.8 Billion to Advance Chipmaking Equipment

SiCarrier, a Chinese chip equipment manufacturer closely associated with Huawei and owned by the Shenzhen city government, is seeking $2.8 billion in funding to advance its ambitions of becoming China's leading chipmaking equipment provider. Founded in 2021, the company aims to surpass domestic rivals such as Naura and AMEC, amid U.S. export restrictions that have fueled China's drive for semiconductor self-sufficiency. The fundraising, targeting a valuation of $11 billion, is expected to conclude soon, with proceeds allocated primarily to R&D. State-owned firms and domestic investors have shown strong interest. Despite showcasing 30 products at Semicon China 2025, most of its tools remain under development and are not yet production-ready. SiCarrier has filed 92 patents, indicating plans to offer a comprehensive suite of chipmaking tools, including lithography and AI-driven inspection systems. However, its deep ties to Huawei have raised concerns among potential customers over data security and trade secret protection. Industry experts suggest full operational independence from Huawei is essential for broader market acceptance and long-term growth.

"Founded in 2021 and owned by the Shenzhen city government, SiCarrier is largely seen as a Huawei supplier. But it wants to become the leading domestic provider of chipmaking equipment in China, surpassing Naura and Advanced Micro-Fabrication Equipment China (AMEC), according to four people with knowledge of its goals."

A Reuters review of 92 patents filed by Shenzhen SiCarrier Industry Machines and its parent Shenzhen SiCarrier Technologies between October 2022 and March 2025 reveals the company’s ambitious plan to establish itself as a comprehensive supplier of semiconductor manufacturing equipment. Unlike domestic peers such as Naura and AMEC, which have taken more focused approaches, SiCarrier is pursuing an expansive product roadmap that spans the entire chip production chain—from wafer metrology and defect inspection to etching and atomic layer deposition (ALD) systems. These filings, verified through Anaqua’s AcclaimIP database, illustrate SiCarrier’s intention to compete head-on with established global players such as KLA, Lam Research, and Tokyo Electron, particularly in process-critical segments like thin-film deposition and etch uniformity control. Notably, SiCarrier is investing in AI-powered wafer defect recognition, a frontier area aimed at enhancing production yields, especially important in advanced nodes where precision is paramount. Industry observers cited by Reuters suggest metrology and inspection tools offer SiCarrier the most immediate opportunity, given the absence of a dominant Chinese competitor in that space. The patent portfolio also reveals efforts to close the technological gap in lithography by focusing on components for deep ultraviolet (DUV) systems and multi-patterning techniques. These are presented as domestic alternatives to extreme ultraviolet (EUV) lithography, which remains out of reach due to US export controls. However, experts like Dan Hutcheson of TechInsights caution that the multi-patterning approach—though pioneered by Intel and used by TSMC at 7 nm—carries known drawbacks such as increased complexity and yield challenges, stemming from its reliance on sequential deposition and several etch processes. 

Sources:

Exclusive: SiCarrier - Huawei partner in chips - seeks $2.8 billion in funds, sources say | Reuters

Tokyo Electron Delivers Record FY2025 Results Amid AI Boom, Eyes Growth Through CVD Innovation and Geopolitical Resilience

Tokyo Electron (TEL) achieved a record-breaking financial year in FY2025, with strong top- and bottom-line growth driven by robust global demand for advanced semiconductor equipment. Net sales rose by 32.8% year-on-year to approximately ¥2.43 trillion (around $15.7 billion USD), marking the highest in the company's history. Operating profit surged to ¥697.3 billion (about $4.5 billion USD), supported by an improved operating margin of 28.7%. Growth was underpinned by increased investment in leading-edge logic and memory, particularly High Bandwidth Memory (HBM) and advanced DRAM nodes, where TEL maintained or expanded market share through key Process of Record (POR) wins in etch and wafer bonding technologies. Revenue contributions diversified geographically, with notable gains in South Korea and Taiwan, even as China remained a key market. TEL also demonstrated strong cash flow, increased its R&D and capital investments, and returned significant value to shareholders through dividends and buybacks. Looking ahead, TEL forecasts continued growth in FY2026, positioning itself to capitalise on accelerating AI, 2nm logic, and heterogeneous integration trends.

Tokyo Electron TEL has demonstrated strong financial performance and strategic market expansion through FY2025, according to their investor presentation dated April 30, 2025. Their net sales, gross profit, operating profit, and net income have all reached record highs, signaling both operational efficiency and favorable market conditions.

LINK: Tokyo Electron Limited 2025 Q4 - Results - Earnings Call Presentation (OTCMKTS:TOELY) | Seeking Alpha

Tokyo Electron's Q4 FY2025 earnings call highlighted strong financial performance and an optimistic forward outlook amid geopolitical uncertainties. Despite global concerns around US tariffs and export controls—particularly in China, which saw its WFE market share fall to 35%—TEL stated that it has not observed any significant changes in customer investment sentiment or competitive dynamics. The company reaffirmed its strategy of focusing on long-term innovation rather than short-term regulatory shifts, underscoring its commitment to developing higher-productivity tools to offset potential external headwinds. Looking ahead, TEL forecasts continued double-digit WFE market growth into calendar 2026, driven by AI infrastructure demand, 2nm logic, and HBM scaling. The company plans record-high investments of ¥300 billion in R&D and ¥240 billion in CapEx for FY2026, reflecting confidence in sustained momentum across DRAM, advanced logic, and packaging technologies. TEL aims to expand global market share and reach ambitious mid-term goals, including over ¥1 trillion in operating profit and 35%+ OPM, by capitalising on technology transitions such as GAA, backside PDN, and heterogeneous integration.

LINK: Tokyo Electron Limited (TOELY) Q4 2025 Earnings Call Transcript | Seeking Alpha

Revenue and Profitability Growth:

Net sales increased significantly from ¥1,399.1 billion in FY2021 to ¥2,431.5 billion in FY2025, a 74% increase over four years. The gross profit also rose steadily, reaching ¥1,146.2 billion in FY2025, up from ¥564.9 billion in FY2021. Operating profit followed suit, more than doubling from ¥320.6 billion to ¥697.3 billion. These trends underscore TEL’s ability to scale profitably, with operating margins rising from 22.9% in FY2021 to 28.7% in FY2025. Return on equity (ROE) also remained strong, peaking at 37.2% in FY2022 and settling at 30.3% in FY2025, a testament to effective capital management.

Regional Sales Composition:

The revenue breakdown by region from Q1 FY2024 to Q4 FY2025 shows growing diversification. Notably, China has remained the single largest market, although its share declined from 47.4% in Q4 FY2024 to 34.3% in Q4 FY2025, reflecting a strategic balancing across geographies. South Korea, Taiwan, and North America significantly increased their contributions, with South Korea reaching ¥147.0 billion and Taiwan ¥135.8 billion in Q4 FY2025. This reflects growing demand from advanced logic and memory fabrication customers in these regions.

In FY2025, Tokyo Electron’s semiconductor production equipment (SPE) sales reached ¥1.86 trillion, driven by a sharp rise in DRAM-related investments, particularly for high-bandwidth memory (HBM), which accounted for 31% of total sales. Non-volatile memory (NAND) remained stable at 7%, while non-memory segments, including logic and foundry, continued to dominate with 62%, reflecting robust demand from both advanced and mature nodes. The overall recovery and expansion of customer investments across segments underpinned this strong performance.

Market Segment Performance

Tokyo Electron’s global market share in CY2024 demonstrates its leadership across multiple core segments of the semiconductor production equipment market. The company holds a commanding 92% share in coater/developer systems, underlining its unparalleled position in photoresist processing for advanced lithography applications. It also leads the wafer prober segment with a 38% share and maintains robust positions in key deposition categories, including 38% in CVD and 37% in oxidation/diffusion systems. In contrast, TEL’s market share in ALD stands at 16%, notably behind ASM International, highlighting an opportunity for expansion in this strategically important technology as the industry moves towards GAA and other 3D device structures. Performance in dry etch (27%), cleaning systems (21%), and wafer bonding (32%) rounds out a broadly competitive portfolio that positions TEL to effectively support ongoing advancements in scaling, heterogeneous integration, and high-performance packaging across logic, memory, and AI-related applications.

To further expand our future profit, we made steady progress in penetrating into new technology domains. Specifically, we released multiple new outstanding products contributing to the semiconductor technology innovation. For example, penetration to untapped segments such as single-wafer plasma CVD and PVD, gas cluster beam system which improves efficiency of leading-edge lithography, and laser-lift-off system to drastically decrease environmental footprint of processing. In fiscal 2025, we conducted share repurchase of about ¥150 billion in total.

- Toshiki Kawai - Representative Director, President and CEO

 

New product 2025 Episode™ single-wafer CVD platform

Episode™ 1 is Tokyo Electron's latest single-wafer CVD platform, launched in 2024 to address the challenges of advanced device scaling in logic, DRAM, and future AI processors. It supports up to eight process modules, enabling complex, uninterrupted multi-step processing. The system integrates the OPTCURE™ module for native oxide removal and ORTAS™ for titanium CVD, allowing immediate Ti deposition to minimise contact resistance in advanced interconnects. Episode™ 1 replaces traditional PVD with CVD to achieve uniform, low-resistivity films in high aspect ratio structures such as deep contact holes. With a 45% smaller footprint than its predecessor and advanced edge computing, data analytics, and environmental tracking capabilities, the system enhances fab productivity, engineer efficiency, and readiness for new materials in next-generation device manufacturing.

The TEL Episode™ 1 system shown in the image seems to feature twin or dual single-wafer process chambers, which is typical in modular CVD tools designed for high throughput. Each visible module (with two load ports per unit) likely contains two process chambers within the same footprint to maximise wafer handling efficiency and enable parallel processing—common in tools aimed at advanced logic and memory manufacturing.

Episode™ 1 offers a reduced footprint. Compared with the Triase+™ series, twice as many smaller modules can be installed in a system. With the same number of modules installed, Episode™ 1 takes up about 45% less fab space than its predecessor

LINK: Episode™ 1 Single-Wafer Deposition System for Semiconductors: Driving the Evolution of AI Semiconductors to Transform Everyday Life | Blog | Tokyo Electron Ltd.

Applied Materials Unveils Industry-First Ruthenium-Cobalt Liner and Next-Gen Dielectrics to Enable 2nm Chip Wiring and Boost 3D Stacking for Energy-Efficient AI Computing

Applied Materials has announced new materials engineering breakthroughs aimed at improving energy efficiency in computing by enabling copper wiring to scale down to the 2nm node and beyond. Central to this innovation is the industry’s first high-volume use of ruthenium in a binary metal liner with cobalt (RuCo), which allows for thinner liners, improved copper fill, and up to 25% lower electrical resistance. This innovation, part of the new Endura™ Copper Barrier Seed IMS™ system, combines six process technologies in one high-vacuum system and is already being adopted by major logic chipmakers. These advances address the increasing challenges of interconnect resistance and mechanical weakness as chip feature sizes shrink.

Applied Materials’ new Endura™ Copper Barrier Seed IMS™ with Volta™ Ruthenium CVD combines six different technologies in one high-vacuum system, including an industry-first combination of materials that enables chipmakers to scale copper wiring to the 2nm node and beyond.

Complementing this, Applied also introduced an enhanced version of its long-standing Black Diamond™ low-k dielectric material, designed to reduce capacitance and reinforce chip strength — critical for advanced 3D stacking in logic and memory chips. These solutions help overcome scaling limitations associated with Moore’s Law and are critical for sustaining AI-driven computing advancements. As demand for high-performance, energy-efficient chips grows, Applied’s innovations are expanding its served market for interconnect technologies, which is projected to reach $7 billion per 100K wafer starts per month with the addition of backside power delivery.

With the semiconductor industry’s first use of ruthenium in high-volume production, Applied Materials' new binary metal combination of ruthenium and cobalt (RuCo) enables copper chip wiring to be scaled to the 2nm node and beyond and reduces electrical line resistance by as much as 25 percent.

Applied Materials today introduced an enhanced version of the company’s Producer™ Black Diamond™ PECVD dielectric film. This new material enables chip scaling to 2nm and below, while offering increased mechanical strength to help take 3D logic and memory stacking to new heights.

The new Producer™ Enhanced Black Diamond™ dielectric is a revolutionary product, enabling next-generation chips of the AI era. Enhanced Black Diamond™ addresses two key issues in leading-edge chips. As wires become closer together, parasitic capacitance increases. The phenomenon slows signals down, worsening performance and energy consumption. Additionally, damaging plasma manufacturing processes can cause the thinner insulating dielectric material between wires to fracture or collapse, potentially leading to chip failure (Embedded from Youtube : https://youtu.be/uJju9KNA-yE?si=ae-Eqc0Qaf5J8e0W).

Sources:

Applied Materials Unveils Chip Wiring Innovations for More Energy-Efficient Computing | Applied Materials

Photos accompanying this announcement are available at

https://www.globenewswire.com/NewsRoom/AttachmentNg/96098774-3afd-4e4a-9f5c-e0ba8d523bc2

https://www.globenewswire.com/NewsRoom/AttachmentNg/fd0d0edb-65ea-49ab-a66b-1f5bc5265b16

https://www.globenewswire.com/NewsRoom/AttachmentNg/8c6a061b-92da-4b37-a475-8f57e3884ef4

New Method for Precision Doping in 2D Semiconductors Enables Next-Gen CMOS Integration

Researchers have achieved a breakthrough in doping two-dimensional (2D) semiconductors, paving the way for monolithic integration of p-type and n-type semiconductor channels on a single chip. This development holds promise for advancing complementary CMOS technology, allowing further transistor scaling and efficient interlayer connections.

The study focuses on 2H-MoTe2, a van der Waals material, and employs a precise substitutional doping technique. Unlike conventional methods such as ion implantation—which do not work well with 2D materials—this approach allows the targeted introduction of niobium (Nb) for p-type doping and rhenium (Re) for n-type doping, using a magnetron co-sputtering method followed by chemical vapor deposition (CVD). By precisely adjusting the concentration of these dopants, researchers produced wafer-scale films with consistent carrier properties, even enabling spatial control of the doped regions. This advance allows for the patterning of p-type and n-type channels on the same wafer in a single growth process, which is essential for CMOS device fabrication.

Using this novel technique, the team created a large-scale 2D CMOS inverter array that achieved impressive performance metrics. For instance, a typical inverter from this array demonstrated a voltage gain of 38.2 and low static power consumption, key parameters for efficient CMOS operation. The new doping method also exhibits high uniformity and reliability, essential for scaling up 2D materials in commercial semiconductor applications.

This innovation in 2D semiconductor doping introduces a promising pathway for integrating materials like 2H-MoTe2 into very-large-scale integration (VLSI) technology, further driving forward Moore's Law and the miniaturization of semiconductor devices.

Figure 1 from paper, Pan, Y., Jian, T., Gu, P. et al. Precise p-type and n-type doping of two-dimensional semiconductors for monolithic integrated circuits. Nat Commun 15, 9631 (2024). https://doi.org/10.1038/s41467-024-54050-2

Experimental

In the study, co-sputtering and CVD is used to create large-scale, precisely doped 2D 2H-MoTe2 films by transforming a molybdenum film doped with niobium or rhenium into 2H-MoTe2 through a process called tellurization. Here’s a breakdown of how this process works:

Preparation of the Mo Film: Initially, thin Mo films are deposited on a silicon/silicon dioxide (Si/SiO2) substrate using magnetron co-sputtering. During this step, controlled amounts of Nb (for p-type doping) or Re (for n-type doping) are co-sputtered with the Mo film, resulting in a doped Mo layer.

Tellurization Process in the CVD Reactor: The Mo film, now doped with Nb or Re, is placed in a CVD furnace along with solid tellurium (Te) lumps. Under a controlled flow of carrier gases (argon and hydrogen), the CVD chamber is heated to high temperatures (around 650°C). The Te vapor reacts with the Mo, leading to the formation of 1T'-MoTe2.

Phase Transformation to 2H-MoTe2: At the elevated temperatures within the CVD system, the 1T'-MoTe2 structure undergoes a phase transformation into the more stable 2H phase, producing the final doped 2H-MoTe2 film. This phase is crucial because 2H-MoTe2 has semiconducting properties suitable for integrated circuits.

Doping Incorporation: During the CVD tellurization, Nb and Re atoms from the initial Mo film become substitutionally incorporated into the MoTe2 lattice. This incorporation determines the semiconductor type (p-type or n-type) and carrier concentration of the resulting 2H-MoTe2 film.

Large-Scale Uniformity: By controlling the initial dopant concentration and maintaining consistent conditions in the CVD process, the researchers achieved uniform doping across large-scale wafers, crucial for creating reliable semiconductor devices.

Source: Precise p-type and n-type doping of two-dimensional semiconductors for monolithic integrated circuits | Nature Communications

Lam Research Sees Growth Opportunities in Etch and Deposition Technologies Despite NAND Downturn

In its Q1 2025 earnings call, Lam Research reported strong performance and emphasized growth opportunities, particularly in etch and deposition technology. CEO Tim Archer highlighted optimism for NAND spending recovery in 2025, supported by technology upgrades and a transition to molybdenum through Lam’s advanced Atomic Layer Deposition (ALD). Lam is positioned to capture opportunities in advanced semiconductor nodes like gate-all-around and EUV patterning, while its expanded offerings in high-bandwidth memory (HBM) and advanced packaging align with growing demand in AI and high-performance computing. Despite regulatory challenges in China, Lam continues to serve this market by focusing on upgrades and services. Looking ahead, Lam expects to outpace industry growth, driven by its strategic positioning across advanced technologies.

In its Q1 2025 earnings call, Lam Research Corporation (NASDAQ: LRCX) reported solid performance and reiterated optimism for growth in 2025, largely driven by demand for etch and deposition technologies. CEO Tim Archer emphasized Lam’s strategic positioning in an industry experiencing technological shifts, despite a prolonged downturn in NAND spending.

Lam anticipates a recovery in NAND spending in 2025, largely driven by technology upgrades rather than new capacity expansions. Key factors include a transition from tungsten to molybdenum in NAND structures, which improves performance by reducing resistivity. Lam is well-positioned in this area due to its extensive installed base and production wins, projecting an advantageous position as these upgrades scale into 2025.

NAND Technology Upgrades Set to Drive Etch and Deposition Demand in 2025

While the NAND segment has been in a prolonged downturn, Lam anticipates a recovery in 2025 as manufacturers upgrade to advanced nodes. The push toward 3D NAND layers exceeding 200 is essential to meet the growing demand for high-speed, high-capacity storage in data centers and client devices. Currently, about two-thirds of NAND capacity remains at older technology nodes, highlighting significant room for technology upgrades. Lam’s extensive installed base of NAND equipment positions it well to benefit as customers look to improve efficiency and performance.

Furthermore, Archer highlighted a shift from tungsten to molybdenum as a key materials change in NAND, addressing word line resistance challenges. This transition is particularly favorable for Lam, as it has already secured production wins in molybdenum deposition, which will scale up throughout 2025. These advancements are expected to enhance Lam's leadership position in NAND technology transitions.

Lam's product offerings mentioned in the reporting, along with their primary applications and strategic impacts.

Advanced Logic and Foundry Nodes: Key Growth Segments for Lam

Lam is also poised to benefit from shifts in advanced logic and foundry nodes, which are increasingly adopting gate-all-around architectures, backside power distribution, and advanced EUV patterning. These cutting-edge technologies require more intensive use of etch and deposition processes, aligning with Lam’s expertise and product offerings.

Archer noted the company's recent wins in selective etch tools and other innovations that support these advanced nodes, positioning Lam favorably as customers transition to architectures with greater power and performance needs. This expanding demand from foundry and logic customers offers a substantial growth opportunity for Lam’s advanced etch and deposition technologies.

Advanced Packaging Driven by AI Fuels Revenue Growth

The AI and high-performance computing boom has intensified demand for advanced packaging, particularly for high-bandwidth memory (HBM). Lam’s copper plating technology, SABRE 3D, has experienced substantial adoption, doubling its market share this year. This growth has been fueled by the rising complexity of 2.5D and 3D packages, which require high-performance interconnections to support AI-driven systems.

Lam anticipates this trend will continue into 2025 as the industry moves toward more advanced and intricate packaging solutions. According to Archer, advanced packaging will play a critical role in the semiconductor ecosystem for the foreseeable future, and Lam’s early investment in this technology has positioned it for continued market share gains.

Supporting Installed Base and Productivity in Memory Markets

Lam’s Customer Support Business Group (CSBG) has also shown growth, focusing on productivity enhancements and tool reuse. With Lam’s extensive tool installations in both DRAM and NAND, customers are prioritizing upgrades over entirely new systems, especially as they look to improve cost efficiency during NAND’s down cycle. This focus on tool reuse has led to recent market share gains for Lam, as existing tools are upgraded for better value than new installations.

As DRAM and NAND customers intensify efforts to reduce costs, Lam’s service-oriented model and productivity solutions, including equipment intelligence services, have seen greater adoption. This trend underscores Lam's ability to support its customers' evolving needs in an era of increased etch and deposition intensity.

Lam Research Leverages ALD for Moly Transition in NAND, Driving Next-Gen Semiconductor Performance

Lam Research's perspective on ALD is optimistic, particularly as it becomes increasingly essential in NAND technology upgrades. The company highlighted the industry's ongoing shift from tungsten to molybdenum (moly) for improved resistivity in 3D NAND structures, a transition that Lam’s ALD technology is well-positioned to support. Lam has already secured production wins for ALD applications with molybdenum, expected to ramp up significantly in 2025. This capability extends beyond NAND, with potential applications in DRAM and advanced logic/foundry nodes, underscoring ALD’s growing importance in meeting next-generation semiconductor demands.

Lam Research Adapts to Regulatory Challenges as China Revenue Set to Decline in 2025

In its Q1 2025 earnings presentation, Lam Research highlighted key developments and expectations for the China market. China accounted for roughly 37% of Lam's revenue in the September quarter, but the company anticipates this share will decrease to around 30% by December and potentially decline further in 2025. This projected downturn reflects both anticipated shifts in demand and the impact of U.S. export restrictions on advanced semiconductor equipment sales to China. Lam acknowledged the challenges posed by ongoing and potential new U.S. export controls, which could limit its ability to sell to certain advanced technology segments in China. Nevertheless, Lam remains committed to supporting its domestic Chinese customers within the boundaries of regulatory compliance, expecting demand in restricted segments to normalize as global WFE (wafer fabrication equipment) spending adjusts.

Much of Lam's business in China now focuses on servicing domestic fabs with tools for trailing-edge and specialty node processes, areas that generally remain unaffected by export controls. Through its Reliant product line, Lam continues to support these nodes, emphasizing upgrades and maintenance services as primary offerings in a market constrained by new advanced technology sales. Despite potential reductions in advanced equipment sales, the company is confident that its service and support model will help stabilize revenue in the region. By prioritizing productivity solutions and customer support, Lam is adapting to a complex regulatory environment while anticipating that China’s share of its revenue will gradually normalize amid a broader decline in WFE spending in the country.

Strategic Positioning in 2025 and Beyond

In summary, Lam Research is set to capitalize on a growing demand for etch and deposition technology driven by the industry’s shift to advanced architectures. Archer concluded the call with optimism, stating that the company is well-positioned to capture market share as the semiconductor industry increasingly relies on complex, three-dimensional structures. With its advanced product offerings, Lam expects to outperform overall wafer fabrication equipment (WFE) growth in 2025, strengthening its leadership across multiple semiconductor sectors.

JSR Corporation Completes Strategic Acquisition of Yamanaka Hutech Corporation to Bolster Semiconductor Materials Portfolio with CVD and ALD Precursors

On August 2, 2024, JSR Corporation announced the successful acquisition of Yamanaka Hutech Corporation, a renowned supplier of high-purity chemicals for the semiconductor industry. The acquisition, finalized on August 1, 2024, positions YHC as a wholly-owned subsidiary of JSR. This strategic move allows JSR to enhance its product offerings, particularly in semiconductor film-forming technologies, and aligns with its growth strategy aimed at strengthening its presence in the advanced semiconductor materials sector. JSR is committed to driving innovation, optimizing supply chains, and maintaining strong customer relationships as the semiconductor industry undergoes significant changes.

JSR Corporation's acquisition of Yamanaka Hutech Corporation (YHC) brings YHC's high-purity CVD and ALD precursors into JSR's portfolio, enhancing its capabilities in semiconductor materials. YHC, with over 60 years of expertise in advanced molecular design and synthesis technology, has a strong track record in supplying high-quality CVD/ALD precursors, particularly in competitive ALD material areas. This acquisition allows JSR to diversify beyond its traditional focus on photoresists and strengthens its position as a global leader in advanced semiconductor materials, poised to drive innovation in both miniaturization and device structure advancements.

Sources:

JSR Completes Acquisition of All Shares in Yamanaka Hutech ~ Accelerating Semiconductor Materials Industry Reorganization~ | 2024 | News | JSR Corporation

JSR to make Yamanaka Hutech, a high-purity chemical for semiconductors, a wholly owned subsidiary ~Expanding the product portfolio in the field of cutting-edge semiconductor deposition~ | 2024 | News | JSR Corporation

Applied Materials Pioneer® CVD film for EUV Sculpta and DRAM Sym3 Etch applications

Applied Materials continues to lead in semiconductor technology with its introduction of the Producer® XP Pioneer® CVD patterning film at the SPIE Advanced Lithography + Patterning conference. This latest innovation is critical for DRAM scaling and EUV lithography, offering improved etch selectivity and pattern fidelity due to enhanced film density and stiffness. Optimized for use with the Sculpta® pattern-shaping system, Pioneer allows for advanced patterning capabilities, crucial for maintaining precise feature dimensions. With its adoption by leading foundry-logic and memory manufacturers, the Pioneer system is set to significantly enhance Applied Materials' portfolio and revenue, affirming its leadership in CVD technologies.

Applied Materials' Draco™ hard mask and Sym3® Y HT etch system have revolutionized DRAM production by enabling the etching of perfectly cylindrical capacitor holes, significantly enhancing etch selectivity and improving critical dimension uniformity, which contributes to a notable increase in the company's market share in DRAM.

Demand for DRAM innovation continues to grow to feed the insatiable need for memory bandwidth in the AI era. The recently launched Pioneer CVD patterning film has already been adopted by leading memory manufacturers for DRAM patterning. Pioneer is a completely new CVD architecture based on a unique high-density carbon formula that is more resilient to etch chemistries used in the most advanced process nodes, permitting thinner film stacks with superior sidewall feature uniformity.

A thinner hard mask means less vertical distance is required for etch, resulting in a lower aspect ratio. This allows use of lower-power plasma and offers better control of the ratio of ions to radicals. A higher concentration of ions produces more efficient etches with better control, allowing desired patterns to be transferred to the wafer with exceptional fidelity. Pioneer is also being co-optimized with Applied’s new Sym3® Y Magnum® etch system to provide better control over conventional carbon films for critical etch applications in memory processing.

For EUV Lithography the Pioneer CVD patterning film developed by Applied Materials addresses the stringent demands of EUV lithography by increasing film density and stiffness, which enhances etch selectivity and allows for finer pattern control, vital for the ultra-fine dimensions required in advanced chip manufacturing.

Source: Building on an Unmatched Foundation of CVD Innovation (appliedmaterials.com)

Applied Materials Unveils Cutting-Edge Patterning Technologies for Next-Gen Semiconductor Device Manufacturing

Applied Materials is leading the charge into the angstrom era of chipmaking, unveiling a suite of innovative solutions at the SPIE Advanced Lithography + Patterning conference. The company's focus is on overcoming the challenges posed by extreme ultraviolet (EUV) and high-NA EUV lithography, crucial for the production of chips at 2nm process nodes and below. Their approach integrates new materials engineering, metrology techniques, and pattern-shaping technology to enhance chip performance and yield.

To help overcome patterning challenges for leading-edge chips, Applied Materials offers a portfolio of technologies designed to complement the latest advances in lithography. The company’s newest innovations include the Producer® XP Pioneer® CVD patterning film, the Sym3® Y Magnum™ etch system, the Centura® Sculpta® pattern-shaping system and Aselta contour technology for design-based metrology.

Central to Applied Materials' advancements is the Sculpta® pattern-shaping technology, first introduced at the previous year's conference. Sculpta has seen growing adoption among top logic chipmakers for its ability to refine EUV patterning, notably reducing double patterning steps and mitigating defects such as bridge defects. This technology not only lowers patterning costs but also improves chip yields, showcasing its increasing importance in the semiconductor manufacturing landscape.

Over the next few years, chipmakers will be looking to create “angstrom era” chips that will use EUV and High-NA EUV lithography to pattern their smallest features. An entire ecosystem of capabilities will be required to enable this advanced patterning – including software and design tools, innovations in deposition and etch, advanced metrology and inspection systems, and entirely new approaches such as pattern shaping.

In response to the issue of EUV line edge roughness, Applied Materials has launched the Sym3® Y Magnum™ etch system. This innovative system employs a combination of deposition and etch processes within a single chamber to smooth out rough edges before etching, thereby enhancing yield and chip performance.

Additionally, the company introduced the Producer® XP Pioneer® CVD patterning film, designed for high-fidelity pattern transfer with enhanced resistance to etch chemistries. This film is especially significant for advanced process nodes, offering improved sidewall feature uniformity and co-optimization with both Sculpta and the Sym3 Y Magnum system for superior patterning capabilities.

To address the critical issue of feature alignment across chip layers, Applied Materials has acquired Aselta Nanographics, integrating its design-based metrology with Applied's leading eBeam systems. This integration enables a comprehensive metrology solution that significantly enhances feature placement accuracy, crucial for optimizing chip performance and yield.

Applied Materials' expansion of its patterning solutions portfolio underscores its commitment to advancing semiconductor technology. By addressing key challenges in EUV lithography and introducing groundbreaking technologies, the company is setting new standards for the industry, driving forward the capabilities of angstrom era chipmaking.

Source: Applied Materials Expands Patterning Solutions Portfolio for Angstrom Era Chipmaking | Applied Materials

Kokusai Electric's Successful IPO Raises $724.4 Million, Japan's Largest in 5 Years

Japanese chip equipment manufacturer Kokusai Electric has successfully raised $724.4 million through its initial public offering (IPO) by pricing its shares at the top end of a reduced marketing range. The IPO, Japan's largest in five years, saw Kokusai Electric value its shares at 1,840 yen per share, giving the company an overall valuation of 423.9 billion yen ($2.84 billion). The decision to lower the price range was influenced by the underwhelming performance of chip designer Arm's shares following its recent listing. Kokusai Electric's shares are set to debut on the Tokyo exchange's Prime Market on October 25. The company's major customers include Samsung Electronics, TSMC, and Micron Technology, accounting for over 40% of its revenue.

TSURUGI-C²® is a KOKUSAI ELECTRIC’s new thermal processing platform which is most recently developed for advanced devices especially for the ones with high aspect ratio 3D structures requiring high quality, uniform and conformal film deposition with new innovative reactor design and process techniques.

Kokusai Electric specializes in deposition and treatment process equipment for semiconductor manufacturing. Their deposition equipment is designed for creating nanoscale thin films on semiconductor wafers and supports technologies like LP-CVD, oxidation, annealing (low and high temperature), diffusion, and ALD. Notable products include TSURUGI-C², designed for advanced devices with complex 3D structures, AdvancedAce®-300 for batch thermal processing of 300mm wafers, and VERTRON® Revolution for 200-mm batch thermal processing.

Kokusai Electric's treatment equipment improves film properties through processes like nitridation, oxidation, curing, and annealing. MARORA® is ideal for gate dielectric film formation, utilizing plasma with low electron temperature. TANDUO® offers modular single-wafer treatment for various processes, and AdvancedAce®-300 supports LP-CVD, oxidation, annealing, and diffusion.

These equipment offerings are essential for semiconductor manufacturing, enabling the production of high-quality, high-performance components used in diverse electronic devices.

Sources:

Kokusai Electric raises $724.4 mln after setting IPO price at the top end of range | Reuters

Products＆Services | KOKUSAI ELECTRIC CORPORATION (kokusai-electric.com)

Aixtron’s G10-SiC CVD System Supports GlobiTech’s SiC Epitaxy Expansion

• GlobiTech Inc produces silicon carbide (SiC) and silicon epitaxial wafers, primarily focusing on serving the power and electric vehicle (EV) market segments.
• GlobiTech Inc's production facilities are located in Sherman, Texas, USA.

Aixtron SE is aiding Texas-based silicon-epitaxy foundry GlobiTech Inc's entry into the silicon carbide (SiC) epitaxy market. The G10-SiC chemical vapor deposition (CVD) system from Aixtron has enabled GlobiTech to rapidly scale SiC epitaxy production in response to growing demand for power epiwafers. Featuring dual wafer sizes (9x150mm and 6x200mm), it offers high throughput per fab space. GlobiTech's expansion confirms the trend of SiC replacing silicon in various applications. Both firms have enjoyed a fruitful partnership, with Aixtron's tools maximizing wafer output. The G10-SiC is projected to be Aixtron's top-selling product in 2023.

Aixtron G10-SiC (Source Aixtron.com)

Source: AIXTRON Pressemeldungen :: AIXTRON

Recent Blog posts on SiC:

BALD Engineering - Born in Finland, Born to ALD: SiC Market Soars Towards $9 Billion: EVs and High-Power Chargers Drive Growth

BALD Engineering - Born in Finland, Born to ALD: SiC Market Soars Towards $9 Billion: EVs and High-Power Chargers Drive Growth

BALD Engineering - Born in Finland, Born to ALD: Samco launches new ICP Tornado Plasma ALD system

BALD Engineering - Born in Finland, Born to ALD: ASM International has completed the acquisition of Italian Silicon Carbide Equipment Manufacturer LPE S.p.A.

BALD Engineering - Born in Finland, Born to ALD: Chemistry paves the way for improved electronic materials - LiU have developed a new molecule that can be used to create high-quality indium nitride

Background:

• Silicon carbide: from gold rush to commodity?¹, which provides an overview of the global SiC market and its predictions for the future of the technology. It discusses the growth rate, size, and drivers of the SiC device market, as well as the competitive landscape and supply chain of the SiC industry. It also analyzes the challenges and opportunities for SiC technology in different applications, such as automotive, industrial, energy, and telecommunications. It also compares and evaluates SiC with other wide bandgap materials, such as gallium nitride (GaN) and diamond.
• The 2023 global fab landscape: opportunities and obstacles², which considers the state of the global semiconductor fab market in a post-COVID world. It discusses the emerging business models that could enable the semiconductor industry to migrate to leading-edge and mature technology with optimal manufacturing capacity. It also examines the impact of COVID-19, trade wars, and geopolitical tensions on the semiconductor supply chain and fab investments. It also explores the trends and innovations in semiconductor materials, devices, and modules, such as silicon carbide (SiC), gallium nitride (GaN), and quantum computing.

Call for Papers on ALD & ALE Applications, at ECS Fall Meeting / Gothenburg Oct. 2023 ►►DEADLINE EXPIRES APRIL 21◄◄

Call for Papers on ALD & ALE Applications, at ECS Fall Meeting / Gothenburg Oct. 2023 ►►DEADLINE EXPIRES APRIL 21◄◄

The Electrochemical Society (ECS) conference is an international event running every spring and fall, and gathering 2000-4000 participants and 30-40 exhibitors both from academia and industry.

The conference has a strong focus on emerging technology and applications in both electrochemistry and solid-state science & technology.

This fall the event will be held as 244^th ECS Meeting on Oct. 8-12, 2023 in Gothenburg (Sweden).

The full program as well as information on travel assistance for students can be found on https://www.electrochem.org/244.

 

The organizers of symposium G01 on “Atomic Layer Deposition & Etching Applications, 19” encourage you to submit your abstracts on the following (and closely related) topics:

 

1.   Semiconductor CMOS applications: development and integration of ALD high-k oxides and metal electrodes with conventional and high-mobility channel materials;

2.   Volatile and non-volatile memory applications: extendibility, Flash, MIM, MIS, RF capacitors, etc.;

3.   Interconnects and contacts: integration of ALD films with Cu and low-k materials;

4.   Fundamentals of ALD processing: reaction mechanisms, in-situ measurement, modeling, theory;

5.   New precursors and delivery systems;

6.   Optical and photonic applications;

7.   Coating of nanoporous materials by ALD;

8.   MLD and hybrid ALD/MLD;

9.   ALD for energy conversion applications such as fuel cells, photovoltaics, etc.;

10. ALD for energy storage applications;

11. Productivity enhancement, scale-up and commercialization of ALD equipment and processes for rigid and flexible substrates, including roll-to-roll deposition;

12. Area-selective ALD;

13. Atomic Layer Etching (‘reverse ALD’) and related topics aiming at self-limited etching, such as atomic layer cleaning, etc.

 

Abstract submission

Meeting abstracts should be submitted not later than the deadline of April 21, 2023 via the ECS website: Abstract submission instruction

 

List of invited speakers

·   Johan Swerts, (Imec, Belgium) KEYNOTE: ALD challenges and opportunities in the light of future trends in electronics

·   Stephan Wege (Plasway Technology, Germany), Reactor design for combined ALD & ALE

·   Masanobu Honda (TEL, Japan), Novel surface reactions in low-temperature plasma etching

·   Barbara Hughes, (Forge Nano, USA), Dual Coatings, Triple the Benefit; Atomic Armor for Better Battery Performance

·   Juhani Taskinen, (Applied Materials-Picosun, Finland), ALD for biomedicine

·   Alex Kozen (Univ. of Maryland, USA), ALD for improved Lithium Ion Batteries

·   Malachi Noked (Bar-Ilan Univ., Israel), ALD/MLD for batteries

·   Yong Qin (Chinese Academy of Sciences), ALD for catalysis

·   Jan Macák, (Univ. of Pardubice, Czechia), ALD on nanotubular materials and applications

·   Bora Karasulu, Univ. of Warwick, UK), Atomistic Insights into Continuous and Area-Selective ALD Processes: First-principles Simulations of the Underpinning Surface Chemistry

·   Ageeth Bol (Univ. Michigan, USA), ALD on 2D materials

·   Pieter-Jan Wyndaele (KU Leuven-imec, Belgium), Enabling high-quality dielectric passivation on Monolayer WS₂ using a sacrificial Graphene Oxide template

·   Elton Graugnard (Boise State Univ., USA), Atomic Layer Processing of MoS₂

·   Han-Bo-Ram Lee (Incheon National Univ., Korea), Area-Selective Deposition using Homometallic Precursor Inhibitors

·   Ralf Tonner (Univ. Leipzig, Germany), Ab initio approaches to area-selective deposition

·   Nick Chittock (TU Eindhoven, Netherlands), Utilizing plasmas for isotropic Atomic Layer Etching

·   Heeyeop Chae (Sungkyunkwan Univ., Korea), Plasma-enhanced Atomic Layer Etching for Metals and Dielectric Materials

·   Charles Winter (Wayne State Univ., USA), New Precursors and Processes for the Thermal ALD of Metal Thin Films

·   Anjana Devi, Ruhr Univ. Bochum, Germany), Novel precursors dedicated for Atomic Layer Processing

 

Visa and travel

For more information, see: www.electrochem.org/244/visa-travel/

In addition, Mrs. Francesca Spagnuolo at the ECS (Francesca.Spagnuolo@electrochem.org) can provide you with an official participation letter from the site of the Electrochemical Society.

 

We are looking forward to meeting you in Gothenburg !

Samsung to focus on treatment of gas used in chip production to achieve net-zero emissions

A major cause of greenhouse gas emissions is process gas used in semiconductor wafer manufacturing comes from processing equipment such as reactive ion etching (RIE) and deposition (CVD and ALD). You can read and watch an interview here and study that paper that was recently published by me and my professor friends Henrik Pedersen and Sean Barry:

BALD Engineering - Born in Finland, Born to ALD: Green CVD: How Sustainable is Thin Film Deposition?

Green CVD-Toward a sustainable philosophy for thin film deposition by chemical vapor deposition

It is almost obvious that higher VPs at Samsung and TSMC (LINK) did just that ;-)

[Korea Herald, Link below] Advancing abatement technologies to reduce carbon emissions is the top priority in the Samsung Electronics semiconductor unit's goal to become carbon neutral by 2050, a top official said Friday.

"Treatment of gas used to manufacture semiconductor chips is our biggest focus in our spending (to achieve net-zero emissions)," Song Doo-guen, executive vice president and head of the Environment ＆ Safety Center at Samsung Electronics, told reporters at a briefing in Seoul.

According to the article, Song Doo-guen, executive vice president and head of the Environment & Safety Center at Samsung Electronics, speaks at a briefing in Seoul, Friday and announced that:

• Samsung has pledged a 7 trillion won ($5 billion) investment to achieve its climate ambitions, and announced that it had recently joined RE100, a coalition comprising 380 global enterprises committed to becoming 100 percent renewable.
• Alongside the plan to cut direct carbon emissions, Samsung has also laid out a raft of plans to reduce indirect emissions, mainly by pursuing ultralow-power chip products.
• Other eco-conscious plans it has drawn up include capping the maximum use of freshwater to 300,000 tons a day by 2030 and eradicating gaseous and liquid pollutants by 2040 with treatment technology.

Source: Samsung chip plants look to stamp out carbon footprint (koreaherald.com)