Sunday, June 21, 2015

A Novel ALD SiBCN Low-k Spacer for FinFETs presented at VLSI 2015 in Kyoto

A key challenge in reducing capacitance around the transistor is incorporating spacer and contact etch stop materials that are simultaneously low-k and robust to processing. One approach is to develop new low-k materials that can withstand the processing conditions [IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 7, JULY 2012]

A Novel ALD SiBCN Low-k Spacer for FinFETs presented at VLSI 2015 in Kyoto by IBM and Globalfoundries. The abstract does not give too many details on the ALD process itself except that it is a "a novel low temperature ALD-based SiBCN material has been identified". However, the conference proceeding states that the SiBCN is deposited in a batch furnace:
  • SiBCN low k spacer was deposited in a batch furnace at 600 °C. The referral to low thermal process here may relate to earlier CVD processes at higher process temperatures.
  • The process was run in thermal ALD mode with alternating layers of BN and SiCN. 
  • The B/C ratio in the film was controlled by adjusting the BN:SiCN cycle ratio

A Novel ALD SiBCN Low-k Spacer for Parasitic Capacitance Reduction in FinFETs

T. Yamashita*, S. Mehta*, V. S. Basker*, R. Southwick*, A. Kumar**, R. Kambhampati*** , R. Sathiyanarayanan**, J. Johnson**, T. Hook*, S. Cohen*, J. Li*, A. Madan*, Z. Zhu*, L. Tai*, Y. Yao*, P. Chinthamanipeta*, M. Hopstaken*, Z. Liu*, D. Lu*, F. Chen**, S. Khan**, D. Canaperi*, B. Haran*, J. Stathis*, P. Oldiges*, C.-H. Lin*, S. Narasimha**, A. Bryant*, W. K. Henson**, S. Kanakasabapathy*, K. V. R. M. Murali**, T. Gow*, D. McHerron*, H. Bu* and M. Khare*, *IBM Research, **IBM SRDC and ***GLOBALFOUNDRIES, USA 

FinFET has become the mainstream logic device architecture in recent technology nodes due to its superior electrostatic and leakage control. However, parasitic capacitance has been a key performance detractor in 3D FinFETs. In this work, a novel low temperature ALD-based SiBCN material has been identified, with an optimized spacer RIE process developed to preserve the low-k value and provide compatibility with the down-stream processes. The material has been integrated into a manufacturable 14nm replacement-metal-gate (RMG) FinFET baseline with a demonstrated ~8% performance improvement in the RO delay with reliability meeting the technology requirement. A guideline for spacer design consideration for 10nm node and beyond is also provided based on the comprehensive material properties and reliability evaluations.

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