Wednesday, December 11, 2019

Imec shows excellent performance in ultra-scaled FETs with 2D-material channel

[Press release, imec, LINK] SAN FRANCISCO (USA), December 8, 2019 — At this year’s IEEE International Electron Devices Meeting (Dec 7-11 2019), imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, reports an in-depth study of scaled transistors with MoS2 and demonstrates best device performance to date for such materials. 

TEM pictures showing (a) 3 monolayers MoS2 channel, with contact length 13nm and channel length 29nm Transfer characteristics have improved sub-threshold swing (SS) with thinner HfO2. (www.imec.be)

MoS2 is a 2D material, meaning that it can be grown in stable form with nearly atomic thickness and atomic precision. Imec synthesized the material down to monolayer (0.6nm thickness) and fabricated devices with scaled contact and channel length, as small as 13nm and 30nm respectively. These very scaled dimensions, combined with scaled gate oxide thickness and high K dielectric, have enabled the demonstration of some of the best device performances so far. Most importantly, these transistors enable a comprehensive study of fundamental device properties and calibration of TCAD models. The calibrated TCAD model is used to propose a realistic path for performance improvement. The results presented here confirm the potential of 2D-materials for extreme transistor scaling – benefiting both high-performance logic and memory applications.



Theoretical studies recommend 2D materials as the perfect channel material for extreme transistor scaling as only little short channel effects are expected compared to the current Si-based devices. Hints of this potential have already been published with one-of-a-kind transistors built on natural flakes of 2D materials.

For the first time, imec has tested these theoretical findings through a comprehensive set of 2D-materials-based transistor data. The devices with the smallest footprint have a channel length of 30nm and <50nm contact pitch. ON current as high as 250µA/µm has been demonstrated with 50nm SiO2 gate dielectric. On current of ~ 100 µA/µm and an excellent SSmin of 80mV/dec (for VD =50mV) have been demonstrated with 4nm HfO2 in a backgated configuration. The device performance is not impacted by contact length scaling, confirming that carriers are injected from the edge of the contact metal directly into the channel, in line with TCAD simulations. The work confirms that TCAD models capture large parts of device physics and guide experimental validation and mapping the application space. Part of the paper that is presented at IEDM, is dedicated to setting the path for device optimization for reaching Si-like performance targets.

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