Tuesday, July 14, 2015

Advanced Metallization Scheme for 3 x 50 um TSV Middle Process – IMEC

Here are some highly interesting insights to the latest Imec process technology for TSVs using a number of advanced Lam Research processing platforms including ALD - As reported by Solid State Technology, By Dr. Phil Garrou, Contributing Editor (I spiced it up with some nice Lam  Research chamber pictures): 

Scaling down the TSV diameter from 5μm to 3μm is very attractive for the 3D IC implementation in more advanced CMOS nodes. For instance, stress caused by the mismatch between the coefficient of thermal extension (CTE) of Si and Cu may generate strain in the Si around the TSV, degrading the device performance of transistors located close to a TSV. To reduce the impact on transistors, a so called keep-out-zone (KOZ), is generally defined around the 3D TSVs. This keepout-zone is however significantly smaller when scaling down the TSV diameter from 5μm to 3μm. When increasing the aspect ratio of the TSV from 10:1 to 17:1 (for 3μm diameter and 50μm depth), the conventional PVD barrier and seed options reach their conformality limits. Very thick barrier/seed layers need to be deposited in order to assure a continuous film at the bottom of the TSV. This not only fundamentally limits the extendibility of this integration scheme, but also increases the PVD deposition cost itself and the required CMP time, among other technical challenges. For these reasons, a new advanced and scalable TSV metallization scheme was developed.

Atomic layer deposition (ALD) has emerged as a key enabling technology for conformal film applications such as TSV oxide liner. Typical step coverage or conformality of other CVD oxide films is only 60-75% for high aspect ratio TSVs . In contrast, the VECTOR ALD oxide film shows 100% con formality.

Lam Research VECTOR ALD process chambers (www.lamresearch.com)

ALD WN serves as a barrier layer and is deposited on the Altus Max tool. It is highly conformal with >90% step coverage regardless of geometry. ALD WN is deposited at 375°C and has excellent adhesion to ALD oxide and subsequent ELD NiB. The conformality of the ALD process results in a pinhole-free WN layer, as opposed to barriers deposited by PVD, which potentially struggle with pinholes at the bottom of high aspect ratio TSV.

Lam Research Altus Max Chambers (www.lamresearch.com)

NiB electroless deposition on WN barrier was carried out on a Lam ELD2300 tool using a plating chemistry developed at Lam. The entire deposition process was made of several sequential steps such as a brief pre-clean, activation, deposition, rinse and dry. The concentration of reducing agent and nickel ions as well as the pH and temperature are controlled to maintain optimum deposition condition for seed formation during the NiB deposition. After deposition of ELD NiB, TSV copper electrofill is processed on a Lam SABRE 3D electroplating system using an industry standard acid copper sulfate electrolyte with a Lam

Lam Research SABRE 3D Electroplating system (www.lamresearch.com)

exclusive organic additive package. The conductivity and corrosion resistance of the Lam ELD NiB film enable compatibility with the electrofill process on 300mm wafer scale. Bottom-up fill of the vias proceeds without the need for the additional copper seed film that has been used with other conformal metal liners (e.g. Co or Ru).

Because of the high conformality of liner, barrier and seed layers, this proposed Via-middle metallization scheme is believed to be scalable to even higher aspect ratio TSVs with 2μm diameter.


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  3. Such A nice post... thanks For Sharing !!Great information for new guy like Happy New year 2020