Thursday, July 23, 2015

EUV, Atomic Layer Processes and KLA to solve all all Fab Issues at 7 nm and 5 nm

Here is yet another great article in Semiconductor Engineering by Mark Lapedus on the "The race toward the 7nm logic node. He systematically go through and summarize all important issues and technologies and news from SEMICON West from EUV via ALD to KLA ;-)

New technologies after finFETs and how the industry is likely to get there if it can resolve some very tough issues.

The race toward the 7nm logic node officially kicked off in July, when IBM Research, GlobalFoundries and Samsung jointly rolled out what the companies claim are the industry’s first 7nm test chips with functional transistors.

They’re not alone, of course. Intel and TSMC also are racing separately to develop 7nm technology. And in the R&D labs, chipmakers also are working on technologies for 5nm and beyond. Needless to say, the timing and certainty of 7nm and 5nm remain unclear.

In any case, there are two basic transistor candidates at 7nm—the finFETand the lateral gate-all-around nanowire FET, sometimes called the lateral nanowire FET. And at 5nm, the industry is leaning towards the lateral nanowire FET.

  • Patterning and mask making - EUV, LER
  • Fab flow and variation - CMP
  • Selective processes - ALD, MLD, ALE
  • Interconnects - RC
  • Inspection and metrology - KLA
While you´re at it you should also read this article by Mark Lapedus : 

What Will 7nm And 5nm Look Like? - Delays at 10nm raise questions about what’s next.

Today, the lateral nanowire FET is the sole option at 5nm, according to Imec. Vertical FETs, TFETs and the other technologies have been pushed out to 3nm (!)

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