Showing posts with label TSV. Show all posts
Showing posts with label TSV. Show all posts

Monday, July 27, 2015

Hynix high bandwidth memory in an AMD Radeon ALD High-k Fury

Check it out - this is like the coolest thing I have ever seen so far - the two leading ALD High-k products (DRAM & High performance CMOS) merged into one ultra high performance graphics chip by AMD. TechInsights has investigated the AMD Fury X cards in their lab  and published it in a series of articles in EE Times:

The Hunt for Hynix HBM - Hynix high bandwidth memory addresses bandwidth limitations

Accordingly, SK Hynix announced its high bandwidth memory (HBM) product in early 2014, claiming it to be the world’s first 8Gb module made using 2Gb, 20nm node, DDR4 SDRAM. Now the HBM modules has shown up in product - AMD’s Radeon 390X Fury X graphics card.

According to TechInsight : "Hynix disclosed a via middle process for their HBM in two papers (Electronics Components & Technology Conference 2013 and VLSI Tech. Digest 2014). The TSV openings are formed after the tungsten contacts to the gates and source/drain regions are made, using a Bosch TSV etch. An oxide liner is then deposited along the via sidewalls, lined with a Ta-based barrier and Cu seed layers, and filled with electroplated Cu. A thermal anneal process is used as a Cu stress relief. A CMP and etch process is used to thin the backsides of the DRAM wafer and expose the Cu TSVs. The backsides of the DRAM wafers are then passivated with oxide, followed by the formation of the backside micro bumps."

AMD Radeon Fury X (Source: TechInsights)

Some facts from the reports:

  • The GPU die has four Hynix HBM memory modules arranged around its perimeter. 
  • Both the GPU and the HBM modules are flip-chip bumped to a UMC fabbed interposer. 
  • The interposer is, in turn, bumped to a laminate substrate. 
  • The GPU itself is a massive measuring in at 23mm by 27mm large, and is believed to be fabricated using TSMC’s 28nm HKMG process.

"The GPU die is seen in the center of the module with four Hynix HBM memory modules arranged around its perimeter. Both the GPU and the HBM modules are flip-chip bumped to a UMC fabbed interposer. This interposer is, in turn, bumped to a laminate substrate. The GPU is massive measuring in at 23mm by 27mm large, and is believed to be fabricated using TSMC’s 28nm HKMG process." (EE Times, TechInsight)

Schematic cross section of HBM module. (Source: AMD HBM brochure, TechInsights)

Hynix HBM memory (Source: Package Analysis of the SK-Hynix HBM, TechInsights)

Tuesday, July 14, 2015

Advanced Metallization Scheme for 3 x 50 um TSV Middle Process – IMEC

Here are some highly interesting insights to the latest Imec process technology for TSVs using a number of advanced Lam Research processing platforms including ALD - As reported by Solid State Technology, By Dr. Phil Garrou, Contributing Editor (I spiced it up with some nice Lam  Research chamber pictures): 

Scaling down the TSV diameter from 5μm to 3μm is very attractive for the 3D IC implementation in more advanced CMOS nodes. For instance, stress caused by the mismatch between the coefficient of thermal extension (CTE) of Si and Cu may generate strain in the Si around the TSV, degrading the device performance of transistors located close to a TSV. To reduce the impact on transistors, a so called keep-out-zone (KOZ), is generally defined around the 3D TSVs. This keepout-zone is however significantly smaller when scaling down the TSV diameter from 5μm to 3μm. When increasing the aspect ratio of the TSV from 10:1 to 17:1 (for 3μm diameter and 50μm depth), the conventional PVD barrier and seed options reach their conformality limits. Very thick barrier/seed layers need to be deposited in order to assure a continuous film at the bottom of the TSV. This not only fundamentally limits the extendibility of this integration scheme, but also increases the PVD deposition cost itself and the required CMP time, among other technical challenges. For these reasons, a new advanced and scalable TSV metallization scheme was developed.

Atomic layer deposition (ALD) has emerged as a key enabling technology for conformal film applications such as TSV oxide liner. Typical step coverage or conformality of other CVD oxide films is only 60-75% for high aspect ratio TSVs . In contrast, the VECTOR ALD oxide film shows 100% con formality.

Lam Research VECTOR ALD process chambers (

ALD WN serves as a barrier layer and is deposited on the Altus Max tool. It is highly conformal with >90% step coverage regardless of geometry. ALD WN is deposited at 375°C and has excellent adhesion to ALD oxide and subsequent ELD NiB. The conformality of the ALD process results in a pinhole-free WN layer, as opposed to barriers deposited by PVD, which potentially struggle with pinholes at the bottom of high aspect ratio TSV.

Lam Research Altus Max Chambers (

NiB electroless deposition on WN barrier was carried out on a Lam ELD2300 tool using a plating chemistry developed at Lam. The entire deposition process was made of several sequential steps such as a brief pre-clean, activation, deposition, rinse and dry. The concentration of reducing agent and nickel ions as well as the pH and temperature are controlled to maintain optimum deposition condition for seed formation during the NiB deposition. After deposition of ELD NiB, TSV copper electrofill is processed on a Lam SABRE 3D electroplating system using an industry standard acid copper sulfate electrolyte with a Lam

Lam Research SABRE 3D Electroplating system (

exclusive organic additive package. The conductivity and corrosion resistance of the Lam ELD NiB film enable compatibility with the electrofill process on 300mm wafer scale. Bottom-up fill of the vias proceeds without the need for the additional copper seed film that has been used with other conformal metal liners (e.g. Co or Ru).

Because of the high conformality of liner, barrier and seed layers, this proposed Via-middle metallization scheme is believed to be scalable to even higher aspect ratio TSVs with 2μm diameter.

Monday, July 13, 2015

Lam Research Releases High-Productivity VECTOR(R) ALD Oxide Deposition System

Lam Research Corp a major global supplier of innovative wafer fabrication equipment and services to the semiconductor industry, today announced it has released its high-productivity VECTOR® ALD Oxide system on the Extreme platform. The new product uses atomic layer deposition (ALD) to create highly conformal dielectric films with an emphasis on advanced patterning, in particular spacer-based multiple patterning. One key challenge is managing thickness variability of the self-aligned spacers that define critical dimensions (CDs). By delivering superior CD control, VECTOR ALD Oxide has been winning volume-production decisions for multi-patterning applications. Now leveraging Lam's Extreme platform, the latest system meets productivity requirements for continued scaling, where additional steps increase process time, cost, and complexity. As a result, VECTOR ALD Oxide is gaining rapid adoption by a number of leading chipmakers for advanced multi-step patterning applications.

"Multiple patterning continues to be a key inflection for the industry, and spacer-based multi-patterning remains an enabling strategy for chipmakers for both current immersion and future EUV lithography schemes," said Sesha Varadarajan, group vice president, Deposition Product Group. "With this in mind, we are working closely with our customers to deliver cost-effective, extendible solutions required for further scaling, such as the high-productivity atomic-scale control from our VECTOR ALD Oxide product."

By repeating lithography/etch/deposition steps, multiple patterning techniques create smaller features and higher feature densities compared to the capability of current optical lithography using single patterning. To enable scaling for 14 nm and below, chipmakers are adopting self-aligned schemes, including self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP), where deposition plays a critical role in forming the pattern-defining spacers. These deposition processes are challenging since they must form high-quality conformal and very uniform films. For example, a 200-300 angstrom-thick film can have only a few angstroms thickness variation across the wafer. For next-generation 10 nm processes, the manufacturing complexity will continue to increase as additional multi-patterning process steps are added, with each step contributing to overall CD variability.

Using Lam's advanced ALD capabilities, the latest VECTOR ALD Oxide system delivers the uniformity required for CD control of the ultra-thin films critical to SADP and SAQP schemes. The quad-station modules process four wafers simultaneously and share components to improve reliability and chamber matching, contributing to industry-leading wafer-to-wafer repeatability performance. The system's compact design delivers as much as 20% higher footprint productivity compared with other solutions. Process hardware has also been optimized to enable fast gas and RF switching, increasing throughput and reducing precursor usage for improved running costs. These innovative process module features combined with the high-productivity platform deliver the performance and cost-efficiency needed for manufacturing. Consequently, VECTOR ALD Oxide is winning development and production tool of record positions at leading manufacturers for advanced multi-patterning applications. This momentum is being successfully expanded to other applications, such as high-aspect ratio liners for through-silicon vias (TSVs) and image sensors.

Thursday, May 29, 2014

Applied Materials Enables Cost-Effective Vertical Integration of 3D Chips by PVD

As reported by Applied Materials: SANTA CLARA, Calif., May 28, 2014 - Applied Materials, Inc. today introduced the Endura® VenturaTM PVD system that helps customers reduce the cost of fabricating smaller, lower power, high-performance integrated 3D chips. The system incorporates Applied's latest innovations to its industry-leading PVD technology that enables the deposition of thin, continuous barrier and seed layers in through-silicon-vias (TSVs). Demonstrating Applied's precision materials engineering expertise, the Ventura system also uniquely supports the use of titanium in volume production as an alternate barrier material for lower cost. With the launch of the Ventura system, Applied is expanding its comprehensive toolset for wafer level packaging (WLP) applications, including TSVs, redistribution layer (RDL) and Bump.
"Ventura provides a less expensive barrier for copper, as well as the copper seed layer necessary for the subsequent through copper plating process itself. Typical copper interconnects on-chip are very very small -- on the order of 50 nanometers -- but TSVs are much larger -- on the order of 50 microns. Ventura can safely address aspect rations of TSVs ranging from typical TSVs today of 5-to-1 to those of the future of 10-, 11-, and even 12-to-1 aspect ratios. The Ventura tool can also handle traditional tantalum liners for TSVs as well as the more cost-effective titanium TSV liners, before depositing the copper seeds for the eventual polished interconnect itself. Applied materials also claims twice the throughput of competing PVD interconnect tools, and says it has already shipped 30 Ventura chambers in the last 18 months" (Source EE Times)
TSVs are a critical technology for vertically fabricating smaller and lower power future mobile and high-bandwidth devices. Vias are short vertical interconnects that pass through the silicon wafer, connecting the active side of the device to the back side of the die, providing the shortest interconnect path between multiple chips. Integrating 3D stacked devices requires greater than 10:1 aspect ratio TSV interconnect structures to be metallized with copper. The new Ventura tool solves this challenge with innovations in materials and deposition technology to manufacture TSVs more cost-effectively than previous industry solutions.

Applied Materials' Sesh Ramaswami discusses the fundamentals of advanced packaging and the revolutionary impact this technology is having on the gadgets we buy and the cloud infrastructure that makes mobility work. ( 
"Building on 15 years of leadership in copper interconnect technology, the Ventura system enables fabrication of robust high-aspect ratio TSVs, with up to 50 percent barrier seed cost savings compared to copper interconnect PVD systems," said Dr. Sundar Ramamurthy, vice president and general manager of Metal Deposition Products at Applied Materials. "These innovations deliver a higher-performance and more functional, yet, compact chip package with less power consumption to meet leading-edge computing needs. Customers are realizing the benefits of this new PVD system and are qualifying it for volume manufacturing."
Supporting the manufacture of high-yielding 3D chips, the Ventura system introduces advances in ionized PVD technology that assure the integrity of the barrier and seed layers that are critical to superior gap-fill and interconnect reliability. These developments significantly improve ion directionality to enable the deposition of thin, continuous and uniform metal layers deep into the vias to achieve the void-free fill necessary for robust TSVs. With the improvement in directionality, higher deposition rates can be achieved, while the amount of barrier and seed material needed can be reduced. These attributes of the Ventura system and the adoption of titanium as an alternate barrier are expected to improve device reliability and reduce the overall cost of ownership for TSV metallization.