Showing posts with label PVD. Show all posts
Showing posts with label PVD. Show all posts

Wednesday, September 20, 2023

Plasma-Therm Strengthens Power Electronics Presence with Acquisition of Thin Film Equipment SrL

Plasma-Therm, a prominent manufacturer of plasma-process equipment for the semiconductor industry, has announced its acquisition of Thin Film Equipment SrL (TFE) on September 18, 2023. TFE, based in Binasco, Italy, specializes in supplying sputtering equipment for semiconductor research and production, particularly in physical vapor deposition (PVD) sputtering and evaporation process equipment and high purity materials for thin film applications.

This acquisition is part of Plasma-Therm's strategy to expand its presence in Europe and strengthen its position in the power device market. TFE's suite of PVD tools, catering to MEMS, Power, RFID, and other semiconductor applications, complements Plasma-Therm's existing product portfolio in etch and deposition. Additionally, TFE's expertise in PVD technology enhances Plasma-Therm's customer service and support capabilities.

The power semiconductor market is expected to grow substantially, reaching $6.3 billion by 2027, according to The Yole Group's "Power SiC 2022" report. Plasma-Therm is well-positioned to support this growth with the acquisition of TFE and its MRC Eclipse product line.

TFE will continue to operate independently but will collaborate closely with Plasma-Therm to offer a more comprehensive range of plasma and PVD process technology solutions to customers. This acquisition will also enable both companies to expand their R&D resources and global customer service and support teams.

Plasma-Therm is a global manufacturer of advanced plasma processing equipment, serving various industries, including wireless, power devices, MEMS, photonics, advanced packaging, and data storage. It has locations in North America, Europe, and Asia-Pacific.

TFE SrL, founded in 1996, is a leading supplier of sputtering equipment for R&D and production, known for its flexibility, reliability, process knowledge, and a large worldwide installed base.

Source: Plasma-Therm Announces Acquisition of Thin Film Equipment (

Saturday, November 23, 2019

Cobalt and Nickel Targets Super Strategic for IC Fabs

[Press Release, TECHCET LLC] San Diego, CA, November 14, 2019: TECHCET-the advisory services firm providing electronic materials information- announced that the global market for Physical Vapor Deposition (PVD) Sputter Targets is declining by 1.5% in response to semiconductor fabrication market challenges in 2019. However, 5% growth is forecasted for 2020, with the non-precious-metal segment expected to reach US$690 million. 
Including precious metals the 2020 Sputter Target market is expected to reach US$1,084 million, as detailed in the latest Critical Materials Report™ (CMR) quarterly update on Sputter Targets (see Figure). This report covers the following suppliers: Furuya Metals, GO Element, Grikin, Honeywell, JX Nippon, KFMI, Materion, Pioneer Materials, Praxair/Linde, Sumitomo, Tanaka, Top Metal Materials, Tosoh SMD, Solar Applied Materials Technology, Umicore, VEM, and Vital Materials.

Purchase Reports Here:

Tuesday, July 16, 2019

Endura Impulse - Applied Materials’ New Memory Machines

Tools designed to rapidly build embedded MRAM, RRAM, and phase change memories on logic chips expand foundry options

Applied Materials unveiled Endura Impulse System incorporating nine physical vapor deposition reactors to rapidly build STT-MRAM, RRAM or PCRAM, on 9 July at Semicon West, in San Francisco.
Chip equipment giant Applied Materials wants foundry companies to know that it feels their pain. Continuing down the traditional Moore's Law path of increasing the density of transistors on a chip is too expensive for all but the three richest players—Intel, Samsung, and TSMC. So to keep the customers coming, other foundries can instead add new features, such as the ability to embed new non-volatile memories—RRAM, phase change memory, and MRAM—right on the processor. 
The trouble is, those are really hard things to make at scale. So, Applied has invented a pair of machines that boost throughput by more than an order of magnitude.

Applied Materials' Endura Impulse uses nine physical vapor deposition systems to rapidly build RRAM or PCRAM. Photo: Applied Materials 
Source: Applied Materials LINK
By Abhishekkumkar Thakur 

Tuesday, September 18, 2018

IITC-MAM2019 First Call for Papers

The 22nd edition of the International Interconnect Technology Conference (IITC) is sponsored by the IEEE Electron Devices Society as the premier conference for interconnect technology. The 28th edition of the Materials for Advanced Metallization workshop (MAM) is devoted to research on materials properties and interactions of interconnect and silicide materials. These two conferences will be combined again in 2019 for the 3rd joint IITC-MAM conference and feature compelling invited talks and be proceeded by a materials workshop. 

Authors are encouraged to submit their original work describing innovative research and development in the critically important felid of on-chip interconnects. The conference seeks papers on all aspects of BEOL/MOL interconnects and metallization, including design, unit process, integration and reliability.


  • Advanced interconnects with low-k dielectrics
  • Beyond Cu interconnect, optical, wireless, and carbon
  • Contacts to MOS devices: Silicide, III-V, 2D materials
  • BEOL elements for Memory: 3D NAND, CBRAM, PCRAM, ReRAM, MRAM, DRAM
  • Advanced packaging and 3D/2.5D integration: WtW/CtW bonding, Interposer, TSV, CPI, Fan-Out techniques, Integrated Fan-Out
  • Smart technologies for interconnects: AI/neuromorphic, machine learning, big data.
  • Process integration, advanced patterning for MOL/BEOL
  • Materials and Unit Processes: dielectrics, metals, barriers, wet, CMP, PVD, CVD, ALD, selective deposition/SAMs
  • Reliability and Failure analysis, techniques and methods
  • Advanced characterization: material analysis, analytical techniques, process modelling, defectivity, EPE
  • System scaling: design-technology co-optimization, embedded functionalities (memory, MEMS, Sensors...) Novel Systems/form factors: flexible, wearables, etc.
More information: LINK

Monday, August 20, 2018

Overview of Applied Materials cobalt metallization for local interconnects

For those of you interested in the details behind the Applied Materials integrated cobalt metallization process Jonathan Bakke has written two informative blogs about it in Semiconductror Engineering:

(1) The Role Of Cobalt In Enabling AI - For continued performance, power, area and cost improvements, materials need to be engineered at the atomic scale.
(2) The Materials Side Of AI - What comes after tungsten fill for contacts and copper for the lowest-level interconnects?
The integrated cobalt solution using Applied Materials platforms (Applied Materials).

Jonathan Bakke is global product manager for Contact and Middle of Line Products in the Metal Deposition Products Business Unit at Applied Materials. He details the process flow and tool sets from Applied Materials involved in the complete BEOL Co metallization flow:

  • PVD titanium and ALD titanium nitride for the silicide and barrier layers
  • PVD cobalt serves as an anchor layer to ensure good cobalt adhesion to the bottom of the feature
  • CVD cobalt is then used to deposit a conformal film to bulk fill the feature
  • Anneal purifies and reflows the cobalt, removes the CVD seam, and merges crystal grains to form a more crystalline, lower resistance material
  • PVD cobalt for a thick overburden film
  • CMP removes overburden materials to create a smooth planar surface
  • E-beam technology monitors the process and detects voids

Wednesday, June 6, 2018

Imec Extends Damascene Metallization Towards the 3nm Technology Node

LEUVEN, June 4, 2018 – At this week’s 2018 IEEE International Interconnect Technology Conference (IITC 2018), imec, the world-leading research and innovation hub in nanoelectronics and digital technology, will present 11 papers on advanced interconnects, ranging from extending Cu and Co damascene metallization, all the way to evaluating new alternatives such as Ru and graphene. After careful evaluation of the resistance and reliability behavior, imec takes first steps towards extending conventional metallization into to the 3nm technology node.

For almost two decades, Cu-based dual damascene has been the workhorse industrial process flow for building reliable interconnects. But when downscaling logic device technology towards the 5nm and 3nm technology nodes, meeting resistance and reliability requirements for the tightly pitched Cu lines has become increasingly challenging. The industry is however in favor of extending the current damascene technology as long as possible, and therefore, different solutions have emerged. 
Via resistance for Co, Cu, Ru (left); and comparison of damascene line resistance versus total conductor cross-sections area of Ru, Co and Cu nanowires (right)
To set the limits of scaling, imec has benchmarked the resistance of Cu with respect to Co and Ru in a damascene vehicle with scaled dimensions, demonstrating that Cu still outperforms Co for wire cross sections down to 300nm2 (or linewidths of 12nm), which corresponds to the 3nm technology node. To meet reliability requirements, one option is to use Cu in combination with thin diffusion barriers such as tantalum nitride (TaN)) and liners such as Co or Ru. It was found that the TaN diffusion barrier can be scaled to below 2nm while maintaining excellent Cu diffusion barrier properties.

For Cu linewidths down to 15–12nm, imec also modeled the impact of the interconnect line-edge roughness on the system-level performance. Line-edge roughness is caused by the lithographic and patterning steps of interconnect wires, resulting in small variations in wire width and spacing. At small pitches, these can affect the Cu interconnect resistance and variability. Although there is a significant impact of line-edge roughness on the resistance distribution for short Cu wires, the effect largely averages out at the system level.

An alternative solution to extend the traditional damascene flow is replacing Cu by Co. Today Co requires a diffusion barrier – an option that recently gained industrial acceptance. A next possible step is to enable barrierless Co or at least sub-nm barrier thickness with careful interface engineering. Co has the clear advantage of having a lower resistance for smaller wire cross-secions and smaller vias. Based on electromigration and thermal storage experiments, imec presents a detailed study of the mechanisms that impact Co via reliability, showing the abscence of voids in barrierless Co vias, demonstrating a better scalability of Co towards smaller nodes. The research is performed in cooperation with imec’s key nano interconnect program partners including GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, SanDisk/Western Digital, Sony Semiconductor Solutions, TOSHIBA Memory and TSMC.

Applied Materials enables cobalt contact & interconnect for 7nm with pre-clean, PVD, ALD and CVD – on the Endura® platform

At IEDM 2017 in December both Intel and Globalfoundries presented cobalt encapsulation (liner and cap) for copper local interconnects as well as Co fill contacts for their 10nm resp 7nm technologies. Since then many have wondered about the unit process details behind the new cobalt integration and here we have it - The Applied Materials  complete cobalt solution as announced yesterday. Especially interesting that TiN ALD also is used as a cobalt seed/adhesio/dufusion barrier for cobalt contacts. The most interesting stuff you will finde here: LINK
[SANTA CLARA, Calif., June 05, 2018]  Applied Materials, Inc. today announced a breakthrough in materials engineering that accelerates chip performance in the big data and AI era.

In the past, classic Moore’s Law scaling of a small number of easy-to-integrate materials simultaneously improved chip performance, power and area/cost (PPAC). Today, materials such as tungsten and copper are no longer scalable beyond the 10nm foundry node because their electrical performance has reached physical limits for transistor contacts and local interconnects. This has created a major bottleneck in achieving the full performance potential of FinFET transistors. Cobalt removes this bottleneck but also requires a change in process system strategy. As the industry scales structures to extreme dimensions, the materials behave differently and must be systematically engineered at the atomic scale, often under vacuum. 
To enable the use of cobalt as a new conducting material in the transistor contact and interconnect, Applied has combined several materials engineering steps – pre-clean, PVD, ALD and CVD – on the Endura® platform. Moreover, Applied has defined an integrated cobalt suite that includes anneal on the Producer® platform, planarization on the Reflexion® LK Prime CMP platform and e-beam inspection on the PROVision™ platform. Customers can use this proven, Integrated Materials Solution to speed time-to-market and increase chip performance at the 7nm foundry node and beyond. 

“Five years ago, Applied anticipated an inflection in the transistor contact and interconnect, and we began developing an alternative materials solution that could take us beyond the 10nm node,” said Dr. Prabu Raja, senior vice president of Applied’s Semiconductor Products Group. “Applied brought together its experts in chemistry, physics, engineering and data science to explore the broad portfolio of Applied’s technologies and create a breakthrough Integrated Materials Solution for the industry. As we enter the big data and AI era, there will be more of these inflections, and we are excited to be having earlier and deeper collaborations with our customers to accelerate their roadmaps and enable devices we never dreamed possible.”

While challenging to integrate, cobalt brings significant benefits to chips and chip making: lower resistance and variability at small dimensions; improved gapfill at very fine dimensions; and improved reliability. Applied’s integrated cobalt suite is now shipping to foundry/logic customers worldwide.

Applied Materials, Inc. (Nasdaq:AMAT) is the leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. Our expertise in modifying materials at atomic levels and on an industrial scale enables customers to transform possibilities into reality. At Applied Materials, our innovations make possible the technology shaping the future. Learn more at

Saturday, April 14, 2018

The Material Discovery Funnel: A Six-Step Process for Advanced Material Development

The forward march of technology relies on continuous improvement of critical components such as semiconductors, batteries, fuel cells, and the like. In time, every component runs up against performance constraints established by fundamental physics and chemistry. Overcoming those restrictions requires the development of unique advanced materials that circumvent such limitations. Discovering and optimizing these types of new materials is difficult because the range of variables creates an enormous design space that is difficult to explore efficiently. Combinatorial deposition refers to a process of creating many advanced material candidates on a single substrate without removing that substrate from the chamber during the deposition process. The technique is not new in concept, but the remarkable advancements in deposition chamber capabilities and controls are making combinatorial deposition easier to implement. We refer to the process of developing advanced materials using combinatorial deposition as the "material discovery funnel."
The material discovery funnel - PVD Products
As described by PVD Products this is a six step process. You can visit their Blog and get the download link to the excellent white paper!

Source: PVD Products Blog LINK

Friday, December 2, 2016

New Book - Growth and Transport in Nanostructured Materials (PVD, CVD & ALD)

Here is a good Christmas gift for the scientist you really care about.

Growth and Transport in Nanostructured Materials

Reactive Transport in PVD, CVD, and ALD

Authors: Angel Yanguas-Gil, Northwestern-Argonne Inst. of Science and Engineering, Northwestern University, Evanston, Illinois, USA 

This book will address the application of gas phase thin film methods, including techniques such as evaporation, sputtering, CVD, and ALD to the synthesis of materials on nanostructured and high aspect-ratio high surface area materials. We have chosen to introduce these topics and the different application fields from a chronological perspective: we start with the early concepts of step coverage and later conformality in semiconductor manufacturing, and how later on the range of application branched out to include others such as energy storage, catalysis, and more broadly nanomaterials synthesis. [Continue at Springer]

Wednesday, April 29, 2015

AVACO Receives Volume Production Order for PV Manufacturing Line from US Manufacturer

SAN JOSE, Calif.--()--AVACO received additional volume order for PV manufacturing line that will be installed in China from one of the major solar manufacturer in the U.S. AVACO specializes in the manufacturing sputtering (PVD) vacuum deposition equipment, SuVAS™, and atomic Layer deposition (ALD) equipment AEON™. With the expertise in providing the turnkey manufacturing solution, AVACO boosts the PV market momentum.


"The result is in line with our milestone that we would receive additional volume production orders for photovoltaic manufacturing," stated Chuck Kim, AVACO's VP & GM, business development. "It is a major production win and a validation of our proven production technology.”

Leveraging the experience and strength in the mass production industry, AVACO surges at an accelerating pace during the past 24 months in the U.S. market development. AVACO expands its service to meet customers with contract manufacturing needs as well as custom designs in the U.S. Overall, the company has validated its technological capabilities with flexible services in the market with proven reliability, resulting in superior performance and further positioning itself as the technology of choice for leading edge automated manufacturing.

“Our core technology strengthens and broadens our offering of competency, enabling AVACO to continue to serve our customers with innovative and leading-edge solutions for thin film manufacturing challenges,” said Kim. 

AVACO is pleased to announce the participation in the Society of Vacuum Coater, 2015 SVC Techcon Exhibit, April 28 ~ 29, 2015 at Santa Clara Convention Center, Santa Clara, CA. For more information please visit us at our Booth #912, 2015 SVC Techcon Exhibit. Additional information can be found at our website at

AVACO Introduces New ALD Process System for Solar Cell:

Thursday, May 29, 2014

Applied Materials Enables Cost-Effective Vertical Integration of 3D Chips by PVD

As reported by Applied Materials: SANTA CLARA, Calif., May 28, 2014 - Applied Materials, Inc. today introduced the Endura® VenturaTM PVD system that helps customers reduce the cost of fabricating smaller, lower power, high-performance integrated 3D chips. The system incorporates Applied's latest innovations to its industry-leading PVD technology that enables the deposition of thin, continuous barrier and seed layers in through-silicon-vias (TSVs). Demonstrating Applied's precision materials engineering expertise, the Ventura system also uniquely supports the use of titanium in volume production as an alternate barrier material for lower cost. With the launch of the Ventura system, Applied is expanding its comprehensive toolset for wafer level packaging (WLP) applications, including TSVs, redistribution layer (RDL) and Bump.
"Ventura provides a less expensive barrier for copper, as well as the copper seed layer necessary for the subsequent through copper plating process itself. Typical copper interconnects on-chip are very very small -- on the order of 50 nanometers -- but TSVs are much larger -- on the order of 50 microns. Ventura can safely address aspect rations of TSVs ranging from typical TSVs today of 5-to-1 to those of the future of 10-, 11-, and even 12-to-1 aspect ratios. The Ventura tool can also handle traditional tantalum liners for TSVs as well as the more cost-effective titanium TSV liners, before depositing the copper seeds for the eventual polished interconnect itself. Applied materials also claims twice the throughput of competing PVD interconnect tools, and says it has already shipped 30 Ventura chambers in the last 18 months" (Source EE Times)
TSVs are a critical technology for vertically fabricating smaller and lower power future mobile and high-bandwidth devices. Vias are short vertical interconnects that pass through the silicon wafer, connecting the active side of the device to the back side of the die, providing the shortest interconnect path between multiple chips. Integrating 3D stacked devices requires greater than 10:1 aspect ratio TSV interconnect structures to be metallized with copper. The new Ventura tool solves this challenge with innovations in materials and deposition technology to manufacture TSVs more cost-effectively than previous industry solutions.

Applied Materials' Sesh Ramaswami discusses the fundamentals of advanced packaging and the revolutionary impact this technology is having on the gadgets we buy and the cloud infrastructure that makes mobility work. ( 
"Building on 15 years of leadership in copper interconnect technology, the Ventura system enables fabrication of robust high-aspect ratio TSVs, with up to 50 percent barrier seed cost savings compared to copper interconnect PVD systems," said Dr. Sundar Ramamurthy, vice president and general manager of Metal Deposition Products at Applied Materials. "These innovations deliver a higher-performance and more functional, yet, compact chip package with less power consumption to meet leading-edge computing needs. Customers are realizing the benefits of this new PVD system and are qualifying it for volume manufacturing."
Supporting the manufacture of high-yielding 3D chips, the Ventura system introduces advances in ionized PVD technology that assure the integrity of the barrier and seed layers that are critical to superior gap-fill and interconnect reliability. These developments significantly improve ion directionality to enable the deposition of thin, continuous and uniform metal layers deep into the vias to achieve the void-free fill necessary for robust TSVs. With the improvement in directionality, higher deposition rates can be achieved, while the amount of barrier and seed material needed can be reduced. These attributes of the Ventura system and the adoption of titanium as an alternate barrier are expected to improve device reliability and reduce the overall cost of ownership for TSV metallization.