Review—Cobalt Thin Films: Trends in Processing Technologies and Emerging Applications

Here is a fantastic revie on Cobalt ALD and CVD from SUNY Polytechnic Institute and Gelest and it is fee to download - Thanks for sharing this one Henrik Pedersen!

 

Editors' Choice—Review—Cobalt Thin Films: Trends in Processing Technologies and Emerging Applications
Alain E. Kaloyeros, Youlin Pan, Jonathan Goff and Barry Arkles

ECS Journal of Solid State Science and Technology, 8 (2) P119-P152 (2019) (LINK)

Cobalt metallic films are the subject of an ever-expanding academic and industrial interest for incorporation into a multitude of new technological applications. This report reviews the state-of-the art chemistry and deposition techniques for cobalt thin films, highlighting innovations in cobalt metal-organic chemical vapor deposition (MOCVD), plasma and thermal atomic layer deposition (ALD), as well as pulsed MOCVD technologies, and focusing on cobalt source precursors, thin and ultrathin film growth processes, and the resulting effects on film composition, resistivity and other pertinent properties.

 

Open access article distributed under the terms of the Creative Commons Attribution 4.0 License (CC BY, http://creativecommons.org/licenses/by/4.0/)

IEDM 2018 Imec on Interconnect Metals Beyond Copper

At IEDM in December 2018 Imec presented recent results from their interconnect program “Interconnect metals beyond copper – reliability challenges and opportunities”, which was recently covered by Scotten Jones (SemiWiki).

 

The electrical current in interconnect lines haven’t scaled down as fast as the lines' cross sectional area, which has enhanced the current density in the lines. Initial wide aluminum (Al) interconnects were first replaced by narrower aluminum-copper (AlCu) alloys and eventually by Cu to reduce the interconnects line resistance. Now even Cu needs to be replaced by alternate materials for the narrowest lines due to the following limits:

• Higher resistivity with shrinking line width – below 20nm exponential increase in line resistance.
• Via resistance also goes up strongly due to the liner.
• Thinner lines see more grains from electroplating – around 10nm line can’t meet electromigration.

Imec commenced their work on alternative materials for M0 and M1 interconnects by screening based on the two metrics—resistivity multiplied by electron mean free path and melting point. The work reflects Rhodium and Iridium as the best candidate materials for the lowest interconnects that can be reasonably integrated. Ruthenium (Ru) and Cobalt (Co) exhibit similar performance. These materials can be deposited using ALD, CVD or electroplating. Co needs a thin adhesion layer but not a barrier layer. Ru also doesn’t require any seed or barrier layer. Imec is still working on reliability tests of these materials.

Meanwhile, TSMC has been using Co capping on Cu interconnects since 16 nm due to improved electromigration. Co (TSMC) and Ru (Intel) seed layers were introduced. Intel has introduced Co contacts at 10 nm and TSMC at 7 nm. Intel has also introduced Co interconnects for metals 0 and 1 at 10 nm.

Source: SemiWiki, Scotten Jones : LINK

 

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By Abhishekkumar Thakur

Overview of Applied Materials cobalt metallization for local interconnects

For those of you interested in the details behind the Applied Materials integrated cobalt metallization process Jonathan Bakke has written two informative blogs about it in Semiconductror Engineering:

(1) The Role Of Cobalt In Enabling AI - For continued performance, power, area and cost improvements, materials need to be engineered at the atomic scale.

(2) The Materials Side Of AI - What comes after tungsten fill for contacts and copper for the lowest-level interconnects?

The integrated cobalt solution using Applied Materials platforms (Applied Materials).

Jonathan Bakke is global product manager for Contact and Middle of Line Products in the Metal Deposition Products Business Unit at Applied Materials. He details the process flow and tool sets from Applied Materials involved in the complete BEOL Co metallization flow:

• PVD titanium and ALD titanium nitride for the silicide and barrier layers
• PVD cobalt serves as an anchor layer to ensure good cobalt adhesion to the bottom of the feature
• CVD cobalt is then used to deposit a conformal film to bulk fill the feature
• Anneal purifies and reflows the cobalt, removes the CVD seam, and merges crystal grains to form a more crystalline, lower resistance material
• PVD cobalt for a thick overburden film
• CMP removes overburden materials to create a smooth planar surface
• E-beam technology monitors the process and detects voids

Cobalt and Ruthnium confirmed in Intel 10nm Cannon Lake BEOL

TechInsights has found the long-awaited Cannon Lake - the Intel 10 nm logic process inside the i3-8121U CPU, used in the Lenovo IdeaPad330.

 
This innovation boasts the following:

• Logic transistor density of 100.8 mega transistors per mm², increasing 10nm density 2.7X over the 14nm node
• Utilizes third generation FinFET technology
• Minimum gate pitch of Intel’s 10 nm process shrinks from 70 nm to 54 nm
• Minimum metal pitch shrinks from 52 nm to 36 nm

Process Highlights:

• Deepest scaled pitches of current 10 nm and upcoming 7 nm technologies
• First Co metallization and Ru usage in BEOL
• New self-aligned patterning schemes at contact and BEOL

Source: TechInsight (LINK)

By reading this it is not possible to determine exactly how Ruthenium is used or how it has been deposited and there are several options like barrier and seed layer for plating Copper or Cobalt. What is known is that Intel presented already at IEDM2017 the use of cobalt in their 10 nm MOL/BEOL process flow as contacts and M0/M1 lines as well as barrier/seed for copper and copper cap for complete encapsulation of copper up to M5.

Intel 10nm mid end of line cobalt and copper metallization as presented at IEDM 2017.

Aveni extends copper interconnects to 5nm and below for BEOL integration employing ALD TaN & CVD Co barrier/seed

Recently at IEDM 2017 IBM announced that copper is here to stay and can continue to be scaled for the future back end of line (BEOL) interconnects - 20 Years of Cu BEOL in Manufacturing, and its Future Prospects (Invited), D. Edelstein, IBM TJ Watson Research Center (LINK)

Before the actual copper plating process, the advanced dual-damascene structures for interconnects employ two very important conformal deposition processes :

• an atomic layer deposition tantalum nitride (ALD TaN) copper diffusion barrier
• a thin chemical vapor deposition cobalt (CVD Co) liner

More detailed information on Cobalt CVD for barrier/seed and selective encapsulation of copper from the leader Applied Materials can be found here (LINK).

According to a press release below (LINK), Aveni has announced it has obtained results that support the continued use of copper in the BEOL for advanced interconnects, at and beyond the 5nm technology node. Aveni is a French developer and manufacturer of wet deposition technologies and chemistries for 2D interconnects and 3D through silicon via packaging. The company was originally founded in 2001 as a spinoff from the Commissariat à l’énergie atomique et aux énergies alternatives (CEA) to develop and market groundbreaking nanometric deposition technologies for a variety of electronic applications.  

MASSY, France – Dec. 12, 2017 – aveni S.A., developer and manufacturer of market-disrupting wet deposition technologies and chemistries for 2D interconnects and 3D through silicon via packaging, today announced it has obtained results that strongly support the continued use of copper in the back end of line (BEOL) for advanced interconnects, at and beyond the 5nm technology node.