Intel 2019 Investor Meeting: 7 nm Product in 2021

Intel held its 2019 investor meeting May 8, 2019 (LINK), it's first since 2017, and CEO Bob Swan announced that Intel would launch its 7 nm process in 2021 to challenge TSMC's 5 nm products.

Intel's Xe graphics will be the leading 7 nm product, which will come on the heels of Intel's first discrete 10 nm GPU that arrives in 2020. The company also unveiled its first block diagram of the Ice Lake architecture and announced that its new 10nm Tiger Lake processors will come to market in 2020.

Source: Tom´s Hardware LINK

 (intel.com)

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By Abhishekkumar Thakur

IEDM 2018 Imec on Interconnect Metals Beyond Copper

At IEDM in December 2018 Imec presented recent results from their interconnect program “Interconnect metals beyond copper – reliability challenges and opportunities”, which was recently covered by Scotten Jones (SemiWiki).

 

The electrical current in interconnect lines haven’t scaled down as fast as the lines' cross sectional area, which has enhanced the current density in the lines. Initial wide aluminum (Al) interconnects were first replaced by narrower aluminum-copper (AlCu) alloys and eventually by Cu to reduce the interconnects line resistance. Now even Cu needs to be replaced by alternate materials for the narrowest lines due to the following limits:

• Higher resistivity with shrinking line width – below 20nm exponential increase in line resistance.
• Via resistance also goes up strongly due to the liner.
• Thinner lines see more grains from electroplating – around 10nm line can’t meet electromigration.

Imec commenced their work on alternative materials for M0 and M1 interconnects by screening based on the two metrics—resistivity multiplied by electron mean free path and melting point. The work reflects Rhodium and Iridium as the best candidate materials for the lowest interconnects that can be reasonably integrated. Ruthenium (Ru) and Cobalt (Co) exhibit similar performance. These materials can be deposited using ALD, CVD or electroplating. Co needs a thin adhesion layer but not a barrier layer. Ru also doesn’t require any seed or barrier layer. Imec is still working on reliability tests of these materials.

Meanwhile, TSMC has been using Co capping on Cu interconnects since 16 nm due to improved electromigration. Co (TSMC) and Ru (Intel) seed layers were introduced. Intel has introduced Co contacts at 10 nm and TSMC at 7 nm. Intel has also introduced Co interconnects for metals 0 and 1 at 10 nm.

Source: SemiWiki, Scotten Jones : LINK

 

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By Abhishekkumar Thakur

Intel 10 nm Logic Process Analysis (Cannon Lake) by TechInsight

[TechInsight, LINK] TechInsights has found the long-awaited Cannon Lake - the Intel 10 nm logic process inside the i3-8121U CPU, used in the Lenovo IdeaPad330.

 
This innovation boasts the following:

• Logic transistor density of 100.8 mega transistors per mm², increasing 10nm density 2.7X over the 14nm node
• Utilizes third generation FinFET technology
• Minimum gate pitch of Intel’s 10 nm process shrinks from 70 nm to 54 nm
• Minimum metal pitch shrinks from 52 nm to 36 nm

Process Highlights:

• Deepest scaled pitches of current 10 nm and upcoming 7 nm technologies
• First Co metallization and Ru usage in BEOL
• New self-aligned patterning schemes at contact and BEOL

Design Highlights:

• Hyperscaling via 6.2-Track high density library
• Contact on active gate (COAG) cell-level usage

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By Abhishekkumar Thakur