Applied Materials launch Selective Tungsten CVD for their Endura(TM) platform

[Applied Materials Blog LINK] Tungsten has been widely used as a gapfill material in middle-of-line (MOL) contacts for its low resistivity and bulk fill characteristics. MOL contacts form the critical electrical link between the transistors and the interconnects. Hence, ensuring low resistivity contacts is crucial for overall device performance.

With continued scaling, however, contact dimensions have decreased to the point at which contact resistance is becoming a bottleneck in realizing optimum device performance. As the cross-sectional area of the contact shrinks, a growing proportion of the volume is occupied by metal liner/barrier and nucleation layers, leaving less volume for the conducting metal fill. In addition, multiple resistive interfaces in the plug contribute to higher contact resistance.

An Applied Materials Endura(TM) Platform equipped with seven Selective Tungsten CVD Volta(R) and 2 pre-clean 300 mm chambers. (Credit: Applied Materials)

The Applied Endura Volta Selective W CVD system offers an integrated materials solution that relieves these adverse effects with a breakthrough in 2D scaling. The system combines surface treatment chambers with selective tungsten deposition chambers. The selective deposition is enabled by both the unique process capabilities of the deposition chambers and the various surface treatments that use specialized chemistries to prepare the underlying metal and dielectrics of the contact to enable bottom-up, metal-on-metal deposition. The selective process eliminates both liner/barrier and nucleation layers to alleviate the bottleneck in device performance, and produces void- and seam-free gapfill.

Cross section of a leading edge Logic processor showing the Source/Drain contacts to the transistors and the metal interconnetcs (Credit: TechInsight, Applied Materials)

As all process steps are performed in an ultra-clean, continuous high-vacuum environment, the integrated materials solution ensures a pristine interface and defect-free contact fill. With the volume of conducting metal maximized, contact resistivity is substantially improved compared to conventional liner/barrier contact fabrication. This lower resistance facilitates higher device density and extends 2D scaling.

The selctive W CVD defect-free contact fill maximizes the volume of conducting metal (right), contact resistivity is substantially improved compared to conventional liner/barrier contact fabrication (left). (Credit: Applied Materials)

IEDM 2018 Imec on Interconnect Metals Beyond Copper

At IEDM in December 2018 Imec presented recent results from their interconnect program “Interconnect metals beyond copper – reliability challenges and opportunities”, which was recently covered by Scotten Jones (SemiWiki).

 

The electrical current in interconnect lines haven’t scaled down as fast as the lines' cross sectional area, which has enhanced the current density in the lines. Initial wide aluminum (Al) interconnects were first replaced by narrower aluminum-copper (AlCu) alloys and eventually by Cu to reduce the interconnects line resistance. Now even Cu needs to be replaced by alternate materials for the narrowest lines due to the following limits:

• Higher resistivity with shrinking line width – below 20nm exponential increase in line resistance.
• Via resistance also goes up strongly due to the liner.
• Thinner lines see more grains from electroplating – around 10nm line can’t meet electromigration.

Imec commenced their work on alternative materials for M0 and M1 interconnects by screening based on the two metrics—resistivity multiplied by electron mean free path and melting point. The work reflects Rhodium and Iridium as the best candidate materials for the lowest interconnects that can be reasonably integrated. Ruthenium (Ru) and Cobalt (Co) exhibit similar performance. These materials can be deposited using ALD, CVD or electroplating. Co needs a thin adhesion layer but not a barrier layer. Ru also doesn’t require any seed or barrier layer. Imec is still working on reliability tests of these materials.

Meanwhile, TSMC has been using Co capping on Cu interconnects since 16 nm due to improved electromigration. Co (TSMC) and Ru (Intel) seed layers were introduced. Intel has introduced Co contacts at 10 nm and TSMC at 7 nm. Intel has also introduced Co interconnects for metals 0 and 1 at 10 nm.

Source: SemiWiki, Scotten Jones : LINK

 

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By Abhishekkumar Thakur

Is the semiconductor industry preparing for ruthenium again?

As cobalt is being implemented for 10/7 nm logic interconnects, the next contender on roadmaps for the leading IDMs and foundries is ruthenium. This is not the first time that ruthenium comes into play, ruthenium has on regular basis been on the DRAM and Logic manufacturers roadmaps. Last year there were several indications that ruthenium is back again including that you could spot a rice in ruthenium metal pricing. However, since I started in the semiconductor world 2003 I think that I have managed to be part of six ALD/CVD ruthenium programs and I am happy that one of them is still running (this was my shortest participation, all in all 7 days).

So why do you want to use an expensive and rather fancy metal like ruthenium in interconnects? The lowest Ru resistivity reported for use in interconnects is 15 μΩ-cm, at a cross-sectional area of 300 nm2. Ru damascene metallization is extendible to features with critical dimension around 10 nm and Ru may match Cu line resistance for line dimensions below ~17 nm.

Therefore, as semiconductor devices become even smaller at sub 7 nm nodes, Ru is a strong candidate for replacing some of the back end copper and middle of the line tungsten or ultimately cobalt as the interconnect material or as a liner/barrier/seed for metallization.

At AVS ALD 2018 in Incheon South Korea had a high number of presentations on ruthenium. Besides the oral presentations here below, there were also a number of interesting posters. You can get the abstracts by searching "ruthenium" in the AVS ALD conference planer (LINK).

Low Temperature Atomic Layer Deposition of Ru for Copper Metallization [Oral]
Anil Mane‚ Yan Zhang (Argonne National Laboratory); Amit Kumar‚ John Allgair (BRIDG); John Hryn‚ Jeffrey W. Elam (Argonne National Laboratory)

Insight in Surface Dependence and Diffusion-mediated Nucleation Mechanism of Ruthenium Atomic Layer Deposition on Dielectrics
Job Soethoudt (KU Leuven‚ Belgium); Yoann Tomczak (IMEC‚ Belgium); Fabio Grillo‚ Ruud Van Ommen (Delft University of Technology‚ Netherlands); Efrain Altamirano Sanchez (IMEC‚ Belgium); Annelies Delabie (KU Leuven‚ Belgium)

Inherent Substrate Selectivity and Nucleation Enhancement during Ru ALD using the RuO4-Precursor and H2-gas.
Matthias Minjauw‚ Hannes Rijckaert‚ Isabel Van Driessche‚ Christophe Detavernier‚ Jolien Dendooven (Ghent University‚ Belgium)

 

Conformal Growth of Low-resistivity Ru by Oxygen-free Thermal Atomic Layer Deposition [Oral]

Guo Liu‚ Jacob Woodruff‚ Daniel Moser (EMD Performance Materials)

Ruthenium: Advanced Nodes and Supply Chain Implications [Oral]

Oliver Briel‚ Don Zeng‚ Andreas Wilk (Umicore AG & Co. KG‚ Germany)

 

The last contribution by Umicore is especially interesting since it explain in great details the whole supply chain of ruthenium today including:

• Ruthenium in electronic applications
• Todays Ruthenium market - Platinum Group Metals market
• Market drivers, Sources, uses, supply vs. demand,
• Managing Ruthenium in your precursor portfolio
• Sourcing strategies

Umicore Tweet: Oliver Briel's fascinating talk on ‘#Ruthenium: Advanced Nodes and Supply Chain Implications’ (LINK).

Another event taking place this summer was the Imec US Technology Forum in San Fransisco, also here ruthenium was again on the agenda. According to a recent article in C&EA (LINK), reporting from the annual Imec Technology Forum, Imec experts made the case that the metal ruthenium has potential to replace copper in interconnect. Such a replacement could prevent the semiconductor industry from tripping over a wiring problem in coming years. The main information was given in a talk by Zsolt Tokei - Program Director Nano-interconnect, imec:

New Conductors - Reality or not? [LINK]

For several decades Cu, Al and W were used for interconnect wiring. Recently, due to resistance and reliability concerns alternatives to conventional conductors gained significant interest. Alternative metals are of interest to both memory and logic chips. In this talk imec’s conductor research activities will be showcased with a few implementation examples using damascene or subtractive processes. Benchmark to conventional conductors as well as future perspectives will be provided.

Before that there was also the IITC 2018 and there ruthenium was on the agenda as well. One interesting presentation was the Adelman et. al also from Imec, “Alternative Metals: from ab initio Screening to Calibrated Narrow Line Models” (LINK).

So as for now, ruthenium is on the roadmaps for 5 nm and below but not yet implemented in HVM by any Foundry. However there is a reverse engineering report claiming that ruthenium has been found in Intels 10 nm technology [LINK].

Ruthenium could rewire computer chips https://t.co/mkXzCDzWrE via @cenmag #ruthenium #ALDep #CVDep

— BALD Engineering AB (@jv3sund) August 10, 2018

Further reading : Ruthenium Liners Give Way To Ruthenium Lines (LINK)

Much more detailed information on ALD/CVD metal precursors : TECHCET LLC Critical Materials Report(TM) on Metal & High-k  CVD and ALD precursors (LINK)