This innovation boasts the following:
- Logic transistor density of 100.8 mega transistors per mm2, increasing 10nm density 2.7X over the 14nm node
- Utilizes third generation FinFET technology
- Minimum gate pitch of Intel’s 10 nm process shrinks from 70 nm to 54 nm
- Minimum metal pitch shrinks from 52 nm to 36 nm
- Deepest scaled pitches of current 10 nm and upcoming 7 nm technologies
- First Co metallization and Ru usage in BEOL
- New self-aligned patterning schemes at contact and BEOL
By reading this it is not possible to determine exactly how Ruthenium is used or how it has been deposited and there are several options like barrier and seed layer for plating Copper or Cobalt. What is known is that Intel presented already at IEDM2017 the use of cobalt in their 10 nm MOL/BEOL process flow as contacts and M0/M1 lines as well as barrier/seed for copper and copper cap for complete encapsulation of copper up to M5.
Intel 10nm mid end of line cobalt and copper metallization as presented at IEDM 2017.