Decoupling from Dependence: The Global Semiconductor Industry Races to Diversify Amid Geopolitical Risks

The semiconductor industry is at a critical juncture, driven by the dual pressures of rising demand for advanced chips in artificial intelligence (AI) and the urgent need to mitigate geopolitical vulnerabilities. With Taiwan’s fabs, particularly TSMC, supplying over 90% of the world’s cutting-edge semiconductors, nations are rapidly investing in new fabs to reduce reliance on both Taiwan and China. While TSMC, Samsung, and Intel lead efforts to expand capacity in regions like the US, Europe, and Japan, these initiatives fall short of replacing Taiwan’s unparalleled output of 2 nm and below chips by 2030. Simultaneously, China’s struggle to compete at leading-edge nodes, compounded by export restrictions on critical tools, further underscores the fragility of the global semiconductor supply chain. These dynamics signal a transformative era as the free world works to establish more resilient and geographically diversified semiconductor ecosystems.

According to a recent article by FT (Source), the primary drivers for 2 nm technology development are the surging demand for custom and specialized chips, particularly in artificial intelligence (AI), and the need to create competitive alternatives to current large-scale semiconductor manufacturers. Rapidus, for instance, is targeting a niche in the AI market by producing bespoke chips that prioritize efficiency and can outperform more generic chips, such as those produced by Nvidia, in specific applications.

The motivation also includes addressing capacity limitations from dominant players like TSMC, which prioritizes large orders. Rapidus sees an opportunity to capture smaller customers who are willing to pay a premium for speed and customization. Additionally, geopolitical factors are influencing the push for advanced technology, with Japan aiming to reduce reliance on Taiwan's semiconductor manufacturing expertise and establish its own ecosystem for leading-edge production. 

This is why the semiconductor industry is advancing rapidly toward 3 nm and 2 nm process nodes, with leading players outlining production timelines and capacity expansions over the next five years. Below is a detailed overview of these developments, including plans from TSMC, Samsung, Intel, and Rapidus.

The forecast predicts a 540% growth in the global AI semiconductor market between 2020 and 2030, driven by increasing adoption across key segments such as servers, networking, edge devices, and PCs/smartphones. Servers are projected to dominate the market, reflecting the growing demand for AI in data centers and cloud computing, while networking and edge computing are expected to see rapid expansion, driven by real-time processing needs in IoT and automotive applications. Moderate growth is anticipated in the PCs/smartphone segment as AI integration in consumer electronics continues. Tokyo’s recent $65 billion investment in AI and semiconductor industries underscores the importance of this market, which is expected to exceed $400 billion by 2030, highlighting the transformative role of semiconductors in powering AI advancements across industries.

TSMC

Taiwan Semiconductor Manufacturing Company (TSMC) is enhancing its semiconductor fabrication capabilities globally, focusing on 3 nm and 2 nm and below nodes.

• 3 nm Production (Taiwan): TSMC began volume production of its 3 nm process technology in December 2022 at Fab 18, located in the Southern Taiwan Science Park (STSP). Fab 18 consists of eight phases, each featuring a cleanroom area of 58,000 square meters, roughly double the size of a standard logic fab. TSMC has invested over NT$1.86 trillion in Fab 18, creating more than 11,300 high-tech jobs.
  Source

• 2 nm Development (Taiwan): TSMC’s 2 nm process is scheduled for risk production in late 2024 and mass production in 2025. A new facility in Hsinchu Science Park is under construction, with equipment installation set for April 2024.
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• 2 nm (Arizona, USA): TSMC is building a second fab in Arizona to produce 2 nm nodes, with production expected to begin in 2028. A third fab, focused on cutting-edge technologies, is planned for later this decade. This is part of a $40 billion investment, the largest foreign investment in Arizona's history.
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Samsung

Samsung Electronics is expanding its semiconductor manufacturing capabilities in South Korea and the United States, focusing on 3 nm and 2 nm nodes.

• 3 nm Production (South Korea): Samsung began mass production of its first-generation 3 nm chips in the second half of 2022, using its proprietary Multi-Bridge Channel Field-Effect Transistor (MBCFET) technology, a Gate-All-Around (GAA) architecture. Second-generation 3 nm production began in 2023, offering improved energy efficiency and performance.
  Source

• 2 nm Development (South Korea): Samsung plans to start 2 nm production in 2025 for mobile devices, followed by high-performance computing in 2026 and automotive semiconductors by 2027. The 2 nm (SF2) process is expected to deliver a 12% performance increase, 25% power efficiency improvement, and 5% area reduction compared to 3 nm.
  Source

• Taylor Fab (Texas, USA): Samsung is constructing a $17 billion fab in Taylor, Texas. Initially planned for 4 nm production in late 2024, the fab may start directly with 2 nm technology in 2026 to align with Samsung’s broader roadmap.
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Intel

Intel Corporation is investing in global semiconductor manufacturing, focusing on advanced nodes like Intel 3, Intel 20A, and Intel 18A.

• United States: Intel’s Fab 42 in Arizona produces 10 nm chips and is transitioning to Intel 7 and Intel 4 nodes. In Ohio, Intel is building two fabs with a $20 billion investment to produce Intel 18A by the decade's end.
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• Europe: Intel’s Fab 34 in Ireland will produce Intel 4 technology using EUV lithography. In Germany, Intel delayed its is investing €17 billion to construct two fabs in Magdeburg, focusing on advanced nodes.
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• Israel: Intel’s Fab 28 in Kiryat Gat, Israel, is transitioning from 10 nm to Intel 7 and Intel 4 processes. Intel has committed $10 billion to expand this facility.
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Rapidus

Rapidus, a Japanese semiconductor start-up, aims to produce 2 nm chips, positioning itself as a significant player in the advanced semiconductor market.

• 2 nm Development: Rapidus plans to start trial production of 2 nm chips in April 2025, with mass production by 2027. The company is collaborating with IBM to integrate cutting-edge technology, including Extreme Ultraviolet (EUV) lithography.
  Source

• Manufacturing Facilities: Rapidus is building its IIM-1 fab in Chitose City, Hokkaido, Japan. The first EUV machine from ASML is expected to arrive in mid-December 2024.
  Source

• Strategic Approach: Rapidus is rethinking traditional manufacturing models by emphasizing smaller batch production with faster cycle times, aiming for greater efficiency and adaptability.
  Source

SMIC

China’s stake in leading-edge semiconductor manufacturing and AI is hindered by significant technological and geopolitical challenges. While domestic efforts, such as those by SMIC, have made strides in producing 7 nm chips, China remains far behind global leaders like TSMC, Samsung, and Intel, who are advancing toward 2 nm production. Critical dependencies on foreign equipment, such as ASML's EUV lithography machines, and U.S.-led export restrictions on advanced semiconductor tools and high-performance GPUs have further constrained its progress. Although China has invested heavily in AI development, its capabilities remain primarily focused on practical applications like surveillance and automation rather than leading innovation in foundational AI technologies. To conclude, China has an uphill battle to compete in the global semiconductor and AI industries.

Is the free world Decoupling from China and future risk of relying on Taiwan Fabs?

The global semiconductor industry is undergoing significant restructuring as it increasingly decouples from China and prepares for potential decoupling from Taiwan’s fabs. Geopolitical tensions, driven by concerns over China's ambitions toward Taiwan and its own restricted access to advanced chip-making technologies, have accelerated efforts by the US, Europe, and their allies to diversify supply chains and reduce dependency on both regions. Export controls targeting China, including restrictions on advanced chips and manufacturing tools, have prompted heavy investments in domestic semiconductor manufacturing in the US, Japan, South Korea, and Europe. Simultaneously, Taiwan’s pivotal role in leading-edge semiconductor production, dominated by TSMC, has highlighted vulnerabilities, spurring new fabs outside the island, such as TSMC’s facilities in Arizona and Samsung’s in Texas. These shifts reflect a broader trend toward creating more resilient, geographically dispersed semiconductor ecosystems that mitigate risks associated with reliance on any single region for critical technologies.

Current global plans for semiconductor manufacturing expansion aim to reduce dependency on Taiwan but fall short of ensuring sufficient non-Taiwan capacity for 2 nm and below nodes in the near term. Taiwan, led by TSMC, still dominates leading-edge semiconductor production, supplying over 90% of the world’s advanced chips. While significant investments are underway—such as TSMC's Arizona fabs, Samsung’s expansions in South Korea and Texas, and Intel's facilities in the US, Europe, and Israel—these efforts are unlikely to match Taiwan’s scale and technological leadership at 2 nm and below by 2027-2030.

For example, TSMC’s planned Arizona fab is projected to produce 2 nm chips by 2028, but its capacity will be a fraction of TSMC's output in Taiwan. Similarly, Samsung and Intel are progressing toward advanced nodes, but both face challenges in matching TSMC’s efficiency and yield at these cutting-edge technologies. Additionally, the complexity of EUV lithography and the industry's high R&D costs further limit the pace at which non-Taiwan fabs can scale to competitive capacities.

Intel Sets Record with 2D TMD Transistors for Next-Gen Electronics

Intel researchers have achieved record-breaking performance in transistors using ultra-thin 2D transition metal dichalcogenides (TMDs) like MoS₂ and WSe₂ as channels. These monolayer materials are ideal for scaled devices but present challenges in integration due to their lack of atomic “dangling bonds.” By developing a specialized gate oxide atomic layer deposition (ALD) process and low-temperature gate cleaning, Intel built GAA NMOS and PMOS transistors with record subthreshold slopes and high drain currents. Specifically, they achieved a subthreshold slope of <75 mV/dec and Idmax >900 µA/µm in MoS₂ NMOS transistors, and a slope of 156 mV/dec with Idmax = 132 µA/µm in WSe₂ PMOS devices. These advancements highlight the promise of 2D TMDs for next-gen electronics and the need for further research to overcome integration challenges.

The images above are TEM characterizations of the record GAA NMOS device across the gate, showing a healthy, conformal GAA architecture with 43nm-wide monolayer MoS2 channel and conformal HfO2 with a thickness of ~4.0nm.

Record Performance with 2D Channels: Ultra-thin transition metal dichalcogenides (TMDs), such as MoS2 and WSe2, are called monolayer, or 2D, materials because they’re one just atomic layer thick. They are being extensively studied for use as the channel in extremely scaled devices because of their excellent electrical performance. However, interfacing them with other materials in a device structure is difficult because at the atomic level there are no available “dangling bonds” to use. Thus, 2D channels have been a challenge to optimize.

Intel researchers will describe how they used 1) a unique gate oxide atomic layer deposition (ALD) process and 2) a low-temperature gate cleaning process to build GAA devices that demonstrated breakthrough performance for MoS2- and WSe2-based GAA NMOS and PMOS transistors, respectively. This includes record subthreshold slope (<75mv/dec) and drain current (Idmax>900 µA/µm at <50nm gate length) in sub-1nm-thick monolayer MoS2 GAA NMOS transistors. Also, using ruthenium (Ru) source and drain (S/D) contacts, they achieved record subthreshold slope (156mV/dec) and drain current (Idmax = 132µA/µm) in a ~30nm gate-length WSe2 PMOS device. The researchers say these results both underscore the potential of 2D TMDs for use in next-generation electronics, and highlight the critical need for continued research to address the remaining scientific and technological challenges.

Sources:

https://www.ieee-iedm.org/press-kit

(Paper #24.3, “Gate Oxide Module Development for Scaled GAA 2D FETs Enabling SS<75mV/d and Record Idmax>900µA/µm at Lg<50nm,” W. Mortelmans et al, Intel)

Intel's Breakthrough in RibbonFET Transistor Scaling Demonstrates Silicon Viability for Future Nodes

For the latest insights from the 2024 IEEE International Electron Devices Meeting (IEDM), including groundbreaking advancements in 2nm CMOS logic, extremely scaled transistors, monolithic CFET inverters, energy-efficient 3D computing-in-memory, and novel device technologies, you can explore the full press kit here.

Extremely Scaled Transistors from Intel: Intel researchers will show that silicon can continue to support the extreme gate length scaling which future technology nodes require. They will describe how they built RibbonFET CMOS transistors (Intel’s version of nanosheets) with 6nm gate lengths at 45nm contacted poly pitch (CPP, the spacing between adjacent transistor gates), with no degradation of electron mobility (how fast electrons can move through a material). The researchers will show that electron mobility doesn’t degrade until 3nm Tsi (silicon thickness), below which electron scattering due to surface roughness becomes an issue. They will describe how they achieved good short channel control (≤100mV/V at <4nm Tsi), with extremely low threshold voltage at these gate lengths through clever workfunction engineering. The work shows that 3nm is a practical scaling limit for RibbonFETs.

The image illustrates the behavior of drain-induced barrier lowering (DIBL) vs. silicon thickness (Tsi) at LG=18nm. It shows a reduction as Tsi is scaled from 10nm to 1.5nm; however, DIBL reduction saturates at Tsi <4nm, below which very little gain is obtained. PMOS DIBL is elevated vs. NMOS DIBL at the same Tsi. Also shown are TEM micrographs of a 1NR transistor with various Tsi values down to 1.5nm.

The series of images are (a) TEM micrograph and EDX scan of a completed 6nm RibbonFET device on a 1NR vehicle, showing a disconnected subfin; (b - d) are high-resolution cross-section TEMs for Tsi=5.5nm, 3.1nm and 1.7nm respectively, at 6nm gate length on a 1NR vehicle

Sources:

IEDM 2024 Press Kit Paper #2.2, “Silicon RibbonFET CMOS at 6nm Gate Length,” A. Agrawal et al, Intel https://www.ieee-iedm.org/press-kit

Intel's Strategic Leap with 14A Node and DSA: Pioneering Next-Gen Semiconductor Manufacturing

Semi Analysis recently published a deeper dive into of Directed Self Assembly (DSA) and prospects of Intel using it at their 14A node (Link below). Intel's latest efforts in semiconductor manufacturing have brought considerable attention to its 18A node, yet it's the 14A node that is most important according to the analysis for the success of Intel Foundry's IDM 2.0 strategy. While the industry watches the ongoing discussions around the merits of TSMC's N2 and Intel’s 18A technologies, Intel is quietly setting a foundational stage with its 14A node, aiming to solidify customer trust and secure critical, high-value chip projects for the future. A key element in Intel's strategy may be the adoption of DSA that could significantly reduce lithography costs. DSA utilizes the self-organizing properties of block copolymers (BCPs) that assemble into predetermined patterns when guided by an underlying template. This approach promises to lower the doses required in extreme ultraviolet (EUV) lithography, allowing for more efficient patterning at reduced costs.

However, integrating DSA into commercial manufacturing involves challenges such as defectivity and pattern limitations, which could hinder its adoption. So I looked more into historical patent filings and found that reveal a typical hype cycle with increased filings during periods of peak expectations, followed by a decline as practical challenges emerged. Intel and TSMC have been consistently filing DSA patents, indicating sustained investment and belief in DSA's potential. Merck, among other chemical suppliers, has significantly increased patent filings, aligning with technological advancements in DSA. Please find on overview below.

It is well known that Intel plans to be the first major company to implement ASML’s high-NA EUV lithography scanners in high volume, despite the higher costs associated with single exposure high-NA systems compared to low-NA double patterning. It was also recently reported on X and other places that ASML is delivering a High-NA System to another player. SemiAnalysis argues that, the economic challenge posed by high-NA technology is addressed through the integration of DSA, which can improve the final pattern quality and dramatically reduce the necessary dose, thus potentially making high-NA economically more viable.

The benefits of DSA are significant: 

• The ability to produce finer features with lower line edge roughness and increased throughput, thanks to its ability to heal discrepancies in the EUV guide patterns. 
• Substantial cost savings and improved yield, especially for layers critical to the performance of advanced logic chips (bigger dies like AI accelerators).

However, DSA's integration into a commercial manufacturing environment is not without risks. The risks associated with Intel's adoption of DSA include:

• The primary risk with any new patterning technology is defectivity, for DSA it is linked to the chemical purity of the block copolymers (BCP). Synthesizing BCP to extremely high purities is challenging, and any inhomogeneity directly impacts the critical dimension (CD), leading to defects. Trace metals need to be below 10 parts-per-trillion, and filtering out organic impurities is difficult, impacting the viability of DSA for mass production. My assessment - Expect this to come from a MERCK or a Japanese chemical vendor.
• DSA is inherently limited to producing 1D line/space patterns or contact hole arrays, restricted to a single pitch per layer. This complicates the integration with other process technologies that might require more diverse patterning capabilities. However, these issues have potential solutions similar to those used in multi-patterning schemes.
• Despite the theoretical benefits and recent advances in DSA, it remains largely untested in high-volume, leading-edge manufacturing. Intel is pioneering the use in high-NA scenarios, but the broader adoption across the industry, including by competitors like TSMC who are also developing DSA, remains uncertain. 

Source: Intel’s 14A Magic Bullet: Directed Self-Assembly (DSA) (semianalysis.com)

So let´s do the Patbase Test - how does this hold out if we dig into historical and current patent filing by the suspects!

Yes indeed, we have seen much increased filing the past decade or so representing a typical hype cycle. The hype cycle is a model developed by Gartner that describes the progression of a technology from inception to widespread adoption and maturity. It typically consists of five phases: the Technology Trigger, Peak of Inflated Expectations, Trough of Disillusionment, Slope of Enlightenment, and Plateau of Productivity. So for DSA in semiconductor manufacturing, the technology first garnered attention when its potential applications in advanced lithography were identified (2000-2010), marking the Technology Trigger. Interest surged about 2011, leading to a Peak of Inflated Expectations around 2016/2017, evidenced by a spike in patent filings as companies raced to capitalize on the emerging technology. However, as practical and economic challenges such as defectivity and integration complexities became evident, the enthusiasm waned, and DSA entered the Trough of Disillusionment. During this phase, the technology's limitations led to a decline in interest as initial expectations were not met. Over time, as more sustainable applications and improvements are developed, DSA may progress into the Slope of Enlightenment, where understanding and optimization occur as described in the assessment by SemiAnalysis, before finally reaching the Plateau of Productivity in the years to come, where it becomes a standard part of semiconductor manufacturing processes. This progression through the hype cycle reflects the typical maturation path of innovative technologies in the industry. Please note that there is a delay in patent filing data of up to 18 months so 2022, 2023 and 2024 are not complete yet.

Patent filing since 2000 in DSA (Patbase, 2024-04-19)

2. Yes, Intel is actively filing DSA patents and in the lead, and so is TSMC, along with other key players in the ecosystem. Over the past decade, the pattern of DSA patent filings has been quite revealing. Initially, GlobalFoundries and IBM in Upstate New York were early filers. GlobalFoundries ceased their filings around the time they decided not to pursue 7 nm and nodes below. IBM also stopped filing after completing their 2 nm demonstration on 300 mm wafers in 2021. Main contenders Intel and TSMC have been consistently filing DSA patents throughout the hype cycle and have continued to do so. Notably, there has been a clear acceleration in Intel's patent filings since 2019, although there was a slight drop during the COVID-19 lockdowns. Looking at chemical suppliers, Merck has taken the lead, with increased filings beginning in parallel with Intel from 2019 onwards, and accelerating until today. Other suppliers such as JSR, Shin-Etsu, and Brewer Science are also active in the DSA space. In the segment of wafer equipment OEMs, Tokyo Electron and SCREEN have been dominant. However, SCREEN appears to have recently exited the game.

DSA Patent filing last decade (Patbase , 2024-04-19)

In Summary - good assessment by SemiAnalysis and i passes the Patbase Test!

Intel Receives ASML's First High-NA EUV Lithography Scanner, Pioneering Next-Gen Semiconductor Manufacturing

ASML has delivered its groundbreaking High-NA EUV lithography scanner, the Twinscan EXE:5000, to Intel Oregon. Marking a significant technological leap, this first-of-its-kind scanner boasts a 0.55 NA lens, enabling 8nm resolution for advanced semiconductor manufacturing. Designed for process technologies beyond 3nm, it promises to enhance chip production efficiency and reduce costs. Intel's early adoption of this state-of-the-art equipment, valued between $300-$400 million, positions them at the forefront of the industry, potentially setting new standards in High-NA manufacturing. This development represents a major milestone in semiconductor technology, signaling a new era of innovation and capability in chip production.

Intel Showcases Groundbreaking Transistor Innovations at IEDM 2023

At the 2023 IEEE International Electron Devices Meeting (IEDM), Intel introduced significant advancements in transistor technology that continue to drive Moore's Law forward. Intel's Components Research group demonstrated innovative 3D stacked CMOS transistors, enhanced with backside power and direct backside contacts. This breakthrough in transistor architecture allows for more efficient scaling and improved performance, marking a first in the industry.

3D Stacked CMOS Transistors

Intel displayed the ability to vertically stack complementary field effect transistors (CFET) with a scaled gate pitch down to 60 nanometers (nm). This technology, combined with backside power and direct backside contacts, underscores Intel's leadership in gate-all-around transistors and its capacity to innovate beyond RibbonFET.

Beyond Five Nodes in Four Years

Intel's PowerVia, set for manufacturing readiness in 2024, represents the first implementation of backside power delivery. At IEDM 2023, the company identified ways to extend and scale backside power delivery beyond PowerVia, utilizing backside contacts and other novel vertical interconnects for efficient device stacking.

Integration of Silicon and GaN Transistors

Intel successfully integrated silicon transistors with gallium nitride (GaN) transistors on the same 300 mm wafer. The "DrGaN" technology showcased at the event demonstrates Intel's advancements in high-performance integrated circuits for power delivery.

Advances in 2D Transistor Space

Intel presented high-mobility transition metal dichalcogenide (TMD) 2D channel materials, showcasing prototypes of high-mobility TMD transistors for both NMOS and PMOS. Additionally, Intel revealed the world’s first gate-all-around (GAA) 2D TMD PMOS transistor and the first 2D PMOS transistor fabricated on a 300 mm wafer.

These developments by Intel represent a significant stride in semiconductor research, promising to enhance the efficiency and capabilities of future computing technologies.

Revolutionizing Power Technology: Intel's Integrated CMOS Driver-GaN (DrGaN) Power Switch for Enhanced Efficiency and Density in Data Centers and Networks

Intel researchers have developed an integrated CMOS Driver-GaN (DrGaN) power switch, combining gallium nitride (GaN) and silicon CMOS technologies on a 300mm GaN-on-Si platform. This innovation is designed to meet the increasing power density and efficiency needs of data centers and networking platforms. The new device, termed DrGaN, features an e-mode HEMT and an integrated 3D monolithic Si PMOS. It's capable of addressing the power requirements of future CPUs and GPUs, showing excellent resistance and leakage performance. A key advancement is the development of a new gate-last process flow for 3D monolithic integration of GaN and Si CMOS through layer transfer. 

Intel researchers have developed an integrated CMOS Driver-GaN (DrGaN) power switch, combining gallium nitride (GaN) and silicon CMOS technologies on a 300mm GaN-on-Si platform.

This process involves completing the high-temperature activation steps for the Si CMOS transistors before depositing the GaN transistor's gate dielectric, solving a major challenge in integrating these two technologies. This method also allows GaN and Si CMOS transistors to share the same backend interconnect stack, which reduces resistance and mask count. The new technology demonstrates great promise for scaling, evidenced by a figure of merit of 0.59 (mΩ-nC)-1 for a 30nm gate-length GaN MOSHEMT. The paper includes images of the new process flow, the 3D monolithic integration, and the layout of a DrGaN unit cell, illustrating the advanced integration and circuitry of this novel power device.

Source: https://btbmarketing.egnyte.com/dl/m2hsmeZ6qH

Hamas' Brutal Attacks on Israel Could Disrupt Global Tech Supply Chain and Intel's Expansion Plans

The escalating Israel-Hamas war, after Hamas brutal attack on Israel and innocent civilians, is affecting the global tech sector. Many professionals, including top executives, are now serving as reservists in the Israel Defense Forces, as highlighted by EPSNews. Intel, a major private employer in Israel, along with other tech giants like Nvidia, Apple, Amazon, and Microsoft, faces potential disruptions, especially with facilities near conflict zones. The blockade in Gaza and transportation interruptions further strain the supply chain, emphasizing the tech industry's vulnerability to geopolitical challenges.

Intel factory in Kiryat Gat, employing about 5000 workers, which manufactures computer chips (wWikipedia), Location of Intel Fabs in Israel (Google)

Kiryat Gat, situated in Israel's Southern District, is known for Intel's semiconductor fabrication plants, including Fab 28 and the upcoming Fab 38. Founded in 1954, the city has grown significantly due to Jewish immigration over the decades and it remains an educational hub with 25 schools serving over 10,000 students.

The Israel-Hamas conflict has intensified concerns over the global semiconductor supply chain, as CNBC reports. With Israel being a key player in chip production, the geopolitical unrest poses risks to the semiconductor industry. The recent kidnapping of an Nvidia engineer further accentuates these threats, prompting tech firms to prioritize their employees' safety in the region.

Bloomberg reported this summer of Intel Corp.'s initiative to set up a new manufacturing facility in Israel. This move is part of Intel's strategy to diversify its production sources. While details remain undisclosed, the facility will focus on wafer fabrication. Intel's CEO, Pat Gelsinger, intends to expand manufacturing bases outside Asia. The plant, expected to operate from 2027, will be located in Kiryat Gat and is seen as a significant foreign investment in Israel. This development aligns with the global shift in chip manufacturing, as seen with Intel's investment in Poland and Micron Technology's potential investment in India.

Sources: 

War in Israel to Impact Electronics Supply Chain - EPS News

Intel to Build in Israel as Chipmakers Move Beyond East Asia - Bloomberg

Israel Is an Important Link in the Global Chip Supply Chain - Bloomberg

Kiryat Gat - Wikipedia

Intel Unveils Breakthrough 3D CFET Design at IEDM: Setting the Stage for Next-Gen Compact and Efficient Electronics

Intel researchers developed a 3D monolithic CFET device* with 3 n-FET nanoribbons atop 3 p-FET nanoribbons, separated by 30 nm gap. This industry-first device enabled the creation of functional inverters at a 60 nm gate pitch. Notably, it incorporated vertically stacked dual-Source/Drain epitaxy, dual metal work function gate stacks, and backside power delivery with direct device contacts. They also introduced a nanoribbon "depopulation" method for varying n-MOS/p-MOS device numbers. This research advances the understanding of CFET scalability for logic and SRAM applications and highlights key process enablers. The paper will be presented at the upcoming IEDM conference in San Francisco.

Comment: The stacked CMOS inverter at a 60 nm gate pitch represents an advancement in semiconductor design, allowing for denser circuits. The 60 nm distance between gates indicates a highly miniaturized design. Power vias provide vertical power connections to different layers, while direct backside device contacts enhance efficiency and heat dissipation. This development offers a glimpse into the  future electronic devices being more compact, efficient, and high-performing than deploying "planar" designs in one layer like the FinFETs and GAA-FETs of today.

ALD plays a key role in manufacturing 3D monolithic CFET devices by assisting in crafting the architecture and providing atomically precise and even thin film layers at small scales. ALD ensures even coverage, which is important for 3D designs, especially on vertical areas and inside deep gaps. It's used to put down important materials in transistor gate stacks (High-k/Metal Gates or HKMG), as well as barrier and seed layers. ALD also helps in doping (SSD - solid state doping), which changes how semiconductors behave, and in creating spacers, important for separating and defining parts of transistors. In brief, ALD helps improve the CFET design and its overall performance.

Figures from IEDM press kit

Paper: 29.2_A CFET-Based CMOS Inverter_Intel.docx (egnyte.com)

* A 3D monolithic CFET device combines three-dimensional stacking and the Complementary Field-Effect Transistor (CFET) design within a single semiconductor structure. This approach vertically integrates both n-type and p-type transistors on the same substrate, promoting tighter integration and reduced interconnect delays. By leveraging the complementary operation of CFET and the benefits of 3D stacking, the device aims to enhance performance, miniaturization, and efficiency in semiconductor technology.

The Semiconductor Showdown: TSMC's GAA FETs vs. Intel's RibbonFET

The semiconductor industry is witnessing a fierce competition between TSMC and Intel, as they advance transistor designs with TSMC's Gate-All-Around (GAA) FETs and Intel's RibbonFET. Atomic Layer Deposition (ALD) plays an instrumental role in crafting these intricate designs. As the race to dominate the microelectronics realm heats up, the innovations from these giants foretell a transformative phase for technology between 2024 and 2026. This article dives into their respective technologies, comparing their strategies and highlighting the future implications for the semiconductor industry.

Both TSMC and Intel are pushing the boundaries of semiconductor innovation with advanced transistor designs. TSMC's GAA (Gate-All-Around) FET (Field-Effect Transistor) technology and Intel's RibbonFET are prime examples of this evolution. ALD is crucial for GAA FET production, ensuring precision and atomically thin, conformal or on purpose non-conformal or selectively deposited films. As transistors miniaturized, ALD replaced traditional silicon dioxide gate dielectrics with high-k materials, reducing gate leakage and offering enhanced uniformity. One of the challenges in GAA FETs is accurately aligning the gate material around the channel; ALD facilitates this through self-aligned processes. Additionally, in configurations with multiple gates or nanosheets, ALD accurately deposits spacer materials, preserving the necessary separation between nanosheets. ALD also offers precise doping for GAA FETs, including NMOS and PMOS. With atomic-level control, ALD introduces dopants like phosphorus for NMOS and boron for PMOS. Given the shrinking device dimensions, ALD's precision becomes vital, especially when considering techniques like solid-state doping to achieve ultra-shallow profiles.

TSMC's Gate-All-Around (GAA) FET technology represents a significant shift from the traditional FinFET transistor design. In a GAA FET, the gate material wraps entirely around the channel, unlike the FinFET where the gate is only on three sides of a vertical fin. This complete encirclement provides enhanced control over the current flow through the channel, reducing leakage current and allowing for lower voltage operation. The result is improved energy efficiency and performance.

TSMC's roadmap to N2. (Image: TSMC)

On the other hand, Intel's RibbonFET introduces a similar gate-all-around design but with a unique twist. Instead of a traditional vertical fin, RibbonFET uses nanosheet technology, where multiple flat nano-sheets are stacked to form the channel. This design offers even better control of the current flow, leading to significant gains in performance and efficiency. RibbonFET is one of Intel's flagship innovations for its advanced nodes, emphasizing the company's commitment to reclaiming technology leadership in the semiconductor space.

Intel 20A Ribbon FET (intel.com)

In a recent article Tom´s Hardware (Anton Shilow, link below) compares the advanced semiconductor technology nodes from industry TSMC and Intel, focusing on TSMC's N3P and N2 nodes against Intel's 20A and 18A nodes. Forecasted for release between 2024 and 2026, these nodes represent the forefront of semiconductor innovation. TSMC's N3P, a 3nm-class node, is set to be available by 2025 and offers performance comparable to Intel's 18A. Interestingly, TSMC's 2nm-class N2, expected in the second half of 2025, is anticipated to outpace Intel's 18A in terms of power, performance, and area advantages. Intel's 20A, arriving in 2024, promises significant advancements by introducing RibbonFET gate-all-around transistors and a backside power delivery network. The subsequent 18A will further refine these innovations. While TSMC leans on its proven FinFET technology for the N3P, it plans to introduce nanosheet GAA transistors in the N2. 

As the semiconductor race intensifies, both companies are heavily invested in outpacing each other, with TSMC focusing on technology maturity and cost-effectiveness, and Intel aiming to regain its technology leadership. The dynamics between these tech giants will shape the semiconductor industry's future.

Comparison of Advanced Semiconductor Technology Nodes: TSMC N3P & N2 vs. Intel 20A & 18A, highlighting the competitive landscape of the semiconductor industry for the years 2024-2026 based on Toms Hardware article below.

Sources: 

TSMC: Our 3nm Node Comparable to Intel's 1.8nm Tech | Tom's Hardware (tomshardware.com)

Intel and TSMC company web pages

Intel to Sell 10% Stake in IMS Nanofabrication to TSMC for $4.3 Billion

Intel will sell a 10% stake in IMS Nanofabrication to TSMC, valuing IMS at $4.3 billion, maintaining Intel's majority ownership. IMS leads in multi-beam mask writing tools for advanced extreme ultraviolet lithography, crucial for AI and mobile applications. This investment enhances IMS' independence and fosters innovation, including high-numerical-aperture EUV technology. The deal is set to close in Q4 2023. IMS is vital for semiconductor industry growth, with the market projected to reach $1 trillion by 2030. Intel acquired IMS in 2015 and sold a 20% stake to Bain Capital earlier in 2023, while TSMC's partnership with IMS dates back to 2012.

About IMS Nanofabrication

IMS Nanofabrication Global, LLC, a majority-owned subsidiary of Intel Corporation, is the global technology leader for multi-beam mask writers. Its customers are the largest chip manufacturers in the world, who rely on its technology to produce current and future chip generations. IMS’ innovative multi-beam writers play a key role in chip manufacturing and provide significant added value to the semiconductor industry. They are continually customized and refined by an interdisciplinary team, in line with the latest market demands. Over the last 10 years, IMS has perfected its electron-based multi-beam technology. The first-generation multi-beam mask writer, MBMW-101, is successfully operating all over the world. The second-generation multi-beam mask writer, MBMW-201, entered the mask writer market in the first quarter of 2019 for the 5nm technology node. And this year, IMS is launching MBMW-301, a fourth-generation multi-beam mask writer that delivers unprecedented performance. Learn more at www.ims.co.at/en/.

ASML Remains on Track to Deliver High NA EUV Machines in 2023

ASML, the leading semiconductor equipment manufacturer, is set to ship the first pilot tool from its next product line in 2023, despite some supplier delays, according to CEO Peter Wennink. These High NA EUV machines, crucial for top chipmakers to create smaller and better chips in the coming decade, will cost over $300 million euros each and provide up to 70% better resolution. ASML currently dominates the lithography market, a pivotal step in chipmaking, and is seeing strong demand for its older DUV machines, with 30% sales growth forecasted in 2023, primarily driven by Chinese customers.

ASML's High NA EUV machines are used by a range of prominent semiconductor manufacturers, including TSMC, Intel, Samsung, SK Hynix, and Micron. These chipmakers rely on ASML's cutting-edge lithography equipment to manufacture semiconductor chips, from microprocessors to memory chips.

"High NA" stands for "High Numerical Aperture." Numerical Aperture (NA) is a measure of the ability of an optical system, such as a lens or mirror, to gather and focus light. A higher numerical aperture indicates a greater ability to capture light and provide finer detail and resolution in imaging or lithography processes. ASML's High NA EUV machines, are designed to gather light from a wider angle compared to their previous generation tools. This wider angle collection of light allows for significantly improved resolution in the semiconductor manufacturing process, making it possible to create smaller and more advanced semiconductor chips with greater precision required for the Ångström Era - basically the sub 2 nm nodes.

Source:

ASML to ship first pilot tool in its next product line in 2023 -CEO | Reuters

Intel Takes Strategic Steps to Regain Semiconductor Chip Leadership

Intel plans to separate its manufacturing and fabless units to regain its semiconductor chip leadership. The move aims to serve emerging markets and make chip manufacturing more efficient. Intel seeks to emulate TSMC's success and become the second-largest external foundry by 2030.

In an effort to reclaim its position as a leader in the semiconductor chip industry, Intel has announced plans to separate its manufacturing and fabless units. This strategic move aims to address evolving market dynamics and capitalize on emerging sectors such as cloud computing, edge computing, and artificial intelligence (AI). By granting independence to its foundry business and diversifying its chip production, Intel aims to regain its competitive edge and accelerate chip development.

Diversifying into New Markets

Intel's factories have traditionally focused on serving the PC and server markets, but the company recognizes the need to adapt to the changing landscape. By separating fabless and manufacturing operations, Intel can now cater to a broader customer base, including external clients. The new fabs, set to be operational by early 2024, will manufacture chips for non-Intel customers, making Intel a potential competitor to contract chip manufacturers like TSMC.

Emulating the TSMC Playbook

Intel's strategy shares similarities with Taiwan Semiconductor Manufacturing Co. (TSMC), which has successfully produced chips for companies like Nvidia, Apple, and AMD. TSMC's approach of guaranteeing capacity to long-term partners during the recent chip shortage has proven effective. Intel aims to replicate this success by becoming the second-largest external foundry by 2030 and generating more than $20 billion in manufacturing revenue.

Competing for Internal Fab Capacity

The separation of fabless and manufacturing units introduces a new dynamic within Intel. Internal chip design units will now compete with external customers for fab capacity, potentially accelerating Intel's internal chip design efforts. The competition for volume will drive efficiency and faster innovation, as internal business units can leverage third-party foundries if they are willing to pay top dollar for guaranteed capacity.

Reviving Manufacturing Prowess

Intel's ability to deliver chips on time has been a key challenge, allowing TSMC to emerge as a leader in the industry. However, Intel aims to regain its position by focusing on advanced nodes such as the Intel 18A process, which incorporates cutting-edge technologies like gate-all-around (GAA) transistors. By emphasizing more efficient manufacturing processes and performance improvements, Intel intends to win back customers and regain its reputation as a reliable chip manufacturer.

Intel is expanding as a foundry in Europe

Intel's expansion plans in Europe took a significant step forward as the company signed a deal with the German government to build a €30 billion chip manufacturing site in Magdeburg. Germany will cover a third of the investment, marking the largest foreign direct investment in the country's modern history. The agreement was signed during a meeting between German Chancellor Olaf Scholz and Intel CEO Pat Gelsinger in Berlin. The investment will significantly expand Intel's production capacity in Europe and is seen as a crucial strategic move for Germany and Europe to establish self-sufficiency in strategic technologies. The project, known as the "Silicon Junction," is expected to create 3,000 high-quality jobs and additional positions in supplier networks. The EU's executive branch will review the plan to ensure fair competition. With this expansion, Germany aims to become one of the major global semiconductor production sites and reduce its dependence on imported chips and global supply chains. The completion of the twin semiconductor plants is expected by 2027 and will contribute to the EU's goal of decreasing reliance on China and the US for microchip production.

Conclusion

Intel's decision to separate its manufacturing and fabless units marks a strategic shift aimed at regaining its leadership in the semiconductor chip industry. By diversifying into emerging markets, emulating successful models like TSMC's, and focusing on advanced manufacturing processes, Intel hopes to reclaim its competitive edge and position itself as a leading player in the evolving landscape of chip manufacturing.

Source: 

Intel to build €30 billion chip plant in Germany | Euronews

Intel Looks to Regain Semiconductor Chip Leadership from TSMC; Separates Manufacturing and Fabless Units (hpcwire.com)

CBS 60 Minutes - Chip shortage highlights U.S. dependence on fragile supply chain

Seventy-five percent of semiconductors, or microchips — the tiny operating brains in just about every modern device — are manufactured in Asia. Lesley Stahl talks with leading-edge chip manufacturers, TSMC and Intel, about the global chip shortage and the future of the industry.

• Pat Gelsinger: 25 years ago, the United States produced 37% of the world's semiconductor manufacturing in the U.S. Today, that number has declined to just 12%
• Within the world of global collaboration, there's intense competition. Days after Intel announced spending $20 billion on two new fabs, TSMC announced it would spend $100 billion over three years on R&D, upgrades, and a new fab in Phoenix, Arizona, Intel's backyard, where the Taiwanese company will produce the chips Apple needs but the Americans can't make.

Intel CEO Pat Gelsinger shows CBS correspondent Lesley Stahl a silicon wafer.

Taiwan-based TSMC, which supplies microchips for most U.S. cars, tells 60 Minutes it will be caught up with car chip production by the end of June. So, does that mean the dire shortage will end in two months? Well, not quite. https://t.co/Wj1yFffaKS pic.twitter.com/Zx3dnRwU0o

— 60 Minutes (@60Minutes) May 2, 2021

Intel is spending $20 billion to build two new chip plants in Arizona

Intel announced on Tuesday that it will spend $20 billion to build two major factories in Arizona. The news comes amid a worldwide chip shortage that is snarling industries from automobiles to electronics and worries the U.S. is falling behind in semiconductor manufacturing. The announcement signals that Intel will continue to focus on manufacturing.

Next chance to get deep insights to Intel quality demands and advanced metrology & analytic for the material supply chain will be at the CMC2021 Conference, broadcasted from San Diego, USA, APril 14-15:

KEYNOTE : Jeanne Yuen-Hum, Vice President of Manufacturing & Operations, and Director of Global Supply-Chain Quality & Reliability, Intel Corporation "The Cost of Quality"

Alex Tregub, PhD Staff Engineer Intel Corporation "From Egyptian Royal Cubit to SEMI Guides for CMP consumables – Industry Standards"

Conference: https://cmcfabs.org/agenda-2021/

• Intel invests $20 billion in two Arizona factories, 7nm chips coming in 2023
• Intel announces steps to boost chip manufacturing
• ‘Intel is back:’ New CEO’s plan to make chips for others excites investors
• Stocks making the biggest moves after the bell: GameStop, Adobe, Intel
• Intel is spending $20 billion to build two new chip plants in Arizona

Intel remains in the lead in 2020 semiconductor sales

IC Insights’ November shows the forecasted top-25 semiconductor suppliers in 2020. Seven top-15 semiconductor suppliers forecast to show ≥22% growth this year with Nvidia expected to post a huge 50% increase. The top-15 companies semiconductor sales are broken out into IC and O-S-D (optoelectronic, sensor, and discrete) device categories for 2019 and 2020. The forecasted 2020 top-15 semiconductor supplier ranking includes eight suppliers headquartered in the U.S., two each in South Korea, Taiwan, and Europe, and one in Japan.

Intel remains No 1. followed by Samsung and TSMC. 2020 show a very high growth for Fabless companies Qualcomm, Nvidia, MediaTek, Apple and AMD.

The Memory segment (DRAM and Flash) is led by SK Hynix +14% followed by Samsung +9% (incl. foundry) and Micron is down by -3%.

Please read the full IC Insights report here: LINK

Intel to present 3D stacked Nanoribbon Transistors for Continued Moore’s Law Scaling at IEDM 2020

Intel to present stacked gate-all-around FET (GAA-FET) technology, i.e., a complementary FET (CFET) at IEDM2020. In CFETs, the idea is to stack both nFET and pFET wires on each other. A CFET could stack one nFET on top of a pFET wire, or two nFETs on top of two pFET wires. This ‘folding’ of the nFET and pFET eliminates the n-to-p separation bottleneck, reducing the cell active area footprint (LINK). Please find the announcement below:

Home-2020 - IEDM 2020 ieee-iedm.org IEDM Conference 2020. To Be Held Virtually December 12-18. The on demand portion of the conference will begin on December 5th. Intel to present 3D stacked Nanoribbon Transistors for Continued Moore’s Law Scaling: 

Stacked NMOS-on-PMOS Nanoribbons: From planar MOSFETs, to FinFETs, to gate-all-around (GAA) or nanoribbon devices, novel transistor architectures have played a critical role in driving performance predicted by Moore’s Law. Intel researchers will describe what may be the next step in that evolution: NMOS-on-PMOS transistors built from multiple self-aligned stacked nanoribbons. This architecture employs a vertically stacked dual source/drain epitaxial process and a dual metal gate fabrication process, enabling different conductive types of nanoribbons to be built so that threshold voltage adjustments can be made for both top and bottom nanoribbons. The approach combines excellent electrostatics (subthreshold slope of <75 mV/dec) and DIBL (<30mV/V for gates ≥30nm) with a path to significant cell size reduction due to the self-aligned stacking. These devices were used to build a functional CMOS inverter with well-balanced voltage transfer characteristics. (Paper #20.6, “3-D Self-Aligned Stacked NMOS-on-PMOS Nanoribbon Transistors for Continued Moore’s Law Scaling,” C.-Y. Huang et al, Intel) 

Paper #20.6, “3-D Self-Aligned Stacked NMOS-on-PMOS Nanoribbon Transistors for Continued Moore's Law Scaling,” C.-Y. Huang et al, Intel

Paper Information (IEDM 2020) : LINK

Figures from IEDM 2020 Press briefing Material -Press kit : LINK

In the images above:

·        (1) shows the evolution of transistor architectures from planar, to FinFETs, to nanoribbons and to a 3D CMOS architecture.

·        (2) (a) shows a 3D schematic diagram of stacked CMOS Si nanoribbon transistors with NMOS on PMOS, (b) describes the process flow; (c) is a TEM image of a stacked multiple-nanoribbon CMOS inverter with a 40-nm gate length and inner (V_ss) and outer (V_cc) contacts, a common gate input (V_IN) and an inverter output node (V_OUT); while (d) is a TEM image of two Si NMOS nanoribbons atop 3 Si PMOS nanoribbons.

·       (3) (a) is a process flow of the vertically stacked dual S/D EPI process, while (b) shows P-EPI selectively grown on the bottom three nanoribbons, (c) shows N-EPI selectively grown on the top two nanoribbons, and (d) features TEM and EDS images showing selective N-EPI and P-EPI growth on the stacked nanoribbon transistors.

·       (4) (a) is a process flow of the vertically stacked dual metal gate process; (b) is a TEM image and (c, d) are EDS images of the dual metal gate with N-WFM (WFM = work function metal) on the top two nanoribbons and P-WFM on the bottom three nanoribbons.

Process Power: The New Lithography - Advanced Energy

Here is a very insightful article by PETER GILLESPIE, VP & GM, Semiconductor Products, Advanced Energy Industries on the progress of Plasma RF Generators and Matching Networks. The article looks at applications in 3DNAND High Aspect Ratio Contacts (HARC) and Logic FinFET transitor fabrication using reactive ion etching and plasma CVD using the latest plasma technology. This is a an articel in a series of three in SEMICONDUCTOR DIGEST entitled “Process Power Steps Out from the Shadows,” looking at the leading edge technology node process challenges to highlight key drivers that are fundamentally transforming the role and importance of process power. 

Process Power: The New Lithography (SEMICONDUCTOR DIGEST, LINK) 

 

"Evolution of RF power supplies (plasma generators) and RF matching networks. Today’s RF power delivery systems are highly sophisticated with frequency tuning, complex pulsing regimes, and agile micro-second response." (Below)

 

 

TechInsights’ Memory Process: 3D NAND Word Line Pad webinar

TechInsights’ ‘Memory Process: 3D NAND Word Line Pad‘ #webinar compares 9x-layer 3D NAND devices from major manufacturers and discusses the process sequence with emphasis on the word line pad (WLP). Watch on demand here LINK 

 

Screendump from Webinar

2020 CMC Conference New Session on Advanced Packaging Materials - CHIPS & EMIB for SiP

San Diego, CA, December 17: The Critical Materials Council (CMC) of semiconductor fabricators and TECHCET announce a new addition to the 2020 CMC Conference:  Advanced Packaging Materials. Scheduled for April 23-24 in Hillsboro, Oregon, the 5th CMC Conference, will explore actionable technical and value-chain trends of critical materials for global semiconductor fabs and feature keynotes from leaders in semiconductor technology and materials. The conference keynote address this year will be: "Critical Materials Pushing the Limits for Semiconductor Manufacturing" by Bruce Tufts, Vice President of Technology and Director of Fab Materials Organization, Intel Corp. Sessions will cover:  I. Global Value-chain Issues, Including Economics and Regulations, II. Immediate Challenges of Materials & Manufacturing, III. Emerging Materials in R&D and Pilot Fabrication, and   New this year is a fourth session, IV. Advanced Packaging Materials Lead by Session Chairman Jim Hannah, Product Development and Applications Manager of SEH, the Advanced Packaging Materials Session will address, system level performance scaling issues and the increased reliance on packaging. As explained by Mr. Hannah, “We see the lines starting to blur between packaging and the back-end wiring on-chip. The CMC Conference will cover both current challenges and future requirements of packaging materials needed to support this middle-ground." A keynote address on “The Future of Silicon as a Packaging Material" for this new session will be provided by Dr. Subramanian Iyer, principle of UCLA’s Center for Heterogeneous Integration and Performance Scaling (CHIPS) consortium, IEEE Fellow, IBM Fellow, IIT Distinguished Alumnus, and UCLA Distinguished Chancellor's Professor of both Electrical and Computer Engineering and Materials Science and Engineering.

Dr. Lauren Link, Intel's Technical Program Manager, Substrate Business Group, will present on materials to enable Embedded Multi-die Interconnect Bridge (EMIB) connections between silicon chiplets in advanced Heterogeneous Integration (HI) System-in-Package (SiP) products. CMC member companies will be attending the public CMC Conference, which follows the annual members-only CMC meeting to be sponsored by Intel and held April 21-22. Conference attendees will include industry experts handling supply-chains, business-development, R&D, and product management, as well as academics and analysts. Business drives our world, but technology enables the profitable manufacturing of semiconductor devices and facilitates the introduction of new materials. To submit a paper for consideration, send a 1-page abstract focusing on critical materials supply dynamics by January 15, 2020 to  cmcinfo@techcet.com For more information and registration: cmcfabs.org/cmc-conference-2020

For more information on CMCFabs or CMC Associate Memberships, please contact Diane Scott at dscott@techcet.com. For information on sponsoring the CMC Conference please contact Yvonne Brown at ybrown@techcet.com, +1-480-382-8336 x1.

CMC Fab members include:

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