Technological Innovations in Semiconductor Manufacturing: Insights from Tokyo Electron's 2024 Integrated Report

This summary, based on Tokyo Electron's Integrated Report 2024, provides insights into the future outlook of the Wafer Fab Equipment (WFE) market, with a particular focus on the technological advancements driving demand for advanced etch and deposition processes, including the transition to next-generation semiconductor architectures like GAAFET (Gate-All-Around Field-Effect Transistor). As the industry evolves, these technologies are becoming increasingly critical to maintaining the pace of innovation and ensuring the continued scaling of semiconductor devices.

The Wafer Fab Equipment (WFE) market is set for significant growth, driven by several key factors: the rising demand for semiconductors fueled by advanced technologies like AI, IoT, 5G, and autonomous vehicles; the ongoing transition to more advanced process nodes, which requires increasingly complex and precise equipment, particularly in etching, deposition, and lithography; substantial investments in new semiconductor fabs globally, expected to boost WFE demand as these facilities come online between 2022 and 2026; and the emergence of new semiconductor architectures like 3D NAND, DRAM, and GAAFET, which necessitate leading-edge WFE to manage the heightened complexity of these manufacturing processes.

According to Tokyo Electron (TEL), the future outlook of the Wafer Fab Equipment (WFE) market is poised for substantial growth, largely driven by the rapid technological advancements in the semiconductor industry. The escalating complexity of semiconductor devices, particularly in the areas of 3D NAND, DRAM, and advanced logic devices, is creating an increasing demand for sophisticated etch and deposition technologies, such as Atomic Layer Deposition (ALD). These technologies are critical for enabling the high precision and performance required in modern semiconductor manufacturing.

For 3D NAND, the trend towards higher layer counts—potentially reaching 500 to 1,000 layers—necessitates advanced etching processes capable of creating deep holes and trenches with high aspect ratios. This is essential for maintaining structural integrity while maximizing storage density. Similarly, ALD is becoming increasingly important in the deposition of conformal films over these intricate 3D structures, ensuring uniformity at the atomic level, which is crucial for device performance and reliability.

DRAM technology is also evolving, with the shift towards 3D DRAM structures demanding new solutions in both etching and deposition. As memory cells are stacked vertically, the need for precise etch processes to define these high aspect ratio structures becomes critical. Concurrently, ALD plays a vital role in creating ultra-thin films that can meet the stringent requirements of these new architectures, enabling the continued scaling of DRAM technology.

The transition to GAAFET (Gate-All-Around Field-Effect Transistor) structures marks a significant evolution in semiconductor technology, necessitating highly advanced etch processes. These processes must achieve extreme precision in defining the narrow, high aspect ratio features characteristic of GAAFETs, ensuring device integrity and performance as scaling continues. The integration of etch with ALD is particularly crucial, allowing for the precise control of gate structures at an atomic level, which is essential for optimizing device characteristics. Additionally, the co-optimization of etching with high-NA EUV lithography ensures that the finest features can be accurately patterned and etched, supporting the successful scaling of next-generation devices. As semiconductor architectures become more complex, the role of advanced etch technologies will be pivotal in enabling the high performance and reliability demanded by GAAFET and beyond.

Furthermore, the industry’s focus on sustainability is driving demand for WFE that not only enhances performance but also reduces environmental impact. Technologies like ALD and advanced etch processes are being developed with an eye towards lowering power consumption and minimizing CO2 emissions, aligning with broader goals of achieving net-zero emissions in semiconductor manufacturing.

Overall, the WFE market is expected to see robust growth, underpinned by the critical role of etch and deposition technologies in advancing semiconductor innovation. These technologies are not only essential for maintaining the pace of Moore’s Law but also for enabling new device architectures that will define the future of the semiconductor industry. With significant investments in R&D and a strategic focus on early-stage technology development, the WFE market is well-positioned to meet the evolving needs of semiconductor manufacturers.

Source: Integrated Report/Annual Report | Investor Relations | Tokyo Electron Ltd. (tel.com)

AMEC's Revenue Grows with Advanced Etch Technology Fueling China's Semiconductor Surge

AMEC, China's etching tools giant, forecasts a 30%+ revenue jump in 2023, driven by local semiconductor demand and replacing US parts with domestic ones.

Advanced Micro-Fabrication Equipment Inc. (AMEC), a leading Chinese provider of semiconductor etching tools, is set to witness a significant revenue surge exceeding 30% in 2023, buoyed by robust demand from China's burgeoning semiconductor manufacturing sector. AMEC's strategic focus on core technological innovations has enabled the deployment of an array of sophisticated chip-making equipment to domestic fabs, catering to the critical process of etching in semiconductor production. AMEC's revenue for 2023 is projected to hit 6.26 billion yuan ($879 million), marking a 32.1% increase from the previous year, underpinned by a substantial 8.36 billion yuan in new orders. This growth trajectory is further evidenced by an impressive net profit forecast ranging between 1.7 billion yuan and 1.85 billion yuan, showcasing year-on-year growth of 45% to 58%. Central to AMEC's success is its adeptness in navigating the challenges posed by tightened US semiconductor sanctions. 

The company has embarked on an ambitious strategy to diminish reliance on foreign components, with a commitment to replacing 80% of US-restricted components with locally sourced parts by the end of last year, aiming for a complete transition by 2024. AMEC's product lineup, particularly its core etching tools like the capacitively coupled plasma (CCP) and inductive coupled plasma (ICP) systems, is pivotal to its revenue stream, anticipated to constitute 75% of its total earnings for the year. These etching tools, essential for the intricate process of sculpting microscopic circuits onto semiconductor wafers, have gained substantial traction among Chinese foundries. This is a testament to AMEC's technological prowess and its role in bolstering China's self-sufficiency in semiconductor manufacturing. 

The company's market share in domestic CCP equipment is expected to soar to 60%, a significant leap from 24% in October 2022. Similarly, AMEC's foothold in the ICP equipment market is projected to reach an impressive 75%, marking a dramatic rise from virtually zero. This growth is particularly notable against the backdrop of declining mainland sales of once-dominant US chip equipment manufacturers like Lam Research. AMEC's technological offerings, characterized by advanced etching capabilities and innovation-driven development, cater primarily to China's semiconductor fabs. These fabs are integral components of the nation's strategic push towards self-reliance in semiconductor production, a sector that has become a focal point of international geopolitical tensions and trade restrictions. As such, AMEC not only stands as a technological leader but also as a key enabler of China's ambitions in the global semiconductor arena.

Source: Chinese etching tools giant AMEC sees 2023 sales rise more than 30% on strong demand from mainland semiconductor fabs (yahoo.com)

Revolutionary Study Unveils Enhanced Uniformity and Selectivity in TiO2 Films for Nanoelectronics Manufacturing

Researchers Achieve 2× Improvement in TiO2 Film Thickness and Pattern-dependent Uniformity in 45 nm Half-pitch Patterns

In a groundbreaking study, researchers have made significant advancements in the area-selective deposition (ASD) of TiO2 films, bringing unprecedented uniformity and selectivity to nanoelectronics manufacturing. The research, led by Rachel A. Nye and her team at imec, KU Leuven, and North Carolina University, demonstrates the successful implementation of passivation + deposition + etch supercycle process in industrially relevant 45 nm half-pitch patterns.

By leveraging the unique capabilities of the DMA-TMS inhibitor, the researchers achieved remarkable results. The TiO2 atomic layer deposition (ALD) process yielded a 2× improvement in film thickness, depositing approximately 8 nm of TiO2 with 88% uniformity and 100% selectivity on SiO2/TiN line/space patterns. Moreover, the study revealed lower defectivity on pattern sidewalls, top surfaces, and corners compared to previous reports.

A key finding was pattern-dependent uniformity, emphasizing the significance of understanding and optimizing processes at specific feature scales. As feature sizes continue to shrink, the researchers anticipate further improvements in uniformity. The study also highlighted the importance of refining passivation, deposition, and etch parameters for enhanced selectivity and uniformity control.

The research opens doors to a wide range of applications for TiO2 thin films in nanoelectronics, including antireflection coatings, sensors, photocatalysts, and etch-resistant layers. The study provides valuable insights into the quantification of uniformity and selectivity in nanoscale patterns, serving as a benchmark for future advancements in nanoscale ASD. The results have significant implications for the design and fabrication of electronic devices on an industrial scale.

Source: Quantified Uniformity and Selectivity of TiO2 Films in 45‐nm Half Pitch Patterns Using Area‐Selective Deposition Supercycles - Nye - Advanced Materials Interfaces - Wiley Online Library

Foundations of atomic-level plasma processing in nanoelectronics (Open Access)

Foundations of atomic-level plasma processing in nanoelectronics

Karsten Arts, Satoshi Hamaguchi, Tomoko Ito, Kazuhiro Karahashi, Harm C M Knoops, Adriaan J M Mackus and Wilhelmus M M (Erwin) Kessels

Plasma Sources Sci. Technol. 31 103002 OPEN ACCESS  

https://iopscience.iop.org/article/10.1088/1361-6595/ac95bc#psstac95bcf10

This article discusses key elementary surface-reaction processes in state-of-the-art plasma etching and deposition relevant to nanoelectronic device fabrication and presents a concise guide to the forefront of research on plasma-enhanced atomic layer etching (PE-ALE) and plasma-enhanced atomic layer deposition (PE-ALD). As the critical dimensions of semiconductor devices approach the atomic scale, atomic-level precision is required in plasma processing. The development of advanced plasma processes with such accuracy necessitates an in-depth understanding of the surface reaction mechanisms. With this in mind, we first review the basics of reactive ion etching (RIE) and high-aspect-ratio (HAR) etching and we elaborate on the methods of PE-ALE and PE-ALD as surface-controlled processing, as opposed to the conventional flux-controlled processing such as RIE and chemical vapor deposition (CVD). Second, we discuss the surface reaction mechanisms of PE-ALE and PE-ALD and the roles played by incident ions and radicals in their reactions. More specifically, we discuss the role of transport of ions and radicals, including their surface reaction probabilities and ion-energy-dependent threshold effects in processing over HAR features such as deep holes and trenches.

Examples of applications of PE-ALD in patterning, logic device fabrication, and memory device fabrication. The layers prepared by PE-ALD are indicated in (dark) red. In these examples, i.e., self-aligned quadruple patterning (A), gap-filling (B), and dielectric lining (C, left), the film conformality, thickness control, and material quality provided by PE-ALD are essentia

Semiconductor Equipment Consumables - Silicon Parts, in High Demand with Continued Shift Toward Asia

San Diego, CA, September 8, 2022: TECHCET—the electronic materials advisory firm providing business and technology information— reports that the demand for high-purity Silicon Parts for semiconductor manufacturing equipment will continue strong in 2022. This forecast is expected as equipment sales grow and fabs expansions continue to ramp. The Silicon Parts market is expected to top US $900 million, a 10% increase from US $824 million in 2021. TECHCET forecasts the 2021 to 2026 CAGR for this market to grow at an almost 6% rate, as shown in the graph below and described further in TECHCET’s Newly Released Critical Materials Report™ (CMR) on Silicon Equipment Components.

“Silicon Parts are primarily consumed in etch equipment systems, so market growth is heavily tied to chip production and influenced by new etch equipment sales,” states Dan Tracy, senior analyst at TECHCET. Additionally, the replacement part segment represents about 70% of the market as these consumable parts have a finite lifetime, and need to be replaced per a fab’s maintenance schedule. Given industry fab investment trends, about 66% of the new and replacement parts are for the 300 mm fab manufacturing segment.

To read the full article, go to: https://lnkd.in/gK-fp8H9

For more information details on the Silicon Parts market and growth trajectory, go to: https://lnkd.in/gM9GMNUs

APTC from South Korea is developing CVD, ALD and oxide etcher systems as it expands its portfolio

Since 2002, APTC has engaged in the manufacturing of dry etcher systems for mass semiconductor production. Today, the company supplies 300mm plasma etching systems, 200mm plasma etching systems, plasma doping systems, and light-emitting-diode etching systems. Over the past 19 years, APTC has been an established supplier for SK Hynix in South Korea and its mass production subsidiaries in China. SK Hynix is the second-largest memory chipmaker and third-largest semiconductor company globally.

300 mm Leo Poly Etcher system from APTC

With its numerous patents, awards, original plasma source technology and market leadership as South Korea’s sole domestic supplier of poly etching equipment, APTC is gearing up for growth at home and overseas. Fully committed to research and development (R&D) in pursuit of quality and innovation, APTC has invested US$20 million in American engineering capabilities, maintaining an R&D office in the United States, where it aims to work with tier-one semiconductor companies.

Listed on the Korea Exchange under the leadership of its current CEO, the company has revitalized its business strategy with plans to explore new markets, new clients, and new technologies. The state-of-the-art plasma technology also has a number of applications in the next-generation dry etch sector and its related innovations.

In semiconductor manufacturing, chemical vapor deposition (CVD) is a method used to produce high-performance and high-quality solid materials such as thin film in a vacuum, while atomic layer deposition (ALD) is a vapor phase technique of laying thin films on a substrate. APTC is developing CVD, ALD, and oxide etcher systems as it expands its portfolio of offerings.

Source: New strategy, markets and innovation fuel APTC’s rise in semiconductor etcher systems (LINK)

Process Power: The New Lithography - Advanced Energy

Here is a very insightful article by PETER GILLESPIE, VP & GM, Semiconductor Products, Advanced Energy Industries on the progress of Plasma RF Generators and Matching Networks. The article looks at applications in 3DNAND High Aspect Ratio Contacts (HARC) and Logic FinFET transitor fabrication using reactive ion etching and plasma CVD using the latest plasma technology. This is a an articel in a series of three in SEMICONDUCTOR DIGEST entitled “Process Power Steps Out from the Shadows,” looking at the leading edge technology node process challenges to highlight key drivers that are fundamentally transforming the role and importance of process power. 

Process Power: The New Lithography (SEMICONDUCTOR DIGEST, LINK) 

 

"Evolution of RF power supplies (plasma generators) and RF matching networks. Today’s RF power delivery systems are highly sophisticated with frequency tuning, complex pulsing regimes, and agile micro-second response." (Below)

 

 

Lam’s new Sense.i Etch platform delivers industry-leading output and innovative sensor technology

• Lam Research (NASDAQ:LRCX) introduces the Sense.i tool, which etches finer 3D details on silicon wafers for chips.
• The Sense.i platform enables the critical etch capabilities required to continue advancing uniformity and etch profile control for maximizing yield and lowering wafer costs
• 3D features can help Lam customers like Samsung and SK Hynix put more memory capacity into small areas such as smartphones.

FREMONT, Calif., March 03, 2020 (LINK) -- Lam Research Corp. (Nasdaq: LRCX) today announced the launch of a completely transformed plasma etch technology and system solution, designed to provide chipmakers with advanced functionality and extendibility required for future innovation. Lam’s groundbreaking Sense.i™ platform offers unparalleled system intelligence in a compact, high-density architecture to deliver process performance at the highest productivity, supporting logic and memory device roadmaps through the coming decade.

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With core technology evolved from Lam’s industry-leading Kiyo® and Flex® process modules, the Sense.i platform enables the critical etch capabilities required to continue advancing uniformity and etch profile control for maximizing yield and lowering wafer costs. As dimensions shrink and aspect ratios increase, the Sense.i platform is designed to support future technology inflections.

Powered by Lam’s Equipment Intelligence® technology, the self-aware Sense.i platform enables semiconductor manufacturers to capture and analyze data, identify patterns and trends, and specify actions for improvement. Sense.i also features autonomous calibration and maintenance capabilities that reduce downtime and labor costs, and delivers machine learning algorithms that allow the tool to self-adapt to minimize process variations and maximize wafer output.

The Sense.i platform has a revolutionary space-saving architecture that will help customers meet their future wafer output targets by producing more than a 50% improvement in etch output density. As semiconductor manufacturers develop smarter, faster, and denser chips, processes are rapidly growing in complexity and number of steps. This requires a greater number of process chambers in a fab and reduces total output for a given floor space. The Sense.i platform’s smaller footprint benefits either a new fab build or a fab undergoing a node-to-node technology conversion.

“Lam is introducing the most innovative etch product that has been developed in the last 20 years,” said Vahid Vahedi, senior vice president and general manager of the Etch product group at Lam Research (LRCX). “Sense.i extends our technology roadmap to meet our customers’ next-generation requirements while solving the critical cost scaling challenges they’re facing in their business. With more than four million wafers processed on Lam etch systems every month, Lam has an installed-base that provides extraordinary learning to innovate, design, and produce the best tools for semiconductor manufacturing.”

The Coventor's SEMulator3D software platform

Semiconductor process engineers would love to develop successful process recipes without the guesswork of repeated wafer testing: Process modeling is a powerful technique to predict process results quickly and locate potential process issues without wafer-based testing. These process-modeling capabilities are fully-integrated in the Coventor's (a Lam Research Company) SEMulator3D software platform. Once a process model is built in SEMulator3D, any changes to a proposed integration scheme or device design (such as layout or hardmask thickness changes) can be easily visualized and quantified, without the time and expense of wafer testing. 

The process of building a 3D device using a process model (instead of physical wafers) is called “virtual fabrication”. Using virtual fabrication in conjunction with calibration cycles, process engineers and integration engineers can easily develop a process and integration model. The accuracy and predictability of any model is dependent on the quality of the input data, but SEMulator3D is able to model a wide range of physical process behavior with great accuracy and can solve highly-advanced process problems.

Source: An Introduction to Semiconductor Process Modeling: Process Specification and Rule Verification (LINK)

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By Abhishekkumar Thakur

Oxford Instruments Partners ITRI for Micro LED Development with Plasma Etch Solutions

[LED Inside, LINK] Oxford Instruments Plasma Technology (OIPT) announced that it has worked with Taiwan’s Industrial Technology Research Institute (ITRI) by providing multiple PlasmaPro 100 systems including both etch and deposition for ITRI’s Micro LED R&D program.

 

The PlasmaPro 100 ICP process solutions are designed to support leading edge device applications such as Lasers, RF, Power and advanced LEDs.

Chinese AMEC 5nm plasma etching tools verified by TSMC

DigiTimes report (LINK) that the Chinese OEM Advanced Micro-Fabrication Equipment (AMEC) announced recently its in-house developed 5nm plasma etching tools have been verified by Taiwan Semiconductor Manufacturing Company (TSMC). AMEC is already among TSMC's equipment suppliers for the foundry's 28nm, 10nm and 7nm processes.

Earlier in 2018 AMEC Introduced the Primo Nanova® System, which is the Company's first ICP etch Product for Chipmakers' most advanced memory and logic (LINK). Besides ICP AMEC has products based on CCP etch and platforms for TSV Etch (LINK).

 AMEC Introduced the Primo Nanova® System (AMEC)

Advanced Micro-Fabrication Equipment Inc. (AMEC)
AMEC is China's leading provider of advanced process technology to global manufacturers of semiconductors and solid-state lighting (SSL) products. Headquartered in Shanghai, the company is an entrenched supplier of dielectric and TSV Etch tools, helping chipmakers build devices at process nodes as low as 7nm. To date, nearly 800 AMEC process units have been positioned at 40 leading-edge semiconductor fabs across Asia. The company is also well established in Europe with AMEC MEMS tools running in production at major IDMs. In addition, with its MOCVD system, the company helps SSL manufacturers build today's most advanced LED products. To learn more about AMEC, please visit www.amec-inc.com.

Advanced Energy sales for Plasma ALD sources show growth in Logic and 3DNAND

Advanced energy recently reported their 1Q/2017 showing off a Q1 Revenue increased 44.9% y/y and 10.3% q/q to $149.4 million (LINK)

In the following eraingscall (Yahoo Finance) Yuval Wasserman, Advanced Energy Industries, Inc. - CEO, President and Director, had this to say about their recent design wins for Plasma ALD remote plasma sources and emerging plasma sources for etch accelerated by 3DNAND and Logic 10 nm ramp demand.

 

A key driver of our success comes from continuously investing in R&D and winning new designs in this fast-growing areas. This quarter, we saw a broad set of design wins in semiconductor applications for customers in Asia and the U.S. Advanced 3D memory and logic devices drove the majority of the wins. We also won designs in new plasma-enhanced atomic layer deposition applications with our new remote plasma source technology, which is being adopted for radicals-based processes.

Finally, this quarter we had an important milestone with our solid state RF matching product, which has progressed from evaluation to pilot and mass production for advanced etch applications. Solid state RF matches enable the performance of emerging short plasma processes with high speed, reliable and dynamic control.

Looking ahead, solid state drives and mobile headsets continue to generate demand, leading to 3D NAND acceleration and additional foundry and logic investment in the ramp of 10 nanometers and the development of 7 and 5 nanometers. As the semiconductor capital equipment industry strives to keep pace, some OEMs are reaching maximum for capacity and tailoring their material planning accordingly. This leads us to expect our second quarter semiconductor revenues to remain at or above the first quarter's level.

Advanced Energy are offer in a ICP source (Litmas RPS) as well as a CCP (QUANTA) sources that are used in ALD and ALE, besides other classical semicondcutor processing like PECVD, PVD and RIE.

The Advanced Energy Litmas RPS Source (ICP type) uses in thin film deposition (LINK)

 

A spatial ALD oxide passivation module in an all-spatial etch-passivation cluster concept!

Prof. Fred Roozeboom and co-workers F. van den Bruele, Y. Creyghton, P. Poodt, and Prof. W.M.M. Kessels (all from Eindhoven University of Technology and TNO, as driving forces behind Spatial ALD and ALE technology), have just published a fantastic open access publication in ECS Journal of Solid State Science and Technology. Just taste the title of this blog text for a moment and then continue reading or down load the article - it´s free, it´s OPEN ACCESS.

Cyclic etch /passivation-deposition as an all-spatial concept towards high-rate room temperature Atomic Layer Etching [OPEN ACCESS]
F. Roozeboom, F. van den Bruele, Y. Creyghton, P. Poodt, and W.M.M. Kessels
ECS Journal of Solid State Science and Technology, 4 (6) pp. N5067-N5076 (2015). doi:10.1149/2.0111506jss

Conventional (3D) etching in silicon is often based on the ‘Bosch’ plasma etch with alternating half-cycles of a directional Si-etch and a fluorocarbon polymer passivation. Also shallow feature etching is often based on cycled processing. Likewise, ALD is time-multiplexed, with the extra benefit of half-reactions being self-limiting, thus enabling layer-by-layer growth in a cyclic process. To speed up growth rate, spatial ALD has been successfully commercialized for large-scale and high-rate deposition at atmospheric pressure. We conceived a similar spatially-divided etch concept for (high-rate) Atomic Layer Etching (ALEt). The process is converted from time-divided into spatially-divided by inserting inert gas-bearing ‘curtains’ that confine the reactive gases to individual injection slots in a gas injector head. By reciprocating substrates back and forth under such head one can realize the alternate etching/passivation-deposition cycles at optimized local pressures, without idle times needed for switching pressure or purging. Another improvement toward an all-spatial approach is the use of ALD-based oxide (Al₂O₃, SiO₂, etc.) as passivation during, or gap-fill after etching. This approach, called spatial ALD-enabled RIE, has industrial potential in cost-effective back-end-of-line and front-end-of-line processing, especially in patterning structures requiring minimum interface, line edge and fin sidewall roughness (i.e., atomic-scale fidelity with selective removal of atoms and retention of sharp corners). 

The publication starts with a History of 3D etching and a description of how and why plasma etching is a key enabling technology and then it gets down to business to introduce the concept behind layer-by layer growth (ALD) or etch (ALE) and more importantly the concept behind spatial layer-by-layer processing. Then via the cyclic Bosch process, and Spatial RIE with Spatial passivation we land at the Grand Finale - Spatial RIE process mode with Spatial ALD passivation!  Or even more beautifully formulated by Prof. Roozeboom himself a spatial ALD oxide passivation module in an all-spatial etch-passivation cluster concept!

Layer-by layer-processing

Schematic of conventional CVD and plasma etching and their layer-by-layer counterparts, ALD and ALEt. ALEt is cycled between modification by chemisorption of a reactant at the surface and, subsequent volatilization of, ideally, one (sub)monolayer by irradiation with an energetic beam or reaction with a co-reactant. For simplicity reasons the etch processes (bottom pictures) are cartooned in plasma-assisted mode, and the deposition processes (top pictures) in thermal mode. The latter two could be plasma-assisted as well. In the conventional processes (CVD and Plasma etch) the chemical reactants are supplied simultaneously and non-interrupted, and in the layer-by-layer processes (ALD and ALEt) they are alternated. (picture used with permission)

Spatial ALD

 

Schematic representation of spatial ALD: a wafer moves horizontally back and forth under spatially divided and confined reaction zones. Arrows pointing upwards indicate exhaust lines. Notice the difference in height of the gas bearing compartments (typically ∼20 to 100 μm) and the deposition compartments (typical height a few mm, and lengths and widths of order ∼1-10 mm).(picture used with permission)

Convential Bosch etching by cyclic surface passivation half-cycles

 

 

Conventional Bosch etch process scheme for etching silicon with a pre-patterned hard mask atop, using alternating etch and passivation half-cycles. (picture used with permission)

Spatial RIE process mode with C₄F₈ passivation

Schematic of spatial RIE process mode with C₄F₈ passivation of a wafer that reciprocates under spatially divided reaction zones. Arrows pointing upwards indicate exhaust lines. Notice the difference in height of the gas bearing compartments (typically ∼20 to 100 μm) and the plasma compartments (typical height ∼10 mm, and length of several 10 mm's and width of order ∼1 mm). The compartments are connected through a gas bearing envelope. Not to scale; wafers will pass the entire zones before shuttling back.  (picture used with permission)

Spatial ALD oxide passivation module in an all-spatial etch-passivation cluster concept

 

Schematic of alternative all-spatial RIE process mode with spatial ALD oxide passivation (e.g., SiO₂, Al₂O₃, ..). ‘Si’ denotes a Si-precursor, TMA is trimethyl aluminum. Note, that for deep etching and for shallow (‘layer-by-layer’) etching the wafer exposure times in the respective zones will differ, which will imply different residence times, or different numbers of unit cells in the two main compartments.  (picture used with permission)

At the end after showing a number of case studies, Prof. Roozeboom et al summarizes - and we all believers will agree on these conclusions - namely that:

• The potential of ALD-assisted nanomanufacturing technologies like Atomic Layer Etching (ALEt) concepts derived from etch-purge-passivation/deposition-purge subroutines in (D)RIE and ALD is now clearly being recognized and promoted.
• The ongoing scaling of Moore's Law will soon require the implemention of these complementary technologies to meet the 10-nm challenges in surface and sidewall passivation of resist and feature patterns that is required to minimize interface, line edge and fin wall roughness.
• For cost reasons and flexibility in local pressure, i.e. (an)isotropy control, in the spatial etch and purge compartments one can envisage a gradual shift to the adoption of ALD-enabled RIE (we abbreviate it as ALDeRIE) in the spatial domain as well. 
• Obviously, the spatially divided version is not commercially available yet and not straightforward, but – once realized for dedicated materials and topographies – it will certainly lead to far improved price-performance ratios in Atomic Layer Etching.  

 

Fred Roozeboom appointed as ECS Fellow, The Electrochemical Society appointed Prof. dr. Fred Roozeboom as Fellow of the Electrochemical Society  for his Scientific contributions to Solid-State Science & Technology and its impact on the society. He has been awarded especially because of his contributions on the areas of rapid thermal processing, passive 3D and heterogeneous integration, reactive ion etching and atomic layer deposition (ALD). He received his award at the Plenary Session of the 226th ECS meeting. October 5, 2014, Cancun, Mexico.