The Coventor's SEMulator3D software platform

Semiconductor process engineers would love to develop successful process recipes without the guesswork of repeated wafer testing: Process modeling is a powerful technique to predict process results quickly and locate potential process issues without wafer-based testing. These process-modeling capabilities are fully-integrated in the Coventor's (a Lam Research Company) SEMulator3D software platform. Once a process model is built in SEMulator3D, any changes to a proposed integration scheme or device design (such as layout or hardmask thickness changes) can be easily visualized and quantified, without the time and expense of wafer testing. 

The process of building a 3D device using a process model (instead of physical wafers) is called “virtual fabrication”. Using virtual fabrication in conjunction with calibration cycles, process engineers and integration engineers can easily develop a process and integration model. The accuracy and predictability of any model is dependent on the quality of the input data, but SEMulator3D is able to model a wide range of physical process behavior with great accuracy and can solve highly-advanced process problems.

Source: An Introduction to Semiconductor Process Modeling: Process Specification and Rule Verification (LINK)

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By Abhishekkumar Thakur

LAM Research MMP Technology Etch for Advanced Memory

"MMP technology enables atomic layer etching (ALE), providing extendibility and repeatability with atomic-scale fidelity"

Atomic-scale fidelity - Can you put it more beautiful?

LAM Research has developed a mixed-mode pulsing (MMP) technology that enables critical conductor etch for advanced memory like 3D NAND and DRAM. The technology is available for their Kiyo Product F Series chambers. 

LAM Research reports: The Kiyo F Series delivers high productivity while minimizing variability for advanced memory applications. Lam's MMP technology provides advanced profile and CD control for vertical profiles with good selectivity and tuning controls for consistent etch depths. These capabilities enable higher trim rate for 3D NAND staircase etch along with excellent repeatability, which is needed for manufacturing environments. Symmetric chamber design and radial tuning provide best-in-class uniformity, which is essential for minimizing CD variability. 

In addition, for new generations of advanced memory as well as logic devices, MMP technology enables atomic layer etching (ALE), providing extendibility and repeatability with atomic-scale fidelity.

By stacking memory cells vertically, NAND flash manufacturers can pack more storage capacity onto a smaller device, ease lithography requirements, and reduce manufacturing cost per bit. For multilayer 3D NAND structures, critical conductor etch processes include staircase etch and high aspect ratio (HAR) mask open for vertical channels. This mask open is crucial since it defines the CD and CD uniformity for subsequent etching of the vertical transistor channels. For staircase etch, equal-width "steps" are created at the edge of each dielectric-film pair throughout the 3D stack to form a staircase-shaped structure. Because of extensive repetition of these steps during device processing, etching at high throughput with stringent process control is vital. CD variability must be tightly managed since wordline contacts may otherwise miss landing on a step that is too narrow or uneven. 

Just for visualisation for the reader of this blog, here the advance HAR etch that is required and mastered by LAM MMP Technology described in a reverse engineering cross section by Chipworks from a SAMSUNG V-NAND Flash array (published here)

LAM Research further reports with respect to DRAM : For advanced DRAM devices, depth control is a key parameter, particularly for HAR front-end-of-line silicon etch applications. Concerns include aspect ratio loading, where etch rates vary because of differences in feature dimensions, and depth loading, where different etch depths may occur due to pattern density variations.

More detailed information on mixed-mode plasma pulsing (MMP) can be found in this patent by LAM Research:

Mixed mode pulsing etching in plasma processing systems US 20130168354 A1

A spatial ALD oxide passivation module in an all-spatial etch-passivation cluster concept!

Prof. Fred Roozeboom and co-workers F. van den Bruele, Y. Creyghton, P. Poodt, and Prof. W.M.M. Kessels (all from Eindhoven University of Technology and TNO, as driving forces behind Spatial ALD and ALE technology), have just published a fantastic open access publication in ECS Journal of Solid State Science and Technology. Just taste the title of this blog text for a moment and then continue reading or down load the article - it´s free, it´s OPEN ACCESS.

Cyclic etch /passivation-deposition as an all-spatial concept towards high-rate room temperature Atomic Layer Etching [OPEN ACCESS]
F. Roozeboom, F. van den Bruele, Y. Creyghton, P. Poodt, and W.M.M. Kessels
ECS Journal of Solid State Science and Technology, 4 (6) pp. N5067-N5076 (2015). doi:10.1149/2.0111506jss

Conventional (3D) etching in silicon is often based on the ‘Bosch’ plasma etch with alternating half-cycles of a directional Si-etch and a fluorocarbon polymer passivation. Also shallow feature etching is often based on cycled processing. Likewise, ALD is time-multiplexed, with the extra benefit of half-reactions being self-limiting, thus enabling layer-by-layer growth in a cyclic process. To speed up growth rate, spatial ALD has been successfully commercialized for large-scale and high-rate deposition at atmospheric pressure. We conceived a similar spatially-divided etch concept for (high-rate) Atomic Layer Etching (ALEt). The process is converted from time-divided into spatially-divided by inserting inert gas-bearing ‘curtains’ that confine the reactive gases to individual injection slots in a gas injector head. By reciprocating substrates back and forth under such head one can realize the alternate etching/passivation-deposition cycles at optimized local pressures, without idle times needed for switching pressure or purging. Another improvement toward an all-spatial approach is the use of ALD-based oxide (Al₂O₃, SiO₂, etc.) as passivation during, or gap-fill after etching. This approach, called spatial ALD-enabled RIE, has industrial potential in cost-effective back-end-of-line and front-end-of-line processing, especially in patterning structures requiring minimum interface, line edge and fin sidewall roughness (i.e., atomic-scale fidelity with selective removal of atoms and retention of sharp corners). 

The publication starts with a History of 3D etching and a description of how and why plasma etching is a key enabling technology and then it gets down to business to introduce the concept behind layer-by layer growth (ALD) or etch (ALE) and more importantly the concept behind spatial layer-by-layer processing. Then via the cyclic Bosch process, and Spatial RIE with Spatial passivation we land at the Grand Finale - Spatial RIE process mode with Spatial ALD passivation!  Or even more beautifully formulated by Prof. Roozeboom himself a spatial ALD oxide passivation module in an all-spatial etch-passivation cluster concept!

Layer-by layer-processing

Schematic of conventional CVD and plasma etching and their layer-by-layer counterparts, ALD and ALEt. ALEt is cycled between modification by chemisorption of a reactant at the surface and, subsequent volatilization of, ideally, one (sub)monolayer by irradiation with an energetic beam or reaction with a co-reactant. For simplicity reasons the etch processes (bottom pictures) are cartooned in plasma-assisted mode, and the deposition processes (top pictures) in thermal mode. The latter two could be plasma-assisted as well. In the conventional processes (CVD and Plasma etch) the chemical reactants are supplied simultaneously and non-interrupted, and in the layer-by-layer processes (ALD and ALEt) they are alternated. (picture used with permission)

Spatial ALD

 

Schematic representation of spatial ALD: a wafer moves horizontally back and forth under spatially divided and confined reaction zones. Arrows pointing upwards indicate exhaust lines. Notice the difference in height of the gas bearing compartments (typically ∼20 to 100 μm) and the deposition compartments (typical height a few mm, and lengths and widths of order ∼1-10 mm).(picture used with permission)

Convential Bosch etching by cyclic surface passivation half-cycles

 

 

Conventional Bosch etch process scheme for etching silicon with a pre-patterned hard mask atop, using alternating etch and passivation half-cycles. (picture used with permission)

Spatial RIE process mode with C₄F₈ passivation

Schematic of spatial RIE process mode with C₄F₈ passivation of a wafer that reciprocates under spatially divided reaction zones. Arrows pointing upwards indicate exhaust lines. Notice the difference in height of the gas bearing compartments (typically ∼20 to 100 μm) and the plasma compartments (typical height ∼10 mm, and length of several 10 mm's and width of order ∼1 mm). The compartments are connected through a gas bearing envelope. Not to scale; wafers will pass the entire zones before shuttling back.  (picture used with permission)

Spatial ALD oxide passivation module in an all-spatial etch-passivation cluster concept

 

Schematic of alternative all-spatial RIE process mode with spatial ALD oxide passivation (e.g., SiO₂, Al₂O₃, ..). ‘Si’ denotes a Si-precursor, TMA is trimethyl aluminum. Note, that for deep etching and for shallow (‘layer-by-layer’) etching the wafer exposure times in the respective zones will differ, which will imply different residence times, or different numbers of unit cells in the two main compartments.  (picture used with permission)

At the end after showing a number of case studies, Prof. Roozeboom et al summarizes - and we all believers will agree on these conclusions - namely that:

• The potential of ALD-assisted nanomanufacturing technologies like Atomic Layer Etching (ALEt) concepts derived from etch-purge-passivation/deposition-purge subroutines in (D)RIE and ALD is now clearly being recognized and promoted.
• The ongoing scaling of Moore's Law will soon require the implemention of these complementary technologies to meet the 10-nm challenges in surface and sidewall passivation of resist and feature patterns that is required to minimize interface, line edge and fin wall roughness.
• For cost reasons and flexibility in local pressure, i.e. (an)isotropy control, in the spatial etch and purge compartments one can envisage a gradual shift to the adoption of ALD-enabled RIE (we abbreviate it as ALDeRIE) in the spatial domain as well. 
• Obviously, the spatially divided version is not commercially available yet and not straightforward, but – once realized for dedicated materials and topographies – it will certainly lead to far improved price-performance ratios in Atomic Layer Etching.  

 

Fred Roozeboom appointed as ECS Fellow, The Electrochemical Society appointed Prof. dr. Fred Roozeboom as Fellow of the Electrochemical Society  for his Scientific contributions to Solid-State Science & Technology and its impact on the society. He has been awarded especially because of his contributions on the areas of rapid thermal processing, passive 3D and heterogeneous integration, reactive ion etching and atomic layer deposition (ALD). He received his award at the Plenary Session of the 226th ECS meeting. October 5, 2014, Cancun, Mexico.