This innovation boasts the following:
- Logic transistor density of 100.8 mega transistors per mm2, increasing 10nm density 2.7X over the 14nm node
- Utilizes third generation FinFET technology
- Minimum gate pitch of Intel’s 10 nm process shrinks from 70 nm to 54 nm
- Minimum metal pitch shrinks from 52 nm to 36 nm
- Deepest scaled pitches of current 10 nm and upcoming 7 nm technologies
- First Co metallization and Ru usage in BEOL
- New self-aligned patterning schemes at contact and BEOL
- Hyperscaling via 6.2-Track high density library
- Contact on active gate (COAG) cell-level usage
By Abhishekkumar Thakur
Let's see when the 7-10 nm chips start to cough !
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