Thermal Atomic Layer Etching of copper by University of Illinois at Urbana-Champaign

Copper is a wonder metal used in moth integrated circuits but is very difficult to etch by a dry process. That is why copper is typically removed by wet chemistry or rather brutal CMP processes. So now quite fantastic news for all BEOL people who have had all kinds of problem etching copper or for those FEOL people who absolutely do not like copper - now there is a way to thermally etch copper as presented in the publication below by scientists form University of Illinois at Urbana-Champaign in the United States.

Thank you Prof. Pedersen for sharing this article on Twitter using the hashtag #ALEtch (#ALDep for ALD).

According to the abstract, the published ALE method of copper relies on:

• a cyclic exposure to an oxidant and hexafluoroacetylacetone (Hhfac) at 275°C
• exposure of a copper surface to molecular oxygen, O₂, a weak oxidant, forms a ∼0.3 nm thick layer of Cu₂O, which is removed in a subsequent step by exposure to Hhfac. 
• the process has high selectivity and does not attack dielectrics such as SiO₂ or SiN_x 
• the surface reactions are self-limiting
• the roughness of the copper surface increases slowly over successive etch cycles 

Promising is also that rhermochemical and bulk etching data indicate that the approach should also work for other metals.

Thermal Atomic Layer Etching of Copper by Sequential Steps Involving Oxidation and Exposure to Hexafluoroacetylacetone

doi: 10.1149/2.0211809jss ECS J. Solid State Sci. Technol. 2018 volume 7, issue 9, P491-P495

http://jss.ecsdl.org/content/7/9/P491.abstract?etoc

Screendump from ECS Journal of Solid State Science and Technology (http://jss.ecsdl.org/content/7/9/P491.abstract?etoc 2018.12.09)

Overview of Applied Materials cobalt metallization for local interconnects

For those of you interested in the details behind the Applied Materials integrated cobalt metallization process Jonathan Bakke has written two informative blogs about it in Semiconductror Engineering:

(1) The Role Of Cobalt In Enabling AI - For continued performance, power, area and cost improvements, materials need to be engineered at the atomic scale.

(2) The Materials Side Of AI - What comes after tungsten fill for contacts and copper for the lowest-level interconnects?

The integrated cobalt solution using Applied Materials platforms (Applied Materials).

Jonathan Bakke is global product manager for Contact and Middle of Line Products in the Metal Deposition Products Business Unit at Applied Materials. He details the process flow and tool sets from Applied Materials involved in the complete BEOL Co metallization flow:

• PVD titanium and ALD titanium nitride for the silicide and barrier layers
• PVD cobalt serves as an anchor layer to ensure good cobalt adhesion to the bottom of the feature
• CVD cobalt is then used to deposit a conformal film to bulk fill the feature
• Anneal purifies and reflows the cobalt, removes the CVD seam, and merges crystal grains to form a more crystalline, lower resistance material
• PVD cobalt for a thick overburden film
• CMP removes overburden materials to create a smooth planar surface
• E-beam technology monitors the process and detects voids

Atomic Layer Deposition of platinum thin films - current and future applications

Strem Chemicals is a well-established (since 1964) supplier of ALD and CVD precursors for both R&D and industrial applications. Many of their compounds are also available in electronic grade suitable for semiconductor applications. The full range of their ALD and CVD precursors can be found in their famous catalog available as a hard copy or on line [LINK]. Amongst the wide range of precursors, the platinum precursors and especially the (trimethyl)methyl-cyclopentadienylplatinum(IV) - MeCpPtMe₃ has proven popular for a wide range of ALD and CVD applications.

Platinum and platinum-rich alloys are naturally occurring and have been known for a long time since it is often found as native platinum. It occurs naturally in the sands of rivers in South America and it was first used by pre-Columbian natives to produce artifacts. Later in 16th century the Spaniards named the metal "platina," or little silver, when they first encountered it in Colombia.  They regarded platinum as an unwanted impurity in the silver they were mining and it was not until 1748 that platinum was properly reported by Antonio de Ulloa y de la Torre-Giral, a Spanish general of the navy, explorer, scientist, author, astronomer and colonial administrator.

Since the platinum has become known and used because of the outstanding catalytic properties, which it has in common with the other of the six platinum group metals (PGM) – iridium, osmium, palladium, platinum, rhodium, and ruthenium.  In addition, platinum's wear and tarnish resistance characteristics are well suited for making fine jewelry.  Other distinctive properties include:

• high resistance to chemical attack
• excellent high-temperature characteristics
• stable electrical properties.
  

Because of all these extraordinary properties the PGMs have been exploited for a wide range of industrial applications.   Platinum, platinum alloys, and iridium are used as crucible materials for the growth of single crystals, especially oxides.  The chemical industry uses a significant amount of either platinum or a platinum-rhodium alloy catalyst to catalyze the partial oxidation of ammonia to yield nitric oxide, which is the raw material for fertilizers, explosives, and nitric acid.   

In recent years, a number of PGMs have become important as catalysts in synthetic organic chemistry.  Platinum supported catalysts are used in the refining of crude oil, reforming, and other processes used in the production of high-octane gasoline and aromatic compounds for the petrochemical industry.  Since 1979, the automotive industry has emerged as the number one consumer of PGMs.  Palladium, platinum, and rhodium have been used as oxidation catalyst in catalytic converters to treat automobile exhaust emissions.  A wide range of PGM alloy compositions are used in low-voltage and low-energy contacts, thick- and thin-film circuits, thermocouples and furnace components, and electrodes.

It was not until the early 2000 that the platinum and the other PGMs became available as a ALD processes and here below is a summary of the most important fundamental discoveries of platinum ALD.

Thermal ALD of high quality platinum films

It all started with thermal ALD of platinum and ruthenium in Helsinki Finland at the famous Laboratory for Inorganic Chemistry headed by Prof. Markku Leskelä and Prof. Mikko Ritala. Here it was found that high quality platinum films can be grown by thermal ALD from MeCpPtMe₃. According to the first publications by Titta Aaltonen (summarized in her PhD Thesis University of Helsinki: LINK) the films had strong (111) orientation even down to the lowest growth temperatures. Except for discovering the secrets of thermal ALD of noble metals (Ru, Ir Pt, Pd) Titta Aaltonen made groundbreaking studies of their ALD  growth mechanism with O₂ as the co-reactant. At first it may seem strange that O₂, or in her case also laboratory air or pressured air, could be used to grow high quality noble metal films. Titta Aaltonen found that adsorbed oxygen atoms react with the ligands of the noble metal precursor during the metal precursor pulse. Unreacted ligand species that remained on the surface after the metal precursor pulse react with oxygen during the following oxygen pulse. The main reaction by-products detected during the both reaction steps were water and carbon dioxide. For detailed studies of the ruthenium process using RuCp₂ it has been concluded that active oxygen that dissolves in the upper most monolayers of the growing noble metal film may be behind the nucleation and growth mechanism of the next “ALD monolayer”.

The growth rates of the platinum films grown at 300 °C from MeCpPtMe₃ was reported at about 0.5 Å/cycle both when air and pure oxygen were used as oxygen sources and a 50-nm film grown at 300 °C had a resistivity of 13 μΩcm, which is close to bulk value for platinum. It was also found that the difference between air and O2 co-reactant was in how the films adhered to the substrate. The films grown with air as the oxygen source did not pass the famous scotch tape test, while the films grown with pure oxygen passed the tape test.

Besides having such a beautiful ALD mechanism with such a simple co-reactant as air or O₂, one additional very big advantage with the MeCpPtMe₃ precursor is that can be vaporized at room temperature, just slightly below its melting point of 30 °C since the vapor pressure of MeCpPtMe₃ at room temperature is high enough for delivery into an ALD process chamber. If you need a bit more precursor flow for larger batch type reactors or applications with relying on high surface area you can melt the precursor in a standard stainless steel ampule or bubbler with carrier gas dip tube to enhance the flow further. 

A hook up of  MeCpPtMe₃ precursor  supplied in a Strem Swagelock ALD/CVD cylinder via a standard Swagelock ALD-valve as close as possible to a thermal horizontal low pressure ALD/CVD reactor (at Fraunhofer IKTS, Dresden, Germany, LINK) to save valuable platinum precursor (LINK) In order to enhance the precursor flow the installation can be wrapped with heater tape and heated to 30-50 °C.

Plasma ALD of platinum films

Some years later, Harm Knoops (now TU Eindhoven/Oxford Instruments) and co-workers published extensive results in a benchmarking study in 2009 [LINK] using MeCpPtMe₃ precursor in a plasma ALD reactor with a remote ICP O₂ Plasma. Here they proved that by the plasma enhanced ALD process (PEALD), the growth temperature could be reduced considerably to as low as 100 °C for both platinum metal and platinum oxide film growth and it was possible to switch between the two growth modes by adding a H₂ step to grow metallic films. More recently, the same group reported platinum ALD at room temperature on polymer, textile, and paper substrates [LINK]. By tuning the dosing of MeCpPtMe₃, O₂ plasma exposure, and H₂ gas or H₂ plasma exposure high-quality platinum films with a resistivity of 18–24 μΩ cm were obtained.

Growth of platinum nanoparticles by ALD

Most recently Prof. Ruud van Ommen (TU Delft) published their detailed study [LINK] on how to control and grow platinum nanoparticles by ALD, again using the MeCpPtMe3 precursor.

They showed that the nanoparticle aggregation takes place during the oxygen half-reaction and that the mobility of the nanoparticles exhibits a size- and temperature-dependent scaling and that ALD-like precision over the nanoparticle size requires low deposition temperatures (< 100 °C).

Industrial applications for platinum ALD

Since early 2000 platinum ALD has been considered in parallel to ruthenium and evaluated multiple times by academia and industry for the use in a number of microelectronic applications including:

• Electrodes for DRAM high-k capacitors
• Transistor Source/Drain contacts with nickel Ni(Pt)Si
• DRAM buried Word Lines and Bit Lines
• Local interconnects as Cu seed layer or complete fill replacing tungsten

The semiconductor industry is very sensitive for raw material pricing and therefore introduction of platinum so far has mainly been using PVD in the case of Ni(Pt)Si source drain contact and for the other applications mentioned above there has been no reports of high volume manufacturing. Meanwhile, ruthenium on the other hand had have some success for hard disk reader heads and is now considered for local interconnects for technologies at 5 nm or below.

One of the biggest industrial applications for the MeCpPtMe3 precursor today is for E-beam direct write repair of photo lithographic masks for both Immersion and EUV lithography and making direct chip level contacts for electrical characterization in FIB-SEM.  

Current research and development on using platinum ALD or CVD as deposition method focuses on:

• Nanobatteries using platinum contacts and electrodes
• Supercapacitors using platinum electrodes
• Nanoparticle catalysis
• Core shell nanoparticles (nanoparticles covered by an ultra-thin platinum layer)
• As contacts to III/V nanowire and 2D materials devices
• Electrodes and contacts in printed flexible electronics
• 3D Nanoprinting via laser-assisted electron beam induced deposition

The main issue to overcome for any successful industrial scale up of platinum is to minimize the use of bulk platinum and use ultra-thin layers and if bulk material is need use either substrates with a very large surface or coated low cost particles. Eventually, for all applications, platinum being a noble metal all of the by-products of precursor or coated parts has to be recaptured and recycled. 

In the case of automotive catalyst support such PGM recycling plants are operational since long time (e.g. operated by BASF and Umicore). For the ruthenium introduction in the semiconductor device manufacturing, several companies have reported development of recapture and recycling methods (e.g. Praxair, Tokyo Electron and Tanaka) and we can assume that these can also be adapted for platinum precursor recapture and recycling. Finally, to put things in perspective, the USGS reported that about 110,000 kilograms of platinum, palladium, and rhodium was recovered globally from new and old scrap in 2017 and they estimate the world resources of PGMs to a total more than 100 million kilograms. The largest reserves are in the Bushveld Complex in South Africa.

References

ALD of platinum from MeCpPtMe₃ and Air and the ALD nobel metal / oxygen reaction mechanism: T. Aaltonen, A. Rahtu, M. Ritala, and M. Leskelä, Reaction Mechanism Studies on Atomic Layer Deposition of Ruthenium and Platinum, Electrochem. Solid-State Lett., 6 (2003) C130–C133. [LINK]

ALD of platinum from MeCpPtMe₃ and O₂ : T. Aaltonen, M. Ritala, Y.-L. Tung, Y. Chi, K. Arstila, K. Meinander, and M. Leskelä, Atomic Layer Deposition of Noble Metals: Exploration of the Low Limit of the Deposition Temperature, J. Mater. Res., 19 (2004) 3353–3358. [LINK]

PEALD and thermal ALD of platinum films from MeCpPtMe₃ :  H. C. M. Knoopsa, A. J. M. Mackus, M. E. Dondersa, M. C. M. van de Sanden, P. H. L. Notten, and W. M. M. Kessels.

PEALD of platinum at room temperature : A. J. M. Mackus, D. Garcia-Alonso, H. C. M. Knoops, A. A. Bol, and W. M. M. Kessels, Room-Temperature Atomic Layer Deposition of Platinum, Chem. Mater., 2013, 25 (9), pp 1769–1774 [LINK]

Platinum nanoparticle ALD growth : F. Grillo, H. Van Bui, J. A. Moulijn, M. T. Kreutzer, and J. R. van Ommen, Understanding and Controlling the Aggregative Growth of Platinum Nanoparticles in Atomic Layer Deposition: An Avenue to Size Selection, J. Phys. Chem. Lett., 2017, 8 (5), pp 975–983 [LINK]

Facts about PGMs : Platinum-Group Metals Statistics and Information (Platinum, Palladium, Rhodium, Ruthenium, Osmium, and Iridium), U.S. Department of the Interior, U.S. Geological Survey [LINK]

MeCpPtMe₃ product information and ordering from Strem Chemicals (Item #: 78-1350):

 

Product Description: (Trimethyl)methylcyclopentadienylplatinum(IV), 99%

CAS #: 94442-22-5

URL: www.strem.com/catalog/v/78-1350/

Safety Data Sheet: [LINK]

Thermal ALD of aluminum metal at low temperature

Aluminum metal is important in semiconductor devices and as a metal itself in metallization and as an alloy in e.g. TiAl metal gates or TiAlN electrodes. Prof. Winter and his team at Wayne State have previously published new paths to thermal ALD of titanium, here they published their recent achievement for thermal ALD of aluminum!

Atomic Layer Deposition of Aluminum Metal Films Using a Thermally Stable Aluminum Hydride Reducing Agent

Kyle J Blakeney and Charles H. Winter

Chem. Mater., Just Accepted Manuscript

LINK: https://pubs.acs.org/doi/abs/10.1021/acs.chemmater.8b00445 

The thermal atomic layer deposition of aluminum metal films at temperatures as low as 100 °C is described using AlCl₃ and a new aluminum dihydride complex that is supported by a bulky amido-amine ligand. A growth rate of about 3.5 Å/cycle was observed within a 120-160 °C ALD window and self-limiting growth was established for both precursors. Resistivities as low as 3.03 Ω·cm were obtained for the aluminum metal films. Root mean square surface roughnesses were 19-23% of the film thicknesses, as determined by atomic force microscopy. Films grown on TiN substrates were crystalline by X-ray diffraction. X-ray photoelectron spectroscopy of films grown at 100 and 140 °C showed Al (> 94 at%) with C and Cl impurities below the detection limit (< 1 and 0.5 at%, respectively). Accordingly, this process affords high purity, low resistivity aluminum metal films.

ALD of Metals Week on Twitter

In between all those very important policy tweets for the world as we knew it there seems to be Metal ALD theme this week on Twitter. Many new interesting publications on both the practical and theoretical paths to successful ALD of Metals to solve those BEOL issues at 7 nm.

Copper #AtomicLayerDeposition #moleculardynamic simulation using #reaxff#compchem #ALDep pic.twitter.com/NCH7qpxSGe

— Scienomics (@Scienomics) February 6, 2017

Our suggestion for classifying metal #ALDep processes according to mechanism in J. Chem. Phys. special issue https://t.co/7K3sdHVxNd pic.twitter.com/BtpJPsIgCt

— Simon Elliott (@Simon_D_Elliott) February 7, 2017

Efficient Process for Direct #ALDep of Metallic Cu Thin Films Based on an Organic Reductant - Chemistry of Materials https://t.co/5ynEmY6mKP

— BALD Engineering AB (@jv3sund) February 6, 2017

BEOL Issues At 10nm And 7nm https://t.co/3KQlu50G7B#10nm #7nm #BEOL #EUV pic.twitter.com/894hBj3m62

— SemiEngineering (@SemiEngineering) January 17, 2017

Managing Parasitics For Transistor Performance- #Capacitances are critical factors @ advanced nodes https://t.co/3x74SyoSLo#transistors pic.twitter.com/ICQHHpxTtH

— SemiEngineering (@SemiEngineering) January 30, 2017

[UPDTAE] Lam Research launch New ALTUS(R) Max E Series for Low-fluorine, Low-stress, and Low-resistivity ALD Tungsten

[UPDATE] :  Lam Blog - Innovative Tungsten ALD Process Provides Pathway to New Memory Chip Production : http://blog.lamresearch.com/innovative-tungsten-ald-process-provides-pathway-to-new-memory-chip-production/

 ALTUS Max E Series 4 station chambers (Picture from Lam Blog)

FREMONT, CA -- (Marketwired) -- 08/09/16 -- Lam Research Corp. (NASDAQ: LRCX), an advanced manufacturer of semiconductor equipment, today introduced an atomic layer deposition (ALD) process for depositing low-fluorine-content tungsten films, the latest addition to its industry-leading ALTUS® family of products. With the industry's first low-fluorine tungsten (LFW) ALD process, the ALTUS Max E Series addresses memory chipmakers' key challenges and enables the continued scaling of 3D NAND and DRAM devices. Building on Lam's market-leading product portfolio for memory applications, the new system is gaining market traction worldwide, winning production positions at leading 3D NAND and DRAM manufacturers and placement at multiple R&D sites.

ALTUS Max E Series 4 station chambers shuffling wafers (Picture from Lamresearch.com)

"Consumer demand for ever more powerful devices is driving the need for high-capacity, high-performance storage, and deposition and etch are key process technology enablers of advanced memory chips," said Tim Archer, Lam's chief operating officer. "With the addition of the ALTUS Max E Series, we are expanding our memory portfolio and enabling our customers to capitalize on this next wave of industry drivers. Over the past twelve months, as the 3D NAND inflection has accelerated, we have doubled our shipments for these applications, leading to the largest deposition and etch installed base in our 3D NAND served markets."

As manufacturers increase the number of memory cell layers for 3D NAND, two issues have become apparent for tungsten deposition in the word line fill application. First, fluorine diffusion from the tungsten film into the dielectrics can cause physical defects. Second, higher cumulative stress in devices with more than 48 pairs has resulted in excessive bowing. The resulting defects and stress can cause yield loss, as well as degraded electrical performance and device reliability. Because of these issues, tungsten films for advanced 3D NAND devices must have significantly reduced fluorine and intrinsic stress. Further, as critical dimensions shrink, resistance scaling becomes more challenging for the DRAM buried word line, as well as for metal gate/metal contact applications in logic devices.

"As memory chip manufacturers move to smaller nodes, the features that need to be filled are increasingly narrow and have higher aspect ratios," said Sesha Varadarajan, group vice president, Deposition Product Group. "Lam's new LFW ALD solution uses a controlled surface reaction to tune stress and fluorine levels and to lower resistance, all while delivering the required tungsten fill performance and productivity. When compared to chemical vapor deposition tungsten, the ALTUS Max E Series lowers fluorine content by up to 100x, lowers stress by up to 10x, and reduces resistivity by over 30%, solving some of our customers' most critical scaling and integration challenges."

The ALTUS Max E Series with LFW ALD technology offers a unique all-ALD deposition process that leverages Lam's PNL® (Pulsed Nucleation Layer) technology, which is the industry benchmark for tungsten ALD with 15 years of market leadership and more than 1,000 modules in production. Lam led the transition of chemical vapor deposition (CVD) tungsten nucleation to ALD tungsten nucleation with its PNL technology. The company continued that leadership by advancing low-resistivity tungsten solutions with its products ALTUS® Max with PNLxT™, ALTUS® Max with LRWxT™, and ALTUS® Max ExtremeFill™ for enhanced fill performance.

The ALTUS products use Lam's quad-station module (QSM) architecture to allow per-station optimization of tungsten nucleation and fill for fluorine, stress, and resistance without compromising fill performance since station temperature can be set independently. The QSM configuration also maximizes productivity of the all-ALD process by providing up to 12 pedestals per system, enabling the highest footprint productivity in the industry.

ALD & CVD Metal Manganese Precursors from Canada

The other day we had a paper by Barry Lab on how to make your own gold ALD precursor and now here another hot topic in ALD & CVD of Metal Manganese and for sure also this paper is from Canada as well! Manganese is being evaluated by Intel, Imec and others for sub 10 nm Cu barrier in BEOL metallization. Even if those barriers are just a couple of nano meters thin it is big business since the potential in BEOL is huge if the processes were to be used for a multiple wafer passes of the BEOL Cu metallization. Recently at 20/14 nm. It will be interesting to follow if Manganese will put up a fight against Cobalt or the slugger Ruthenium for future interconnect barriers and Cu caps.

Base-Free and Bisphosphine Ligand Dialkylmanganese(II) Complexes as Precursors for Manganese Metal Deposition

Jeffrey S. Price, Preeti Chadha, and David J. H. Emslie
Organometallics, Article ASAP, DOI: 10.1021/acs.organomet.5b00907
Publication Date (Web): December 30, 2015

 

 

Graphical abstract

 

The solid-state structures and the physical, solution magnetic, solid-state magnetic, and spectroscopic (NMR and UV/vis) properties of a range of oxygen- and nitrogen-free dialkylmanganese(II) complexes are reported, and the solution reactivity of these complexes toward H₂ and ZnEt₂ is described. The compounds investigated are [{Mn(μ-CH₂SiMe₃)₂}_∞] (1), [{Mn(CH₂CMe₃)(μ-CH₂CMe₃)₂}₂{Mn(μ-CH₂CMe₃)₂Mn}] (2), [Mn(CH₂SiMe₃)₂(dmpe)] (3; dmpe = 1,2-bis(dimethylphosphino)ethane), [{Mn(CH₂CMe₃)₂(μ-dmpe)}₂] (4), [{Mn(CH₂SiMe₃)(μ-CH₂SiMe₃)}₂(μ-dmpe)] (5), [{Mn(CH₂CMe₃)(μ-CH₂CMe₃)}₂(μ-dmpe)] (6), [{Mn(CH₂SiMe₃)(μ-CH₂SiMe₃)}₂(μ-dmpm)] (7; dmpm = bis(dimethylphosphino)methane), and [{Mn(CH₂CMe₃)(μ-CH₂CMe₃)}₂(μ-dmpm)] (8). Syntheses for 1–4 have previously been reported, but the solid-state structures and most properties of 2–4 had not been described. Compounds 5 and 6, with a 1:2 dmpe/Mn ratio, were prepared by reaction of 3 and 4 with base-free 1 and 2, respectively. Compounds 7 and 8 were accessed by reaction of 1 and 2 with 0.5 equiv or more of dmpm per manganese atom. An X-ray structure of 2 revealed a tetrametallic structure with two terminal and six bridging alkyl groups. In the solid state, bisphosphine-coordinated 3–8 adopted three distinct structural types: (a) monometallic [LMnR₂], (b) dimetallic [R₂Mn(μ-L)₂MnR₂], and (c) dimetallic [{RMn(μ-R)}₂(μ-L)] (L = dmpe, dmpm). Compound 3 exhibited particularly desirable properties for an ALD or CVD precursor, melting at 62–63 °C, subliming at 60 °C (5 mTorr), and showing negligible decomposition after 24 h at 120 °C. Comparison of variable-temperature solution and solid-state magnetic data provided insight into the solution structures of 2–8. Solution reactions of 1-8 with H₂ yielded manganese metal, demonstrating the thermodynamic feasibility of the key reaction steps required for manganese(II) dialkyl complexes to serve, in combination with H₂, as precursors for metal ALD or pulsed CVD. In contrast, the solution reactions of 1–8 with ZnEt₂ yielded a zinc–manganese alloy with an approximate 1:1 Zn/Mn ratio.

Tokyo Electron release Triase+™ EX-II™ TiN Plus HT, a Single-Wafer Metallization System

Tokyo Electron Single Wafer SFD (Sequential Flow Deposition) has been dominating the market for e.g. TiN DRAM Capacitor electrodes for a long time. Recently (2013) it was updated to AFSD as in Advanced Sequential Flow Deposition. Tokyo Electron used to claim that they had this position because they had ClF3 chamber in-situ clean technology, but there are a number of other reasons. For those of you familiar with the TiCl4/NH3 ALD process know that there are two major issues:

1. Growth nucleation - for thermal oxide it can be as many as 100 deposition cycles before growth starts.
2. Low growth rate of 0.3 to 0.4 Å/cycle

SFD already addressed booth issues and with ASFD Tokyo Electron addressed lower thermal budget and improved conformality for high aspect ratio applications. Now it is very interesting to see what will happen when Tokyo Electron has released their new version of the ASFD process and the Trias Platform - The Triase+TM EX-IITM TiN* Plus HT single-wafer metallization system with HT as in High Temperauture. One reason to target high temprature is to achieve better performance (lover contact resistance) for Ti/TiN/W in for example:

1) Burried Word Lines in DRAM & coming RRAM

Since the introduction by Qimonda in 2008 (65nm DRAM) all companies uses burried tungsten word lines. 2014 Micron also presnted this technology for RRAM. Since this is a front end process there is absolutely no concern of process temperature.

Micron and Sony get together to build a 27-nm 16Gb Cu-ReRAM (IEDM 2014) 

2) High aspect ratio low resistivity electrodes and gates. 

Thinner electrode materials are needed due to geometrical constraints for scaled devices using high aspect ratio electrodes and metal gates like in DRAM and 2nd generation 3DNAND.

Samsung sub 20 nm DRAM technology presented at IEDM 2015 (Solid State Technology)

Samsung 1st generation 3DNAND investigated by Chipworks showing high aspect ratio metal gates and contacts.

Tokyo Electron Limited (TEL) announced today that it will begin accepting orders for the Triase+TM EX-IITM TiN* Plus HT single-wafer metallization system in April 2016.

Its base model, the Triase+ EX-II TiN, is a high-speed single-wafer ASFD* system with an optimized reactor chamber and unique gas injection mechanism. Since its introduction in January 2013, the Triase+ EX-II TiN has established itself as the standard for single-wafer ASFD TiN metallization systems, and has been adopted by memory and logic device manufacturers throughout the world. The Triase+ EX-II TiN Plus, an upgraded model that became available for booking in July 2015, has also been enthusiastically received in the market.

The continued scaling of semiconductor technologies has required that TiN processes in advanced device manufacturing become more detailed and diverse than ever before. TiN deposition systems must now overcome new technical challenges at highly sophisticated levels.

The EX-II TiN Plus HT, which will soon be available to order, has specialized hardware for high-temperature processes and is capable of depositing TiN film of a lower resistance and lower impurity-key technical requirements for advancing semiconductor scaling. Customers already using the Triase+ EX-II TiN or the EX-II TiN Plus can upgrade to the EX-II TiN Plus HT by modifying their existing systems, thereby reducing investment costs.

"The Triase+ EX-II TiN Plus HT is the latest generation system in the series," said Takeshi Okubo, Executive Officer and General Manager, SDBU at TEL. "It is equipped to perform high-temperature processes to satisfy new technical requirements resulting from the scaling of semiconductors, while maintaining the excellent within-wafer uniformity and step coverage achieved by the preceding EX-II TiN Plus. TEL will keep tackling difficult technology development issues to deliver high value-added products for broad-ranging thin film deposition applications."

* TiN: Titanium Nitride; ASFD: Advanced Sequential Flow Deposition, a low-temperature processing method for forming nanoscale metal films with highly-engineered properties.

The limits of ALD barrier seed for Cu metallization

Here is a great piece by ED KORCZYNSKI, Senior Technical Editor at Solid State Technology on the practical limits for metallization beyond 14nm tthat inspired me too dig into ALD Mn self forming barriers.

http://electroiq.com/blog/2015/12/practical-limits-for-metallization-scaling-in-fabs/

Ed states that one of the limitation for Cu metallization will actually be how thin you can deposit an ALD barrier/seed layer (see figure below).

IBM Research showcases Carbon Nanotubes (CNT) down to 9nm contact

Here is A breakthrough news from IBM Watson Research Center on integrating CNTs down to 9nm contacts. This section from a recent interview with one of the researchers, Shu-Jen Han, behind this work taken from The IBM Research Blog:

Silicon has offered many advantages as a transistor material for the last half century. One biggest perhaps was that it forms a great gate dielectric – SiO2. It also comes with a very pure and high quality substrate, silicon wafers, to start with. And over time we’ve used other materials and device structures to improve its abilities, such as transitioning to high-k metal gate transistors and FinFETs.

On the other hand, for carbonnanotubes, many material issues have to be solved to obtain similar high-quality carbon nanotube wafers for device fabrication. We can’t switch to an entirely new material over night, but silicon is reaching its scaling limits.

 

 

Dr. Qing Cao and my other teammates at [the IBM Watson Research Center] developed a way, at the atomic level, to weld - or bond – the metal molybdenum to the carbon nanotubes' ends, forming carbide. Previously, we could only place a metal directly on top of the entire nanotube. The resistance was too great to use the transistor once we reached about 20 nm. But welding the metal at the nanotubes' ends, or end-bonded contacts, is a unique feature for carbon nanotubes due to its 1-D structure, and reduced the resistance down to 9 nm contacts. Key to the breakthrough was shrinking the size of the contacts without increasing electrical resistance, which impedes performance. Until now, decreasing the size of device contacts caused a commensurate drop in performance.

For full details on this breakthrough research please see a recently published article in Science:

End-bonded contacts for carbon nanotube transistors with low, size-independent resistance

Qing Cao, Shu-Jen Han, Jerry Tersoff, Aaron D. Franklin, Yu Zhu, Zhen Zhang, George S. Tulevski, Jianshi Tang, Wilfried Haensch

Science 2 October 2015:
Vol. 350 no. 6256 pp. 68-72
DOI: 10.1126/science.aac8006 

Moving beyond the limits of silicon transistors requires both a high-performance channel and high-quality electrical contacts. Carbon nanotubes provide high-performance channels below 10 nanometers, but as with silicon, the increase in contact resistance with decreasing size becomes a major performance roadblock. We report a single-walled carbon nanotube (SWNT) transistor technology with an end-bonded contact scheme that leads to size-independent contact resistance to overcome the scaling limits of conventional side-bonded or planar contact schemes. A high-performance SWNT transistor was fabricated with a sub–10-nanometer contact length, showing a device resistance below 36 kilohms and on-current above 15 microampere per tube. The p-type end-bonded contact, formed through the reaction of molybdenum with the SWNT to form carbide, also exhibited no Schottky barrier. This strategy promises high-performance SWNT transistors, enabling future ultimately scaled device technologies. 

Ruthenium may take over from Copper for advanced Interconencts according to Imec

Here is an interesting report by Jeff Dorsch from SEMI’s annual Strategic Materials Conference, that was held September 22-23, at the Computer History Museum in Mountain View, California.

SEMI Conference Addresses Issues in Semiconductor Materials 

One of the most interesting things i find i that ruthenium is back on the table, at least according to Imecs Christoph Adelmann who presented that ruthenium my take over from copper in advanced interconnects one day. This is not the first time ruthenium is announced entering into semiconductor manufacturing. Many ruthenium R&D programs has started and eneded many times the last decade at IDMs, OEMs and materials suppliers especially at DRAM manufacturers looking to integrate SrTiO3 super high-k using ruthenium based electrodes in the capacitor module. So it is time again to have a look at the Ruthenium price development at Johnson Matthey.

Today the ruthenium price is actually as low (~150$/Oz.) as is was the first time I got involved in ruthenium ALD/CVD development in 2003 at Infineon. It will be very interesting to follow ruthenium this time  and if it would actually enter BEOL metallization the price should go up considerably since it does come again many times an an advance interconnect chip 12-16 depending on the design but not all layers may have to contain ruthenium so the upper layer will stay copper for a long time to come. Anotehr driver for sure is if ruthenium were to be used in 3D-stacing TSV technology - Maybe a good timing now to invest in some ruthenium!

Pt & Ru price chart generated at http://www.platinum.matthey.com/prices

Platinum, RutheniumMonthly Average prices between 30 Sep 2000 and 30 Sep 2015JM Base Price $/0zPlatinum average: $1,165.38, Ruthenium average: $150.59 - See more at: http://www.platinum.matthey.com/prices/price-charts#sthash.GMP3wwcI.dpuf

Platinum, RutheniumMonthly Average prices between 30 Sep 2000 and 30 Sep 2015JM Base Price $/0zPlatinum average: $1,165.38, Ruthenium average: $150.59 - See more at: http://www.platinum.matthey.com/prices/price-charts#sthash.GMP3wwcI.dpuf

Platinum, RutheniumMonthly Average prices between 30 Sep 2000 and 30 Sep 2015JM Base Price $/0zPlatinum average: $1,165.38, Ruthenium average: $150.59 - See more at: http://www.platinum.matthey.com/prices/price-charts#sthash.GMP3wwcI.dpuf

Imec and Lam Research Corporation Develop Novel ELD Metallization

New Approach to Pave the Way for Advanced Interconnects Enabling Future Technology Nodes

IEEE IITC, Grenoble (France)—May 19, 2015— During the IEEE IITC conference in Grenoble, the nanoelectronics research center imec and Lam Research Corporation today presented a novel bottom-up prefill technique for vias and contacts. The technique, based on Electroless Deposition (ELD)* of Cobalt (Co) is a highly selective method resulting in void-free filling of via and contact holes. Potentially increasing the circuit performance, it is a promising path to scaling advanced interconnects and enabling future logic and DRAM nodes at the 7 nm node and below.

Co ELD on Palladium/Tungsten (Pd/W) for different timed stops to yield an (i) under fill, (ii) potential ideal stop or an (iii) overburden in 28nm holes (Aspect Ratio (AR) 4.5).

As logic and memory nodes scale, performance of these advanced interconnects is negatively impacted by increasing interconnect resistance. Furthermore, voids that occur in heavily scaled vias severely impact yield. Imec’s industrial affiliation program on advanced interconnects is exploring novel metallization methods to solve these issues. One way to solve the problem is to identify integration and metallization alternatives that provide resistance benefits over conventional technology without compromising reliability and yield. Together with Lam Research, a Co ELD technique was demonstrated as a feasible method for highly selective bottom-up contact fill and via prefill with Cobalt (Co) as an alternative metal to Copper (Cu). Moreover, the high selectivity of the ELD process, at lower cost compared to Chemical Vapor Deposition (CVD), intrinsically ensures a good metal-to-metal interface and paves the way to void-free via filling and increased yield. Trench fill yield and line resistance may also benefit from the de-coupling of line and via aspect ratios, permitting the design of each for optimum Resistance/Capacitance (RC). Therefore, Co prefill ELD has the potential to enable future scaling of advanced logic and memory technologies.

The results were achieved in cooperation with imec’s key partners as part of its core CMOS programs: GlobalFoundries, Intel, Samsung, SK hynix, Sony, TSMC, Amkor, Micron, Utac, Qualcomm, Altera, Fujitsu, Panasonic, and Xilinx.

* ELD means fire in Swedish, how did I not see this one coming... All these wasted years with ALD...