Showing posts with label CMP. Show all posts
Showing posts with label CMP. Show all posts

Tuesday, September 18, 2018

IITC-MAM2019 First Call for Papers

The 22nd edition of the International Interconnect Technology Conference (IITC) is sponsored by the IEEE Electron Devices Society as the premier conference for interconnect technology. The 28th edition of the Materials for Advanced Metallization workshop (MAM) is devoted to research on materials properties and interactions of interconnect and silicide materials. These two conferences will be combined again in 2019 for the 3rd joint IITC-MAM conference and feature compelling invited talks and be proceeded by a materials workshop. 

Authors are encouraged to submit their original work describing innovative research and development in the critically important felid of on-chip interconnects. The conference seeks papers on all aspects of BEOL/MOL interconnects and metallization, including design, unit process, integration and reliability.


  • Advanced interconnects with low-k dielectrics
  • Beyond Cu interconnect, optical, wireless, and carbon
  • Contacts to MOS devices: Silicide, III-V, 2D materials
  • BEOL elements for Memory: 3D NAND, CBRAM, PCRAM, ReRAM, MRAM, DRAM
  • Advanced packaging and 3D/2.5D integration: WtW/CtW bonding, Interposer, TSV, CPI, Fan-Out techniques, Integrated Fan-Out
  • Smart technologies for interconnects: AI/neuromorphic, machine learning, big data.
  • Process integration, advanced patterning for MOL/BEOL
  • Materials and Unit Processes: dielectrics, metals, barriers, wet, CMP, PVD, CVD, ALD, selective deposition/SAMs
  • Reliability and Failure analysis, techniques and methods
  • Advanced characterization: material analysis, analytical techniques, process modelling, defectivity, EPE
  • System scaling: design-technology co-optimization, embedded functionalities (memory, MEMS, Sensors...) Novel Systems/form factors: flexible, wearables, etc.
More information: LINK