ITRS 2013 Emerging Research Devices on HfO2 based ferroelectric devices

ITRS 2013 Emerging Research Devices (ERD) Chapter has been updated on ferroelectric devices (page 13) referring to recent development using ferroelectric hafnium oxide.

From Page 12 : Notably, since 2011, ferroelectricity in a variety of doped and polycrystalline HfO2 has been reported. The HfO2 based FeFETs show promising write speed (down to a few ns), retention (projected to 10 years), and endurance (up to 1012), which all match the best performances of its perovskite counterparts (refer to ERD4a). [65,66,67,68,69], and HfO2-based FeFETs have been fabricated using standard high-k metal gate (HKMG) processes. The use of HfO2-based ferroelectrics significantly reduces the physical thickness of the gate stack, and in turn scales down the channel length to the current technology node [70]. Follow the typical HKMG process, SiO2 serves as the buffer layer between HfO2 and Si with a sub-nanometer thickness, yielding low depolarization field.

"In Ferroelectric FET memory, a ferroelectric dielectric forms the gate insulator of an FET. The main concern on FeFET memory lies in operation reliability. Operational reliability of the FeFET RAM is limited by the time dependant remnant polarization of the ferroelectric gate dielectric reflected in retention loss. Control of the ferroelectric-semiconductor interface is critical for FeFET properties. The scalability of FeFET memory beyond the 22nm generation is uncertain"

 

As a comparasion to RRAM, one of the main contenders for emerging memory technologies:

 

"RRAM include multiple device types and mechanisms with varying level of maturity. The survey is based on rating of the general field rather than specific types. Some recent breakthrough in RRAM significantly enhanced perceived potential of this technology, e.g., 32Gb array demonstration726. Overall RRAM assessment is similar or better than existing CMOS-based nonvolatile memories (Flash). A clear advantage of RRAM is scalability owing to the filamentary conduction and switching mechanisms. The simple device structure and fab-friendly materials also contribute to high rating in CMOS compatibility. One of the major concerns of RRAM is the operation reliability due to the stochastic nature and the defect-related mechanisms. Large variation of RRAM switching parameters has been commonly observed and is considered an intrinsic feature of RRAM mechanisms."

 

Refernces on FeFET:

[65] T. S. Boscke, J. Muller, D. Brauhaus, U. Schroder, and U. Bottger, "Ferroelectricity in hafnium oxide: CMOS compatible ferroelectric field effect transistors," IEDM 2011, pp. 24.5.1–24.5.4.
[66] M. Hyuk Park, H. Joon Kim, Y. Jin Kim, W. Lee, H. Kyeom Kim, and C. Seong Hwang, "Effect of forming gas annealing on the ferroelectric properties of Hf0.5Zr0.5O2 thin films with and without Pt electrodes," Appl. Phys. Lett., vol. 102, no. 11, p. 112914, 2013.
[67] J. Muller, et al, "Ferroelectricity in yttrium-doped hafnium oxide," J. Appl. Phys., vol. 110, no. 11, p. 114113, 2011.
[68] J. Muller, et al, "Ferroelectric Zr0.5Hf0.5O2 thin films for nonvolatile memory applications," Appl. Phys. Lett., vol. 99, no. 11, p. 112901, 2011.
[69] S. Mueller, J. Mueller, A. Singh, S. Riedel, J. Sundqvist, U. Schroeder, and T. Mikolajick, "Incipient Ferroelectricity in Al-Doped HfO2 Thin Films," Adv. Funct. Mater., vol. 22, no. 11, pp. 2412–2417, Jun. 2012.

[70] J. Muller, E. Yurchuk, T. Schlosser, J. Paul, R. Hoffmann, S. Muller, D. Martin, S. Slesazeck, P. Polakowski, J. Sundqvist, M. Czernohorsky, K. Seidel, P. Kucher, R. Boschke, M. Trentzsch, K. Gebauer, U. Schroder, and T. Mikolajick, "Ferroelectricity in HfO2 enables nonvolatile data storage in 28 nm HKMG," 2012 Symp. VLSI Tech., pp. 25–26, 2012

 

Emerging memory taxonomy according to ITRS 2013

For all of you working on emerging memory technologies such as ReRAM, FeRAM, PCM, MRAM etc. this classification scheme in the latest ITRS roadmap should be very useful. Please check out the  ERD - Emerging Research Devices Chapter.

"Figure ERD3 [inserted below] provides a simple visual method of categorizing memory technologies. At the highest level, memory technologies are separated by the ability to retain data without power. Nonvolatile memory offers essential use advantages, and the degree to which non-volatility exists is measured in terms of the length of time that data can be expected to be retained. Volatile memories also have a characteristic retention time that can vary from milliseconds to (for practical purposes) the length of time that power remains on. Nonvolatile memory technologies are further categorized by their maturity. Flash memory is considered the baseline nonvolatile memory because it is highly mature, well optimized, and has a significant commercial presence. Flash memory is the benchmark against which prototypical and emerging nonvolatile memory technologies are measured. Prototypical memory technologies are at a point of maturity where they are commercially available (generally for niche applications), and have a large scientific, technological, and systematic knowledge base available in the literature. These prototypical technologies are covered in Table ERD2 and in the PIDS Chapter. The focus of this section is Emerging Memory Technologies. These are the least mature memory technologies in Fig. ERD4, but have been shown to offer significant potential benefits if various scientific and technological hurdles can be overcome. This section provides an overview of these emerging technologies, their potential benefits, and the key research challenges that will allow them to become viable commercial technologies."

 

Figure ERD3, from the ERD Chapter 2013 - Emerging memory taxonomy (ITRS 2013, Chapter ERD) 

 

If you continue to read from page 8 on you will find a short description of all emerging memory technologies that are being considered by he ITRS. If you´re saturated on resistive technologies you can fast forward to page 12 and read about the new contender FeFET :-)

 

The new ITRS 2013 edition

The new 2013 edition is now released since about a month Follow this link to the Summary Files. However, not all areas/Chapters has been updated. As an example, for Front End Process (FEP) Chapter the status is as follows:

Updated FEP Roadmap tables are: High Performance Devices, Low Standby Power Devices, FeRAM, Thermal, Thin Film, Doping Process Technology, Starting Materials, and Surface Preparation.

 

"Likely to be updated" in 2014: Updates to DRAM, Floating Gate Flash Non-Volatile memory (NVM), Charge Trap Flash NVM, Phase Change Memory, Etch and CMP.

 

We can assume that Samsung, Hynix, Micron, Toshiba and the guys will have some interesting meetings ahead to conclude what to put in those tables :-)

What is The International Technology Roadmap for Semiconductors - ITRS?

"The International Technology Roadmap for Semiconductors is sponsored by the five leading chip manufacturing regions in the world: Europe, Japan, Korea, Taiwan, and the United States. The sponsoring organizations are the European Semiconductor Industry Association (ESIA), the Japan Electronics and Information Technology Industries Association (JEITA), the Korean Semiconductor Industry Association (KSIA), the Taiwan Semiconductor Industry Association (TSIA), and the United States Semiconductor Industry Association (SIA)."

 

"The objective of the ITRS is to ensure cost-effective advancements in the performance of the integrated circuit and the advanced products and applications that employ such devices, thereby continuing the health and success of this industry."

 

The International Technology Roadmap for Semiconductors is sponsored by the five leading chip manufacturing regions in the world: Europe, Japan, Korea, Taiwan, and the United States. (source : http://www.itrs.net/about.html)

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