Here is a impressive report by SK Hynix & Prof. Hwang and co-workers SNU on a RRAM device with Ta/Ta2O5 stacked RS layers with ultra-thin Ta2O5 thicknesses (0.5–2.0 nm) deposited by ALD. Woah that´s thin - like the same order of thickness like native oxide, which makes me wonder if teh extra couple of ALD cycles was needed --> I need to study the paper more carefully!
Thickness effect of ultra-thin Ta2O5 resistance switching layer in 28 nm-diameter memory cell
C.S. Hwang et al
(a) Schematic diagram and (b) TEM image of the TiN/Ta2O5/Ta/TaN device. Ta2O5 (0.5 nm) device, and (d) Ta2O5
(1.5 nm) device. Insets show the linear I-V plot. Scanning transmission
electron microscopy (STEM) high angle annular dark field (HAADF) images
of (c) 0.5 nm-thick device and (d) 2.0nm-thick device.
Resistance switching (RS) devices with ultra-thin Ta2O5
switching layer (0.5–2.0 nm) with a cell diameter of 28 nm were
fabricated. The performance of the devices was tested by voltage-driven
current—voltage (I-V) sweep and closed-loop pulse switching (CLPS)
tests. A Ta layer was placed beneath the Ta2O5 switching layer to act as an oxygen vacancy reservoir. The device with the smallest Ta2O5
thickness (0.5 nm) showed normal switching properties with gradual
change in resistance in I-V sweep or CLPS and high reliability. By
contrast, other devices with higher Ta2O5
thickness (1.0–2.0 nm) showed abrupt switching with several abnormal
behaviours, degraded resistance distribution, especially in high
resistance state, and much lower reliability performance. A single
conical or hour-glass shaped double conical conducting filament shape
was conceived to explain these behavioural differences that depended on
the Ta2O5 switching layer thickness. Loss of oxygen via lateral diffusion to the encapsulating Si3N4/SiO2 layer was suggested as the main degradation mechanism for reliability, and a method to improve reliability was also proposed.
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