Showing posts with label 3nm. Show all posts
Showing posts with label 3nm. Show all posts

Thursday, April 2, 2020

TSMC hit by 3nm delay fears over Covid-19 Lock-downs

TSMC is on schedule with its 5 nm process plan, but its 3 nm trial production may get delayed: The world's largest contract chipmaker is planning to launch mass production of its 3 nm process sometime in 2022, and media reported Monday that installation of production equipment in its 3 nm wafer fab in Tainan will be delayed to October from June this year, which will delay its trial production set for 2021. The COVID-19 escalation has hit Europe, and [Netherlands-based] ASML Holding, which is TSMC's major production equipment supplier, has been affected by a lockdown. It is understandable that the progress of TSMC's new technology has been affected.

Below a comparison of the Covid-19 daily new confirmed deaths, which is the only comparable parameter to use due to different testing capabilities and frequencies, in time and nation to nation. As can be seen the situation in Asian is under control after the gotten hit by the first wave of the Coronavirus. The European situation is stabilizing: Italy, Netherlands, Germany France, others look similar and are flattening the curve. In The USA situation is escalating. Many nations in Europe are forecasting a lift of Lockdown in May but are very careful, as an example Germany will decide in 19 April how to proceed according to Chancellor Dr. Angela Merkel.

BALD Engineering AB continues to monitor the Covid-19 situation due to lockdowns that affect the  the semiconductor industry – Stay Safe!

Google Finance (2020-04-02, 10:39 CET)

Sources:

Taiwan shares edge lower, TSMC hit by 3nm delay fears

Our World of data: https://ourworldindata.org/coronavirus

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By Abhishekkumar Thakur, Jonas Sundqvist

Saturday, January 4, 2020

Samsung's 3 nm Gate-All-Around FET prototype

Samsung has succeeded in making the first strides towards the 3 nm process, as reported by the Korean Maeil Economy this week. According to the report, Samsung's goal is to become the world's number one semiconductor manufacturer by 2030.

Samsung's work on the 3 nm process is based on the Gate All Around (GAAFET) technology rather than FinFET. This supposedly reduces the total silicon size by 35% while using about 50% less power and allows for the same amount of power consumption and 33% performance increase over the 5 nm FinFET process.


Gate-All-Around FETs - Picture credit: Samsung

Source: Toms Hardware (LINK)

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By AbhishekkumarThakur

Thursday, July 4, 2019

Lam Research’s Richard Gottscho shares his perspective advanced processes for 5 and 3 nm

5nm, 3nm, or something in between? Lam Research’s Richard Gottscho shares his perspective on how chipmakers should prepare for the next wave of advanced processes in a Semiconductor Engineering article.


Semiconductor Engineering: LINK