Jumpstart Your Semiconductor Career: ALD Process Engineer III Position in Santa Clara with Competitive Compensation and Benefits!

ALD Process engineer is the best possible start into a future career in the ever-evolving Semiconductor Industry. This Process Engineer III – (E3) position in Santa Clara, CA focuses on designing, analyzing, and troubleshooting complex problems within the semiconductor realm. Candidates should possess a Bachelor's Degree with 4-7 years of experience. The role includes a salary range of $116,000.00 to $159,500.00, potential bonus opportunities, and a comprehensive benefits package, with 10% travel time.

Apply here - Process Engineer III – (E3)

Careers (myworkdayjobs.com)

Stay informed in the ALD LinkedIn Group and chat with the hiring manager!

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ALD TechDay at SEMICON Europa 2023 Hosted by Beneq

Join us for an exclusive expert forum discussing the adoption and applications of Atomic Layer Deposition (ALD) in the semiconductor industry. Powered by Beneq, this event is scheduled for Tuesday, November 14, from 3:00 pm to 5:30 pm at the Internationales Congress Center München (ICM).

Key Insights:

- Learn about the scaling of logic and memory semiconductor devices enabled by ALD.

- Discover ALD's rapid adoption in specialty device fabrication, particularly in wide-bandgap power semiconductors.

- Yole Group's projection reveals a 12% yearly growth in ALD equipment sales, reaching a record $680.5M by 2026.

- Get insights from industry experts, including speakers from Yole Intelligence, Beneq, and imec.

- Engage in discussions with a live panel of innovators and attend keynotes detailing innovative ALD applications, tool solutions, and case examples.

This event is tailored for integrated device manufacturers, foundries, and research and technology organizations. If you're invested in specialty semiconductor devices—from advanced packaging and CMOS image sensors to optoelectronics and power devices—this is an unmissable opportunity.

Attendance is complimentary but by invitation only. If interested, please register through our interest form.

Wrap up the day with the ALD TechDay networking gala dinner, a perfect platform for idea exchange and collaborative exploration.

*About Beneq:* A pioneering leader in atomic layer deposition, Beneq has been at the forefront since 1984. With a vast product range and unique development services, Beneq remains committed to simplifying ALD processes for researchers and shortening the time to market with its state-of-the-art ALD production.

ASML and Lam Research Navigate US Chip Restrictions with Continued Focus on China

The evolving landscape of the global semiconductor industry, marked by the escalating US chip curbs, has seen two industry leaders, ASML and Lam Research, maintain a significant focus on the Chinese market. ASML, the Dutch semiconductor behemoth, has reported a remarkable surge in its sales to China. As they dominate the market for DUV lithography machines, essential for chip production, sales to China for ASML soared to €2.44 billion ($2.58 billion) in the recent quarter, nearly doubling the figures from the previous one. Meanwhile, Lam Research, a US chipmaking equipment supplier for CVD, ALD and Etch, is experiencing a year-on-year decline in revenue by 31.4% to $3.5 billion in the quarter ending Sept. 24, remains buoyant about the Chinese market. With China accounting for a staggering 48% of its total revenue, up from 30% the previous year and 26% in the preceding quarter, CEO Tim Archer remains optimistic. He emphasized that the new U.S. export restrictions brought no unforeseen challenges and anticipates sustainable business growth in China, citing the country's long-term objectives.

Photo : ASML on X

However, it's not all smooth sailing. As the US and the Netherlands tighten their grip on chip equipment exports in an attempt to curb China's burgeoning semiconductor industry, challenges arise for these giants. Notably, Lam Research's shares fell by over 5% in extended trading after Archer's announcement. Furthermore, even though both ASML and Lam Research foresee continued demand from China, the trajectory remains uncertain with the intricate web of export controls and regulations. Still, with giants like KLA, Applied Materials, Tokyo Electron, and the aforementioned firms steering the ship, the semiconductor industry remains hopeful about navigating these turbulent waters.

ASML System sales by region 3Q/2023 (ASML.com)

ASML ArFi vs EUV sales by quarter pic.twitter.com/upEE0vXwpO

— Fred Chen (@DrFrederickChen) October 18, 2023

Sources:

ASML stays optimistic on China as sales surge amid U.S. chip curbs - Nikkei Asia

Lam Research sees no material impact from new U.S. chip curbs - Nikkei Asia

Micron Unveils Breakthrough NVDRAM: A Dual-Layer 32Gbit Non-Volatile Ferroelectric Memory with Near-DRAM Performance

At the upcoming International Electron Devices Meeting (IEDM), Micron is set to present a paper on a novel 32Gbit non-volatile ferroelectric memory, termed NVDRAM. Authored by Nirmal Ramaswamy, the vice president of advanced DRAM and emerging memory at Micron, the paper is titled "NVDRAm: A 32Gbit Dual Layer 3D Stacked Non-Volatile Ferroelectric Memory with Near-DRAM Performance for Demanding AI Workloads". It introduces the world’s first dual-layer, high-performance, 32Gbit stackable ferroelectric memory technology. This technology, branded as non-volatile dynamic random access memory (NVDRAM), promises faster data movement and better energy efficiency than traditional DRAM, making it ideal for larger neural network models.

NVDRAM merges the benefits of ferroelectric memory cells – non-volatility and high endurance – with performance surpassing NAND flash memory retention and offering DRAM-like read/write speeds. The memory's architecture uses a 5.7nm ferroelectric capacitor for charge retention in a 1T1C DRAM structure, while dual-gated polycrystalline silicon transistors control access. The stacked double memory layer resides above a CMOS access circuit layer on a 48nm pitch. Despite the technological advancements, commercialization discussions remain speculative, potentially awaiting feedback from the IEDM presentation.

The images above show the final die layout (left) and SEM cross-section (center) of a 32Gb NVDRAM with 1T1C memory layers, fabricated over a CMOS array. On the right is a schematic diagram of NVDRAM memory arrays, showing polysilicon access device with orthogonal wordline (WL) and digitline (DL), and ferroelectric memory cells.

Abstract: Non-Volatile Ferroelectric w/DRAM-Like Performance, for AI & Machine Learning: Rapid growth in the size of the data models used in artificial intelligence (AI) and machine-learning (ML) applications is creating an urgent need for higher-bandwidth memory solutions. While new compute paradigms like near-memory-compute and processing-in-memory are being investigated, the best near-term opportunity is to outfit existing, traditional compute architectures with more efficient memory for faster data movement and to accommodate larger models. In this year’s Generative AI Focus Session, Micron researchers will unveil a memory technology for these uses which they call NVDRAM. It is the world’s first dual-layer, high-performance, high-density (32Gb), stackable and nonvolatile ferroelectric memory technology. It combines the non-volatile, high-endurance nature of ferroelectric memory cells with DRAM-like read/write speeds and endurance, and also surpasses the retention performance of NAND memory. NVDRAM uses an ultra-scaled (5.7nm) ferroelectric capacitor as the memory cell, and a dual-gated, stackable, polycrystalline silicon transistor as the access device. To achieve high memory density, two memory layers are fabricated above CMOS circuitry in a 48nm pitch, 4F2 architecture. Full package yield is demonstrated from -40°C to 95°C, along with reliability of 10 years (for both endurance and retention).

Sources:

eeNews: IEDM: Micron to present DRAM-like non-volatile memory for AI ... (eenewseurope.com)

IEDM Paper: 15.7_Non-Volatile Ferroelectric with DRAM-Like Performance, for AI & Machine Learning_Micron.docx (egnyte.com)

Kokusai Electric's Successful IPO Raises $724.4 Million, Japan's Largest in 5 Years

Japanese chip equipment manufacturer Kokusai Electric has successfully raised $724.4 million through its initial public offering (IPO) by pricing its shares at the top end of a reduced marketing range. The IPO, Japan's largest in five years, saw Kokusai Electric value its shares at 1,840 yen per share, giving the company an overall valuation of 423.9 billion yen ($2.84 billion). The decision to lower the price range was influenced by the underwhelming performance of chip designer Arm's shares following its recent listing. Kokusai Electric's shares are set to debut on the Tokyo exchange's Prime Market on October 25. The company's major customers include Samsung Electronics, TSMC, and Micron Technology, accounting for over 40% of its revenue.

TSURUGI-C²® is a KOKUSAI ELECTRIC’s new thermal processing platform which is most recently developed for advanced devices especially for the ones with high aspect ratio 3D structures requiring high quality, uniform and conformal film deposition with new innovative reactor design and process techniques.

Kokusai Electric specializes in deposition and treatment process equipment for semiconductor manufacturing. Their deposition equipment is designed for creating nanoscale thin films on semiconductor wafers and supports technologies like LP-CVD, oxidation, annealing (low and high temperature), diffusion, and ALD. Notable products include TSURUGI-C², designed for advanced devices with complex 3D structures, AdvancedAce®-300 for batch thermal processing of 300mm wafers, and VERTRON® Revolution for 200-mm batch thermal processing.

Kokusai Electric's treatment equipment improves film properties through processes like nitridation, oxidation, curing, and annealing. MARORA® is ideal for gate dielectric film formation, utilizing plasma with low electron temperature. TANDUO® offers modular single-wafer treatment for various processes, and AdvancedAce®-300 supports LP-CVD, oxidation, annealing, and diffusion.

These equipment offerings are essential for semiconductor manufacturing, enabling the production of high-quality, high-performance components used in diverse electronic devices.

Sources:

Kokusai Electric raises $724.4 mln after setting IPO price at the top end of range | Reuters

Products＆Services | KOKUSAI ELECTRIC CORPORATION (kokusai-electric.com)

US Researchers Achieve Record 25.1% Efficiency with Large Perovskite-Silicon Tandem Solar Cell

US scientists have achieved a breakthrough in photovoltaic (PV) cell technology by creating a large-area perovskite-silicon tandem solar cell measuring 24 cm2. This tandem cell has achieved a remarkable steady-state power conversion efficiency of 25.1%. To overcome common issues associated with scaling up perovskite solar technologies, such as shunting losses that create alternate pathways for solar-generated charge and lead to power losses, the researchers inserted a lithium fluoride (LiF) interlayer between a hole transport layer (HTL) and a wide bandgap (WBG) perovskite absorber. This interlayer improves physical contact and reduces shunting. The tandem cell demonstrated an efficiency of 25.2% under standard conditions, making it one of the most efficient two-terminal tandem devices for areas exceeding 10 cm2. This development holds promise for efficient, reproducible, and large-scale perovskite-silicon tandem solar cells.

Current-voltage curves for a perovskite mini-module with an aperture area of 42.9 cm2 Image: University of North Carolina at Chapel Hil, Cell Reports Physical Science, Creative Commons License CC BY 4.0

ALD is an important technology in perovskite solar cell fabrication. It enables precise, nanoscale control of layer thickness, ensuring uniform coverage even on complex surfaces. ALD is used for depositing passivation layers to reduce defects and enhance stability, creating protective barriers against environmental factors, engineering interfaces for improved charge transport, and ensuring compatibility with various materials. These applications contribute to improving the efficiency and long-term stability of perovskite solar cells, making ALD an essential tool in their development and optimization.

For deployment in solar cells, "perovskite" denotes a particular class of materials employed as the light-absorbing layer. These perovskite solar cells utilize a group of materials characterized by a crystalline structure akin to that of the mineral perovskite, named after Russian mineralogist Lev Perovski. Typically, these materials are comprised of organic-inorganic hybrid compounds, with common examples including methylammonium lead iodide (CH3NH3PbI3) and formamidinium lead iodide (HC(NH2)2PbI3). Perovskite solar cells have garnered substantial interest due to their potential for high efficiency, cost-effectiveness in production, and simplified manufacturing processes. Researchers are diligently working to enhance the efficiency, stability, and scalability of perovskite solar cells to position them as a competitive and sustainable renewable energy solution.

Source: Large-area perovskite-silicon tandem PV cell hits record efficiency of 25.1% – pv magazine International (pv-magazine.com)

Semiconductor Supply Chain Problems Running Rampant?

Solutions to mitigate future materials supply vulnerabilities

By Lita Shon-Roy, MS/MBA, and Sachi Brown, TECHCET CA

Over the past 2 to 3 years, the semiconductor industry has faced extreme pressure to meet growing consumer demand for an abundance of everyday electronic products like cars, smartphones, and computers. This pressure has only been amplified by various supply chain issues stemming from the raw material sources that are essential to building semiconductors. These material dependencies are easy to overlook since they reside in the sub-tier of the semiconductor market, hidden from direct view of what is sold to chip fabricators and consumers. TECHCET, a leading materials supply chain analysis firm, has consistently worked to uncover many of these dependencies, such as for fluorspar, neon, and helium. These materials play an essential role in the supply chain lifeline to the semiconductor industry and require expertise to identify, qualify, and track for the efficient forward movement of the market.

With recent chip shortages, various producers around the world have announced plans to invest in chip expansions that total more than US$500B over the next five years. For the US alone, this equates to an increase of >45% in semiconductor wafer starts by 2026. While this sounds hopeful for resolving chip deficiencies, it still does not address one key weakness: material shortages. As the industry expands, the risk of complications to the semiconductor supply chain grows, elevating the importance for material supply chain tracking and analysis.

Sulfuric acid is one example of an essential material that would put the semiconductor supply chain at risk if its supply is not properly managed. Fortunately, TECHCET has identified a >50% increase in demand for US sulfuric acid by 2026 to help key chip fabs prepare for expansions. TECHCET consistently provides key metrics related to supply and demand to the Critical Materials Council (CMC), a consortium formed in the mid-1990’s made up of chip fabricators and material suppliers. The Council also provides feedback to TECHCET to direct their ongoing supply chain analysis work. Identifying materials-related disruptions, dependencies, and weaknesses within the supply-chain, are all key elements of TECHCET’s focus and benefits to the CMC subscriber members.

In recent years, material shortages from the Russia-Ukraine conflict and COVID-19 have proven to be high stress points for chip fabricators and material suppliers. For example, neon gas faced shortages at the onset of the Russia-Ukraine war, threatening the stability of semiconductor production and causing high anxiety among chip fabs. At the time, it was unknown how much the US and Asia relied on Ukraine for neon supply. TECHCET managed to uncover various dependencies on Ukrainian neon from different regions around the world, helping major chip companies re-evaluate and better stabilize their supply chains. During the COVID pandemic, sporadic and extreme ocean freight roadblocks also contributed to slowdowns in chip manufacturing. In response to these disruptions, CMC subscriber companies met with logistics and shipping port officials to improve mitigation strategies for further supply interruptions.

CMC member subscribers also gain insight into supply chain challenges from the CMC Seminar. The next one will be hosted in Taiwan (October 25) and will focus on current problems in the materials supply chain and future quality requirements. This event is one of several that brings conversation on supply issues to the forefront. These events connect the entire semiconductor ecosystem by providing essential information on critical materials needed by decision makers at chip fabricators, suppliers, and government. The current CMC chip fab subscribers include more than a dozen of the world’s largest chip makers. (Reference: https://cmcfabs.org)

Given the massive impact semiconductors have in our digital global society, there is a growing and persistent need to manage the coming supply-chain issues, especially with expectations for chip volume to sharply ramp come 2025-2026. Looking into the future, TECHCET and the CMC will continue to facilitate coordination among key players in the materials and chip industry to navigate what lies ahead.

For more information on TECHCET: https://techcet.com or https://cmcfabs.org/2023-cmc-seminar/.

Lita Shon-Roy is President/CEO of TECHCET CA LLC, an advisory services firm expert in market analysis and business development of electronic markets and supply-chains for the semiconductor, display, solar/PV, and LED industries.

Sachi Brown is the Marketing Specialist of TECHCET CA LLC, in charge of marketing communications.

Forge Nano and KULR Partner for Cutting-Edge Battery Safety & Performance

In a significant move to enhance battery safety and efficiency, KULR Technology Group, a key player in sustainable energy management, has formed a strategic partnership with Forge Nano, renowned for its precision nanocoating technology. This alliance, estimated to be worth between $3.5 million to $5 million, will amalgamate KULR ONE Design Solutions - which offers advanced battery cell screening - with Forge Nano’s Atomic Layer Deposition (ALD) coating technique.

The collaboration begins with an assessment of Forge Nano’s elite battery cells intended for space and the US Department of Defense (DoD). KULR's innovative automated cell screening will be instrumental in gauging various battery cell parameters, ensuring they adhere to stringent NASA flight specifications.

In light of the recent announcement by the U.S. Department of Energy about a second tranche of $3 billion funding for battery production and recycling, this partnership positions itself as a catalyst in setting new benchmarks in battery safety and performance. 

Forge Nano, after securing $50 million earlier this year, has been aggressively investing in augmenting its battery production capacities. While KULR, with its expansive market presence in diverse sectors, sees this collaboration as a strategic alignment towards advancing the future of energy storage.

Source: Forge Nano and KULR Form a Strategic Partnership for Enhanced Battery Safety and Performance - Forge Nano

Unlocking the secrets of conformality, Characterization

Are you eager to learn more about 3D thin films Characterization in high aspect ratio structures and the tools essential for achieving this? The most insightful answers will be provided from high level experienced thin film characterization expert Dr. Jennifer S. Emara, the thin film characterization specialist at Fraunhofer IPMS and Dr. Jussi Kinnunen, the Optical measurement specialist at Chipmetrics.

Event Timing: Sept 28th, 2023. 5 pm CET (Europe), 8 am PST (USA)

Contact us at (+358417401098) or info@chipmetrics.com

TechInsights Discovers Micron's Cutting-Edge D1β LPDDR5 16 Gb DRAM Chips in Apple iPhone 15 Pro: Setting a New Standard in Memory Technology

TechInsights has confirmed Micron's cutting-edge D1β LPDDR5 16 Gb DRAM chips in the Apple iPhone 15 Pro, marking the industry's first venture into the D1β generation. These chips are smaller and denser than their predecessors, showcasing significant advancements in DRAM technology. Notably, Micron has achieved this without utilizing Extreme Ultraviolet Lithography (EUVL), a technique employed by competitors like Samsung and SK Hynix for their DRAM processes. This achievement highlights Micron's dedication to pushing the boundaries of DRAM technology, emphasizing innovation and efficiency in the tech landscape. Micron's groundbreaking D1β LPDDR5 16 Gb DRAM chip promises to reshape the future of memory technology, setting a new standard for the industry.

(Source Micron.com)

1-BETA includes cool stuff

High-k/Metal Gate

Micron's 1β fabrication process uses the company's 2nd generation high-K metal gate (HKMG) and is said to increase bit density of a 16Gb memory die by 35% as well as to improve power efficiency by 15% when compared to a similar DRAM device made on the company's 1α node

Pitch multiplication without the need for EUV Lithography

Micron's use of proprietary multi-patterning lithography involves advanced techniques for defining circuit patterns on semiconductor wafers with the highest precision. This approach allows Micron to create intricate patterns on the chips, achieving higher memory capacity in a smaller footprint. It enables the company to fit billions of memory cells on a chip that's roughly the size of a fingernail. 

While the semiconductor industry has been transitioning to extreme ultraviolet lithography (EUVL) to overcome technical challenges in patterning, Micron has opted for its multi-patterning lithography approach. This choice showcases Micron's expertise and innovation in lithography techniques, enabling them to continue shrinking circuit features and achieving greater memory capacity without relying on EUVL, which is still considered an emergent technology. 

By using proprietary multi-patterning lithography, Micron not only reduces the cost per bit of data but also enables devices with small form factors, such as smartphones and IoT devices, to incorporate more memory into compact spaces. This approach underscores Micron's commitment to staying at the forefront of memory technology innovation.

"While the industry has begun to shift to a new tool that uses extreme ultraviolet light to overcome these technical challenges, Micron has tapped into its proven leading-edge nano-manufacturing and lithography prowess to bypass this still emergent technology. Doing so involves applying the company’s proprietary, advanced multi-patterning techniques and immersion capabilities to pattern these minuscule features with the highest precision," Micron explains. Thy Tran, VP Process Integration, Micron

On the heels of the news that Micron has begun shipping QS-sample LPDDR5X components developed on the new 1-beta DRAM process node to its smartphone customers, host Jim Greene welcomes Thy Tran, Vice President of DRAM Process Integration, to the Chips Out Loud Podcast to discuss the emergent technology.

Sources:

Micron LPDDR5 16 Gb Non-EUVL Chip Found in Apple iPhone 15 Pro | TechInsights

LPDRAM | LPDDR | Micron Technology

Micron Ships World’s Most Advanced DRAM Technology With 1-Beta Node | Micron Technology

(Source: TechInsights.com)

Silicon Photonics: Illuminating the Future of High-Speed Data Centers and AI

Silicon photonics technology is fast becoming the linchpin in the quest to meet the soaring demands for data center bandwidth, with a particular focus on its application in artificial intelligence (AI) and machine learning (ML). This transformative technology leverages the power of photons to create efficient interconnections within data centers, a development recognized by experts at imec, a leading semiconductor research lab, as increasingly crucial.

In the imminent future, silicon photonics is set to revolutionize chip-to-chip connectivity among central processing units (CPUs), graphics processing units (GPUs), and other core computational elements at the heart of data centers and AI supercomputers. Despite formidable challenges in tightly integrating optics and electronics, the semiconductor industry is rising to the occasion, epitomized by the development of switch chips featuring co-packaged optics. imec envisions substantial enhancements in the power efficiency, bandwidth density, and cost-effectiveness of silicon photonics, potentially paving the way for advanced co-packaged optics, such as "wafer-level optical interconnects," capable of achieving near-light-speed data transfer between chips on printed circuit boards (PCBs) or within packages. 

Source: Silicon Photonics Will Shine in the Age of AI | Electronic Design

In summary, silicon photonics stands as a pivotal solution to address the burgeoning bandwidth requirements of data centers, with a particularly promising role in the realm of AI and ML applications. imec's concerted efforts in advancing this technology promise to shape the future of high-speed optical interconnect networks, ushering in an era of unprecedented computational capabilities.

NEO Semiconductor Unveils Revolutionary 3D NAND and DRAM Innovations at Flash Memory Summit 2023

NEO Semiconductor, known for its expertise in 3D NAND flash and DRAM technologies, presented groundbreaking innovations at Flash Memory Summit 2023 in August. The full presentation can be seen on Youtube (below). CEO Andy Hsu's keynote introduced their latest creation, 3D X-DRAM™, designed to overcome DRAM's capacity limitations and replace 2D DRAM. This technology utilizes the existing 3D NAND flash process with minor modifications, streamlining development and reducing costs. Hsu also unveiled a new AI application, "Local Computing," promising a substantial enhancement in AI chip performance.

X-DRAM™ significantly reduces data latency and provides ultra-high data throughput to unleash the full potential of High-Bandwidth Memory (HBM). HBM uses many Through Silicon Via (TSV) to increase I/O bandwidth. However, the HBM data latency remains almost the same when using conventional DRAM because bit line lengths remain the same.

Furthermore, NEO Semiconductor showcased various novel memory structures derived from 3D X-DRAM™, tailored for applications like 3D NOR flash memory, 3D Ferroelectric RAM (FFRAM), 3D Resistive RAM (RRAM), 3D Magnetoresistive RAM (MRAM), and 3D Phase Change Memory (PCM). These innovations enable the transition from 2D to 3D memory cells.

Hsu underscored the significance of these technologies for the semiconductor industry, cloud providers, and enterprises, highlighting that 3D X-DRAM™ offers a high-speed, high-density, cost-effective, and high-yield solution.

The presentation addressed the challenges faced by DRAM and NAND flash memory in the context of AI applications and introduced two innovative solutions – 3D X-DRAM™ and 3D X-NAND™.

Being part of the prestigious Flash Memory Summit, NEO Semiconductor showcased its technologies at booth number 215, and interested parties had the opportunity to schedule meetings with the company at the event.

In summary, NEO Semiconductor unveiled groundbreaking advancements in 3D NAND flash and DRAM technologies at Flash Memory Summit 2023, offering solutions to critical challenges in memory performance and capacity.

Source: NEO Semiconductor to Present Its Ground-Breaking 3D NAND and 3D DRAM Architectures in Keynote Address at Flash Memory Summit 2023 - Neo Semiconductor | X-Nand

Stockholm-Based GREEN14 Leads the Charge in Sustainable Silicon Production for Solar Industry

Stockholm-based GREEN14 is making strides in its mission to revolutionize solar-grade silicon production. Following a successful lab-scale feasibility study, the company is set to establish a pilot plant using a pioneering quartz reduction process with hydrogen plasma. Emissions are expected to decrease by 60% to 95%, aligning with the company's commitment to sustainability. The technoeconomic analysis suggests the pilot plant will be economically viable, potentially transforming the solar industry. The plant, scheduled to be commissioned at KTH, signifies GREEN14's dedication to academic collaboration and clean energy innovation. Founder Adam Podgorski anticipates a significant positive environmental impact.

Green 14 is pioneering a sustainable shift in silicon production methods, potentially revolutionizing the solar panel manufacturing industry. Their innovative approach, protected by a patented solution, seeks to redefine how silicon is extracted from quartz. Unlike the traditional reliance on coal, Green 14 utilizes green hydrogen, a cleaner energy source, to convert silicon dioxide into silicon. This transition significantly reduces energy consumption and replaces carbon dioxide emissions with water vapor, offering a more environmentally friendly alternative.

"This is what the initial design of a reactor producing the world's first kg/hour of green solar grade silicon looks like. When we succeed we will have silicon with up to 95 percent GHG reduction at a cost lower than the leading Chinese producers." Source Green14 LinkedIn.

Green 14's primary goal is to reduce the carbon footprint associated with solar panel production, addressing the inherent environmental challenges in the industry. In a world where fossil fuels dominate manufacturing processes, Green 14's commitment to eco-conscious innovation signifies a potential shift toward a greener future.

Their recent successful lab tests mark a promising step forward. However, their most significant project lies ahead—an ambitious eight-meter-high test reactor set to be constructed at the Department of Materials Science at KTH. This project aims to scale up production and transition from batch processing to a more efficient continuous manufacturing process. The ultimate objective is to produce high-purity silicon on a larger scale, potentially setting new industry standards.

While Green 14 maintains the confidentiality of their innovative technology, their use of hydrogen plasma as a reducing agent and operation at temperatures of 3,000 degrees Celsius underline their commitment to technological advancement. The hope is that this approach will not only prove cost-effective but also more energy-efficient and environmentally sustainable compared to prevalent manufacturing methods, which often rely heavily on fossil fuels and are largely concentrated in China.

The estimated cost of the pilot facility at 20 million Swedish kronor reflects Green 14's earnest endeavor to introduce this transformative technology. Pending grant approvals from the Swedish Energy Agency and Vinnova, Green 14 is poised to make a significant impact on the future of solar panel manufacturing. The pilot facility, expected to commence operations soon, signifies a pivotal step toward a more sustainable and cleaner energy future.

About GREEN14

GREEN14 is a pioneering technology company committed to developing innovative solutions for a sustainable future. With a focus on renewable energy, GREEN14 is revolutionizing the production of solar grade silicon through its groundbreaking quartz reduction process. By combining cutting-edge technology with a commitment to environmental stewardship, GREEN14 is driving the transition to a low-carbon economy and paving the way for a cleaner, brighter future.

Sources:
General 2 — Green14
Green 14 vill tillverka grönt kisel för solceller – bygger testreaktor på KTH (nyteknik.se)

Kokusai Electric's Upcoming IPO: A Strategic Move in the Booming Semiconductor Market

Kokusai Electric is set to go public on the Tokyo Stock Exchange on October 25th, with an indicative share price of 1,890 yen per share. The IPO aims to raise 111.2 billion yen ($749.88 million) to fund research investment in the chipmaking equipment market. This move also serves as a partial exit for KKR, which previously purchased Hitachi's electronic equipment unit in 2017 and later spun off Kokusai.

In 2019, KKR attempted to sell Kokusai to Applied Materials for $3.5 billion, but the deal fell through due to regulatory hurdles in China. Applied Materials subsequently acquired a 15% shareholding in Kokusai. Kokusai Electric specializes in semiconductor manufacturing equipment, particularly in Atomic Layer Deposition (ALD) technology, with a strong market position, including a 23% share of the global ALD equipment market in 2020.

Kokusai Electric's ALD equipment portfolio includes products like TSURUGI-C²® for 300mm wafers and VERTRON® Revolution for 200mm wafers, known for their high performance and productivity. The company's main customers for ALD equipment include Samsung, SK Hynix, Micron, and Intel. Kokusai Electric's IPO is scheduled for September 23, 2023.

ASML's 2023 Outlook: Surging Ahead in Semiconductor Equipment Despite Challenges and Export Controls

In 2023, ASML, the leading semiconductor lithography equipment supplier, is set to achieve remarkable success, outpacing its rivals and emerging as the number 1 provider of Wafer Fabrication Equipment. Boasting an impressive 30% revenue growth forecast for the year, ASML is thriving amidst an industry landscape marked by its consistent performance. With a substantial backlog of cutting-edge Deep Ultraviolet (DUV) and Extreme Ultraviolet (EUV) systems and surging demand from China, ASML's growth continues despite hurdles like supply chain disruptions and regulatory changes, ASML remains a beacon of innovation and resilience in the semiconductor sector.

By Abhishek Kumar Thakur and Jonas Sundqvist

ASML, a leading supplier of semiconductor equipment, is poised for a significant year in 2023, projected to surpass Applied Materials (AMAT) as the top provider of Wafer Fabrication Equipment. This achievement is attributed to ASML's robust revenue growth, expected to reach a remarkable 30% increase in 2023, while Applied Materials faces a decline of 20% according to Seeking Alpha*. ASML's success can be attributed to a substantial backlog of Deep Ultraviolet (DUV) and Extreme Ultraviolet (EUV) systems, driven by heightened demand in China.

* Fact check: Due to strong DUV revenue and despite the increased uncertainties, ASML expects strong growth for 2023 with a net sales increase towards 30% and a slight improvement in gross margin, relative to 2022. ASML Holding revenue for the twelve months ending June 30, 2023 was $27.293B, a 25.97% increase year-over-year. AMAT revenue is estimated to increase by 2.6% to 26.33 B. Meaning ASML would pass bu end of 2023.

https://finance.yahoo.com/quote/AMAT/analysis/ 

Despite facing challenges like supply chain disruptions and a factory fire, ASML has consistently ranked among the top three semiconductor equipment suppliers since 2017. Their backlog of EUV systems, combined with growing acceptance of DUV tools, contributes to their strong performance.

However, potential headwinds include supply chain concerns, past issues like the Berlin factory fire, and looming sanctions affecting exports to China. While ASML has addressed some challenges, the possibility of US sanctions in 2024 poses a threat to its growth.

Furthermore, ASML now faces new export controls imposed by the Netherlands, impacting shipments to China. While the company downplays these controls' immediate financial impact, they are expected to affect specific DUV systems, adding to global efforts to limit China's semiconductor advancements.

In this volatile landscape, ASML's ability to adapt to evolving regulations and maintain its technological leadership will be crucial. The impact of these restrictions, especially on shipments to China, could influence the company's growth trajectory in the semiconductor industry. Despite these challenges, ASML remains a prominent player with significant potential in the semiconductor equipment market.

ASML is set to deliver the industry's first High-NA extreme ultraviolet (EUV) lithography scanner by the end of 2023, marking a significant development for advanced chip manufacturing. The Twinscan EXE:5000 pilot scanner with a 0.55 numerical aperture (NA) will enable chipmakers to explore High-NA EUV technology. This innovation is crucial for achieving an 8nm resolution, suitable for manufacturing technologies beyond 5nm nodes. Intel is expected to be the first customer, but integration and adoption details are still uncertain. This advancement requires substantial investments, with reports suggesting costs of $300-400 million per unit.

To add some colour, initially, Intel had plans to employ ASML's High-NA tools for its 18A (1.8 nm) production node, scheduled for high-volume manufacturing in 2025, aligning with ASML's Twinscan EXE:5200 delivery. However, Intel accelerated its 18A production, moving it to the latter part of 2024. This change in strategy involved the use of ASML's Twinscan NXE:3600D/3800E with two exposures and Applied Material's Endura Sculpta pattern-shaping system. The objective was to reduce reliance on EUV double patterning techniques. Applied Materials' Centura Sculpta is a pattern-shaping machine equipped with a unique algorithm that can manipulate patterns produced by an EUV scanner. It has the capability to stretch these patterns in a user-defined direction along the X-axis. This process effectively reduces the space between features and enhances pattern density. This means that moving ahead ASML and Applied Materials are entering an interesting competitive space previously not encountered.

ASMLs Products

As an background, ASML specializes in the production of cutting-edge lithography systems crucial for semiconductor manufacturing. Their product portfolio includes the following key offerings:

Extreme Ultraviolet (EUV) Lithography Machines: ASML's EUV lithography machines are at the forefront of semiconductor manufacturing technology. These machines use extremely short wavelengths of light to create intricate patterns on silicon wafers, enabling the production of advanced and smaller semiconductor chips. EUV technology is essential for next-generation processors and memory chips.

Deep Ultraviolet (DUV) Lithography Machines: DUV lithography systems are another vital component of ASML's product lineup. They use longer wavelengths of light compared to EUV and are employed for a wide range of semiconductor applications, including memory and logic chip production. ASML's DUV systems are known for their precision and reliability.

TWINSCAN Series: Within the DUV lithography category, ASML offers the TWINSCAN series, which includes machines like the TWINSCAN NXT:2000i, NXT:2050i, and NXT:2100i. These systems are designed for immersion lithography, where the wafer and the lens are submerged in a liquid, enhancing precision and resolution.

EUV High Numerical Aperture (NA) Systems: ASML has been advancing its lithography machines by increasing the numerical aperture (NA), a key parameter that affects resolution. High-NA systems are capable of printing even smaller features on semiconductor wafers, enabling the production of highly advanced chips.

ASML's lithography machines are considered critical infrastructure for semiconductor manufacturing, and the company's technological leadership in this area has positioned it as a dominant player in the industry. The company's ability to innovate and adapt its lithography systems to meet the ever-increasing demands of semiconductor manufacturers has been a key factor in its success and growth prospects. However, the recent export controls and geopolitical pressures, particularly concerning shipments to China, introduce additional challenges and uncertainties for ASML and its specialized products.

Sources:

ASML Hit With New Dutch Limits on Chip Gear Exports to China - Bloomberg

ASML To Top WFE Semiconductor Equipment In 2023, Topping Applied Materials | Seeking Alpha

ASML to ship first pilot tool in its next product line in 2023, CEO says | Reuters

ASML to Deliver First High-NA EUV Tool This Year (anandtech.com)

EUV Alternative Speeds Up Chip Production - EE Times

BALD Engineering - Born in Finland, Born to ALD: ASML Remains on Track to Deliver High NA EUV Machines in 2023

BALD Engineering - Born in Finland, Born to ALD: Netherlands' chip tool export controls take effect for DUV Lithography and ALD

BALD Engineering - Born in Finland, Born to ALD: Applied Materials’ Pattern-Shaping Technology - Centura Sculpta

Linköping University Researchers Uncover Challenges in Thermal ALD of Indium Nitride (InN)

Researchers from the Pedersen Group at Linköping University have investigated the limitations of thermal atomic layer deposition (ALD) for indium nitride (InN). Using quantum-chemical density functional theory calculations, they explored the adsorption process of ammonia (NH3) on InN and compared it to gallium nitride (GaN), shedding light on the challenges in InN deposition.

InN holds promise in semiconductor and electronics applications due to its distinctive properties. It boasts a high electron mobility, exceeding that of many other III-nitride materials, rendering it suitable for high-frequency electronic devices like transistors and amplifiers. With a narrow bandgap of around 0.7 eV, InN finds applications in infrared photodetectors and optoelectronic devices. Despite challenges in thermal stability during deposition, it exhibits good stability when appropriately processed, making it valuable in high-temperature electronics. Its high electron velocity enhances the performance of high-speed field-effect transistors. InN also shows potential in energy-efficient electronics and gas sensing applications, furthering its significance in the semiconductor and electronics industry.

The deposition of indium nitride (InN) using CVD is challenging due to its low thermal stability, which limits the use of high-temperature processes. ALD is an alternative method that can operate at lower temperatures. While ALD has been successful in depositing materials like aluminum nitride and gallium nitride (GaN) using ammonia as a nitrogen precursor in thermal processes, InN can only be deposited using plasma ALD. This suggests a limitation to thermal ALD with ammonia for InN.

Gibbs free energy profile for the adsorption of NH3 onto InN and GaN at 500 (a) and 800 K (b).

Researchers used quantum-chemical density functional theory calculations to investigate the adsorption process of ammonia (NH3) on both GaN and InN surfaces. They aimed to understand if differences in this process could explain why thermal ALD of InN is challenging. Their findings revealed a similar reactive adsorption mechanism on both materials, where NH3 adsorbs onto vacant sites created by the desorption of methyl groups from the surfaces. However, the energy barrier for this adsorption process was significantly higher on InN compared to GaN, indicating that the process is much slower on InN.

This slow kinetics would hinder NH3 from effectively adsorbing onto InN during the ALD growth process, making thermal ALD with InN using NH3 impractical. As a result, the only alternative to a fully thermal ALD process for InN appears to be using a different precursor system due to InN's thermal instability.

Source: On the limitations of thermal atomic layer deposition of InN using ammonia | Journal of Vacuum Science & Technology A | AIP Publishing

Plasma-Therm Strengthens Power Electronics Presence with Acquisition of Thin Film Equipment SrL

Plasma-Therm, a prominent manufacturer of plasma-process equipment for the semiconductor industry, has announced its acquisition of Thin Film Equipment SrL (TFE) on September 18, 2023. TFE, based in Binasco, Italy, specializes in supplying sputtering equipment for semiconductor research and production, particularly in physical vapor deposition (PVD) sputtering and evaporation process equipment and high purity materials for thin film applications.

This acquisition is part of Plasma-Therm's strategy to expand its presence in Europe and strengthen its position in the power device market. TFE's suite of PVD tools, catering to MEMS, Power, RFID, and other semiconductor applications, complements Plasma-Therm's existing product portfolio in etch and deposition. Additionally, TFE's expertise in PVD technology enhances Plasma-Therm's customer service and support capabilities.

The power semiconductor market is expected to grow substantially, reaching $6.3 billion by 2027, according to The Yole Group's "Power SiC 2022" report. Plasma-Therm is well-positioned to support this growth with the acquisition of TFE and its MRC Eclipse product line.

TFE will continue to operate independently but will collaborate closely with Plasma-Therm to offer a more comprehensive range of plasma and PVD process technology solutions to customers. This acquisition will also enable both companies to expand their R&D resources and global customer service and support teams.

Plasma-Therm is a global manufacturer of advanced plasma processing equipment, serving various industries, including wireless, power devices, MEMS, photonics, advanced packaging, and data storage. It has locations in North America, Europe, and Asia-Pacific.

TFE SrL, founded in 1996, is a leading supplier of sputtering equipment for R&D and production, known for its flexibility, reliability, process knowledge, and a large worldwide installed base.

Source: Plasma-Therm Announces Acquisition of Thin Film Equipment (globenewswire.com)

Aixtron’s G10-SiC CVD System Supports GlobiTech’s SiC Epitaxy Expansion

• GlobiTech Inc produces silicon carbide (SiC) and silicon epitaxial wafers, primarily focusing on serving the power and electric vehicle (EV) market segments.
• GlobiTech Inc's production facilities are located in Sherman, Texas, USA.

Aixtron SE is aiding Texas-based silicon-epitaxy foundry GlobiTech Inc's entry into the silicon carbide (SiC) epitaxy market. The G10-SiC chemical vapor deposition (CVD) system from Aixtron has enabled GlobiTech to rapidly scale SiC epitaxy production in response to growing demand for power epiwafers. Featuring dual wafer sizes (9x150mm and 6x200mm), it offers high throughput per fab space. GlobiTech's expansion confirms the trend of SiC replacing silicon in various applications. Both firms have enjoyed a fruitful partnership, with Aixtron's tools maximizing wafer output. The G10-SiC is projected to be Aixtron's top-selling product in 2023.

Aixtron G10-SiC (Source Aixtron.com)

Source: AIXTRON Pressemeldungen :: AIXTRON

Recent Blog posts on SiC:

BALD Engineering - Born in Finland, Born to ALD: SiC Market Soars Towards $9 Billion: EVs and High-Power Chargers Drive Growth

BALD Engineering - Born in Finland, Born to ALD: SiC Market Soars Towards $9 Billion: EVs and High-Power Chargers Drive Growth

BALD Engineering - Born in Finland, Born to ALD: Samco launches new ICP Tornado Plasma ALD system

BALD Engineering - Born in Finland, Born to ALD: ASM International has completed the acquisition of Italian Silicon Carbide Equipment Manufacturer LPE S.p.A.

BALD Engineering - Born in Finland, Born to ALD: Chemistry paves the way for improved electronic materials - LiU have developed a new molecule that can be used to create high-quality indium nitride

Background:

• Silicon carbide: from gold rush to commodity?¹, which provides an overview of the global SiC market and its predictions for the future of the technology. It discusses the growth rate, size, and drivers of the SiC device market, as well as the competitive landscape and supply chain of the SiC industry. It also analyzes the challenges and opportunities for SiC technology in different applications, such as automotive, industrial, energy, and telecommunications. It also compares and evaluates SiC with other wide bandgap materials, such as gallium nitride (GaN) and diamond.
• The 2023 global fab landscape: opportunities and obstacles², which considers the state of the global semiconductor fab market in a post-COVID world. It discusses the emerging business models that could enable the semiconductor industry to migrate to leading-edge and mature technology with optimal manufacturing capacity. It also examines the impact of COVID-19, trade wars, and geopolitical tensions on the semiconductor supply chain and fab investments. It also explores the trends and innovations in semiconductor materials, devices, and modules, such as silicon carbide (SiC), gallium nitride (GaN), and quantum computing.

AIXTRON's MOCVD Machine Advancing 2D-Materials at imec

AIXTRON, a German semiconductor equipment manufacturer, has successfully installed the CCS 2D Metal-Organic Chemical Vapour Deposition (MOCVD) reactor at the Interuniversitair Micro-Electronica Centrum (imec) in Belgium. Part of the 2D Experimental Pilot Line initiative, this reactor facilitates large-scale epitaxial deposition of 2D-materials on 200/300 mm wafers, marking a significant milestone in the transition of these materials from lab to fab.

Inge Asselberghs, Director of the 2D Experimental Pilot Line at imec, emphasizes the unique position of imec as a bridge between academia and industry, offering access to both fundamental research laboratories and industrial infrastructure.

Salim El Kazzi, 2D Product Manager at AIXTRON, outlines the challenges of the lab-to-fab transition, including miscommunication and the technical intricacies of 2D-materials. AIXTRON addresses these challenges by fostering collaboration among top researchers and providing FAB-compatible reactors like the CCS 2D.

To bridge the gap effectively, Asselberghs highlights the importance of versatile tools for rapid material and process screening, crucial for seamless information exchange between industry and academia.

The CCS 2D MOCVD machine from AIXTRON offers precise control over deposition parameters and features like closed-coupled shower heads and a transfer module for 2D-material growth on 300 mm wafers.

This installation promises exciting prospects for imec's research on transition metal dichalcogenides (TMDCs) and advances in pilot-line processes for 2D-material growth and layer transfer. Both AIXTRON and imec actively participate in Graphene Week 2023, contributing to the advancement of 2D-materials in industrial applications and strengthening the link between academia and industry.

Source: AIXTRON installs a MOCVD machine CCS 2D in IMEC’s fab | Graphene Flagship (graphene-flagship.eu)

Tokyo Electron Integrated Report/Annual Report 2023 available for download

Tokyo Electron (TEL) issues an integrated report for the purpose of reporting our medium- to long-term profit expansion and continuous corporate value enhancement to their stakeholders.

As they celebrate their 60th anniversary this year, the 2023 report looks back at the history of our business expansion. It also details our efforts to continuously create value by the value chain of their business activities anchored around material issues, in conjunction with their sustainability initiatives.

For anyone involved in the semiconductor industry or those eager to gain fresh perspectives in this dynamic field, this report is a must-read. It not only showcases TEL's history and strategies but also sheds light on industry trends, sustainability practices, and the exciting developments shaping the future of semiconductor technology. Dive into this comprehensive report and unlock valuable knowledge about TEL's journey and the semiconductor industry at large.

Integrated Report/Annual Report | Investor Relations | Tokyo Electron Ltd. (tel.com)

TEL also have great training material and a Nanotech Museum:

Learn about semiconductors | Tokyo Electron Ltd. (tel.com)

nanotec museum (tel.com)

Global Fab Equipment Spending to Rebound in 2024 After 2023 Slowdown, Predicts SEMI Report

Global fab equipment spending is anticipated to decline by 15% in 2023, dropping to $84 billion from the record high of $99.5 billion in 2022. However, a recovery of 15% to $97 billion is expected in 2024, driven by the end of a semiconductor inventory correction in 2023 and increased demand in high-performance computing (HPC) and memory segments. The foundry segment will lead the industry's expansion in 2023 with $49 billion in investments, while memory spending is set to make a strong comeback in 2024 with a 65% increase to $27 billion. 

Taiwan will remain the top region for fab equipment spending in 2024, with $23 billion, followed by Korea with $22 billion, and China in third place at $20 billion. The Americas and Europe/Mideast regions are also expected to see increased investments, while capacity growth in the global semiconductor industry is forecasted to continue, rising by 6% in 2024.

Source: 2024 Global Fab Equipment Spending Recovery Expected After 2023 Slowdown, SEMI Reports | SEMI

Intel to Sell 10% Stake in IMS Nanofabrication to TSMC for $4.3 Billion

Intel will sell a 10% stake in IMS Nanofabrication to TSMC, valuing IMS at $4.3 billion, maintaining Intel's majority ownership. IMS leads in multi-beam mask writing tools for advanced extreme ultraviolet lithography, crucial for AI and mobile applications. This investment enhances IMS' independence and fosters innovation, including high-numerical-aperture EUV technology. The deal is set to close in Q4 2023. IMS is vital for semiconductor industry growth, with the market projected to reach $1 trillion by 2030. Intel acquired IMS in 2015 and sold a 20% stake to Bain Capital earlier in 2023, while TSMC's partnership with IMS dates back to 2012.

About IMS Nanofabrication

IMS Nanofabrication Global, LLC, a majority-owned subsidiary of Intel Corporation, is the global technology leader for multi-beam mask writers. Its customers are the largest chip manufacturers in the world, who rely on its technology to produce current and future chip generations. IMS’ innovative multi-beam writers play a key role in chip manufacturing and provide significant added value to the semiconductor industry. They are continually customized and refined by an interdisciplinary team, in line with the latest market demands. Over the last 10 years, IMS has perfected its electron-based multi-beam technology. The first-generation multi-beam mask writer, MBMW-101, is successfully operating all over the world. The second-generation multi-beam mask writer, MBMW-201, entered the mask writer market in the first quarter of 2019 for the 5nm technology node. And this year, IMS is launching MBMW-301, a fourth-generation multi-beam mask writer that delivers unprecedented performance. Learn more at www.ims.co.at/en/.

Exploring SMIC's 7nm Semiconductor Advancements: Technology, Dimensions, and Future Prospects

The recent introduction of Huawei's Mate 60 Pro smartphone, featuring a 7 nm chip from Semiconductor Manufacturing International Corp. (SMIC), has raised questions about the authenticity of SMIC's technological strides and their implications. This summary dives into the heart of SMIC's 7 nm technology, shedding light on its dimensions, technological intricacies, challenges, and the outlook for the future.

However, it has been known for some time that SMIC has been developing at putting out 7 nm chips, and an early 2022 assessment published at Seeking Alpha can be found here: Applied Materials: SMIC Move To 7nm Node Capability Another Headwind (NASDAQ:AMAT) | Seeking Alpha

The SMIC 7 nm Technology Debate

Central to the debate surrounding SMIC's technology is the classification of whether it genuinely qualifies as 7 nm. Parameters such as Fin Pitch (FP), Contacted Poly Pitch (CPP), and Metal 2 Pitch (M2P) are scrutinized. While SMIC's FP pitches are larger than TSMC's 10 nm, its CPP and M2P dimensions match TSMC's 10 nm, creating a complex classification.

SMIC appears to have a serviceable first generation 7nm process now with a reasonable prospect to get to second generation 7nm/6nm in the near futures. 5nm and 3nm while theoretically possible would be highly constrained and expensive process versions if pursued due to the lack of EUV. - Scotten Jones, SemiWiki (LINK)

Design Technology Co-Optimization (DTCO) Features

SMIC's 7 nm process introduces Design Technology Co-Optimization (DTCO) features uncommon in traditional 10 nm processes. Notably, SMIC's track height is smaller than TSMC and Samsung's 10 nm processes, approaching 7 nm-class characteristics. These features add to the nuanced evaluation of SMIC's technological position.

Cell Density and Cut Masks

SMIC's high-density logic cell boasts an impressive 89 million transistors per millimeter squared, akin to Samsung and TSMC's first-generation 7 nm processes. This suggests that SMIC's technology aligns with the 7 nm category, though the debate on its dimensions continues. Notably, SMIC's process introduces larger Contacted Poly Pitch (CPP) dimensions, hinting at potential performance challenges that necessitated this adjustment.

The EUV Challenge and Future Prospects and Alternative Technologies

SMIC's journey toward further technological advancements faces significant hurdles due to the unavailability of extreme ultraviolet lithography (EUV) systems in China. EUV technology plays a pivotal role in pushing semiconductor boundaries. However, ongoing US restrictions on EUV system shipments to China constrain SMIC's options for achieving cutting-edge technology.

Self aligned multi patterning (SAMP) in Advanced Logic Semiconductor Manufacturing

In advanced logic semiconductor manufacturing, addressing the challenges posed by sub-5 nm nodes and dense metal layers is essential. SMIC can consider alternative technologies like Atomic Layer Deposition (ALD) and Directed Self-Assembly (DSA) to overcome these hurdles.

ALD stands out for its precision in depositing thin films, allowing for the creation of ultra-thin etch masks, spacers, and precise control over critical dimensions. On the other hand, DSA leverages materials' self-assembly properties to form predefined patterns, effectively dividing pitch sizes and simplifying lithography masks.

Incorporating ALD and DSA into semiconductor manufacturing processes has the potential to enhance the capabilities of immersion lithography, enabling smaller nodes without the need for EUV lithography. While these technologies require further research and development, they offer promise in helping semiconductor manufacturers advance their technology and remain competitive, particularly in the absence of EUV lithography equipment.

Together with self-aligned multi-patterning (SAMP) techniques like self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), and self-aligned litho-etch-litho-etch (SALELE), these alternative approaches provide SMIC with a range of options to navigate the complexities of advanced semiconductor manufacturing, ultimately shaping the future of Chinese advanced chip fabrication.

The Future of Nanoimprint Lithography: High-Volume Production Possibilities

Nanoimprint lithography (NIL) offers potential for high-volume production with sub-10 nm resolution, revolutionizing semiconductor manufacturing. TEL and Canon have showcased NIL's sub-10 nm capabilities, making it suitable for multiple memory generations using a single mask. Challenges like edge placement errors (EPE) are addressed through precision techniques like Quasi-Atomic Layer Etch (Quasi-ALE). To achieve aggressive scaling targets, overlay accuracy and critical dimension uniformity (CDU) management are vital. NIL's simplicity and cost-effectiveness make it a promising contender, with ongoing development poised to refine its integration into semiconductor fabrication.

Future Outlook for SMIC and China

SMIC's path forward may involve alternative fabrication technologies such as ALD, DSA, and NIL. that offers the potential for high-volume production with sub-10 nm resolution.

By mastering and integrating these advanced technologies into semiconductor manufacturing could potentially expand immersion lithography's capabilities, accommodating smaller nodes without depending on EUV lithography. While further research and development are essential, these technologies offer potential pathways for SMIC to advance its fabrication processes and sustain competitiveness, particularly in the absence of EUV lithography equipment. These strategies, alongside self-aligned multi-patterning techniques, stand to influence the future of advanced chip fabrication in China beyond 7 nm. 

The answer is as always - it depends. For how long will China have access to also Immersion Lithography? Will top tier OEMs be allowed to continue to export ALD and other process technology needed to China? What will be the cost using higher complexity and additional masks needed for SAQP (cut masks)? Is Huawei's limited chip demand, as compared to Apple & Co, enough to pay for the R&D needed? Will Chinese state support cover the development and fab expansion cost? 

Sources:

193i Lithography Takes Center Stage...Again (semiengineering.com)

Does SMIC have 7nm and if so, what does it mean - SemiWiki

Look Inside Huawei Mate 60 Pro Phone Powered by Made-in-China Chip - Bloomberg

BALD Engineering - Born in Finland, Born to ALD: The Future of Nanoimprint Lithography: Exploring Possibilities and Challenges for High-Volume Production

BALD Engineering - Born in Finland, Born to ALD: Comparison confirms that SMIC reaches 7nm without access to western equipment & technologies

Applied Materials: SMIC Move To 7nm Node Capability Another Headwind (NASDAQ:AMAT) | Seeking Alpha