ALD to take over more and more as CVD and spin-on processes no longer are viable for 3D NAND

EE Times reports [LINK] about the recently announced Striker FE from Lam Research, an enhanced atomic layer deposition (ALD) platform addresses semiconductor manufacturing challenges for 3D NAND as well as DRAM. It employs advanced dielectric gapfill technology the company has dubbed “ICEFill” for filling 3D NAND and DRAM structures — as well as logic devices — in emerging nodes. 

Lam Research’s recently announced Striker FE enhanced atomic layer deposition (ALD) platform addresses semiconductor manufacturing challenges for 3D NAND as well as DRAM

Lam Research Striker FE - Key applications (LINK):

• Gapfill dielectrics
• Conformal liners
• Patterning spacers and masks
• Hermetic encapsulation
• Etch stop layers
• Optical films

The need for gapfill methods isn’t new, said Aaron Fellis, vice president and general manager of Dielectric ALD products, but the traditional ones no longer meet today’s needs, especially as 3D NAND is stacked higher. “They’re so tall and they have a number of different features that get etched through them to enable the integration of different steps,” he said. “Ultimately, they need to get filled back up with a dielectric material, most commonly silicon oxide.”

Legacy techniques, such as chemical vapor deposition, diffusion/furnace, and spin-on processes that are normally used as gapfill for semiconductor manufacturing are no longer viable for 3D NAND, Fellis said, due to trade-offs between quality, shrinkage, and gapfill voids. “They tend to shrink and distort the actual structure that the customer is building and designing.”

According to Risto Puhakka, president of VLSIresearch, Lam Research is a dominant player for ALD technology, and the demands of its technology reflect those placed on memory. It’s all about increasing density for applications, such as artificial intelligence, that require more bits while keeping costs the same, and that includes gapfill capabilities as the memories such as 3D NAND are stacked higher, he said. “The stacking becomes more and more challenging from the manufacturing perspective, but the chip makers themselves get it a little bit little anxious about how much they have to spend.” Sticking with a known material such as silicon oxide adds some predictability because it’s well understood

But just as 3D NAND stacking will eventually hit limits, so will the gapfill techniques and ALD technology, added Puhakka. “It has its own roadmap and limitations.”

TechInsights Webinar: ALD/ALE Process in Commercially Available Memory Devices

2018 saw memory product manufacturers Samsung, Hynix, Toshiba and Micron introducing 64- or 72- stacked layer 3D-NAND devices, and move into 1x generation DRAM devices.

This presentation will examine some of the different structures we have seen through the evolution of these technologies, in particular the latest 3D-NAND and DRAM parts. We will also look at several historical applications of ALD/ALE technology that have been observed through reverse engineering. We will highlight the importance of ALD/ALE process in advanced logic devices. In many cases, the technology could not have advanced without the implementation of ALD technology.

Information and registration: LINK

Process Power: The New Lithography - Advanced Energy

Here is a very insightful article by PETER GILLESPIE, VP & GM, Semiconductor Products, Advanced Energy Industries on the progress of Plasma RF Generators and Matching Networks. The article looks at applications in 3DNAND High Aspect Ratio Contacts (HARC) and Logic FinFET transitor fabrication using reactive ion etching and plasma CVD using the latest plasma technology. This is a an articel in a series of three in SEMICONDUCTOR DIGEST entitled “Process Power Steps Out from the Shadows,” looking at the leading edge technology node process challenges to highlight key drivers that are fundamentally transforming the role and importance of process power. 

Process Power: The New Lithography (SEMICONDUCTOR DIGEST, LINK) 

 

"Evolution of RF power supplies (plasma generators) and RF matching networks. Today’s RF power delivery systems are highly sophisticated with frequency tuning, complex pulsing regimes, and agile micro-second response." (Below)

 

 

TechInsights’ Memory Process: 3D NAND Word Line Pad webinar

TechInsights’ ‘Memory Process: 3D NAND Word Line Pad‘ #webinar compares 9x-layer 3D NAND devices from major manufacturers and discusses the process sequence with emphasis on the word line pad (WLP). Watch on demand here LINK 

 

Screendump from Webinar

Choppy Waters for Shipping $50B of Semiconductor Materials in 2020

Risky Sailing on the Global Supply-Chain Seas

San Diego, CA, Apr 17, 2020:TECHCET announces that:

 

• 2020 global material revenues in semiconductor manufacturing forecasted to decline by 3.0% year-over-year (YoY) despite growth in 1Q2020,
• Impact of COVID-19 pandemic on the global economy is creating choppy waters for shipping and supplying critical materials, as highlighted in recent Critical Materials Council (CMC) monthly meetings, and
• With a return of global economic growth by 2021, compound annual growth rate (CAGR) through 2025 is forecast at 3.5% as shown in the Figure (below).
 

 

“From our market research, materials suppliers are increasing production and sales to ensure safety-stock throughout the supply-chain in case there are further disruptions due to COVID-19 cases,” remarked Lita Shon-Roy, TECHCET President and CEO. “Even without further disruptions, we can already see leading economic indicators such as unemployment levels, metal prices and container shipping indices point toward a significant decline in global GDP.” This is supported by the International Monetary Fund’s (IMF’s) current outlook on 2020.

Currently, almost all chip fabs appear to be running at normal levels, with a few exceptions. During this difficult period, YMTC in Wuhan, China reportedly has maintained R&D and grown production of 3D-NAND chips. However, chip fabs in Malaysia report that the government required companies to request permission to continue operating at 50% staffing levels. One company in France had to temporarily reduce production due to their labor union insisting on temporary workforce reductions.

Significant value-added engineered materials including specialty gases, deposition precursors, wet chemicals, chemical-mechanical planarization (CMP) slurries & pads, silicon wafers, PVD/sputtering targets, and photoresists & ancillary materials for lithography are reporting healthy orders and in some cases will see better than expected revenues for 1Q2020 and April 2020. However, more than 60% of all materials are expected to be negatively impacted before year-end.

Overall demand for commodity materials, such as silane and phosphoric acid, is expected to decline YoY in 2020 by an average of 3% due to softening of the global economy. Average selling prices (ASP) for electronic-grade commodities may drop due to cost reductions in feed-stocks; for example, the global helium (He) gas market which had been forecasted to be in shortage with high ASPs throughout 2020 has already improved due to COVID-19 slowing down helium demand.

DRAM, 3D-NAND, and MPU chips for server / cloud-computing applications are now in high demand for virtual meetings and remote work. It is yet unclear how much of an increase in materials shipments will be needed to support this segment, however from TECHCET’s modeling of prior cycles it will likely be >7%. Despite such an increase in the materials used to make leading-edge ICs to build out data centers, shipments in support of legacy node IC fabrication are expected to decline this year.

Consequently, cloud-computing growth may not compensate for overall reduced semiconductor materials demands caused by economic downturns this year. By 2021 the global economy and all chip fabs should return to healthier growth, with materials markets for all IC devices expected to increase at a CAGR of +3.5% through 2025.

Critical Materials Reports™ and Market Briefings: TECHCET Shop
CMC Events: Click here to view all Events

Lam Research Adds Global Wafer Stress Management Solutions to Portfolio to 3D NAND Scaling

FREMONT, Calif., Aug. 07, 2019 (GLOBE NEWSWIRE) — Lam Research Corp. (Nasdaq: LRCX) today announced new solutions to help customers increase chip memory density, which is needed for applications such as artificial intelligence and machine learning. With the introduction of VECTOR® DT for backside deposition and EOS® GS wet etch for film removal on backside and bevel, Lam continues the expansion of its stress management product portfolio.

While high aspect ratio deposition and etching are key enablers for 3D NAND scaling, the combination of increasing the number of layers while controlling wafer bow due to cumulative stress in the film stack has become a major challenge. Such stress-induced wafer distortion has a significant impact on wafer yield due to degraded lithography depth-of-focus, overlay performance, and structural distortion. To improve overall yield, wafer-, die-, and feature-level stresses need to be carefully managed at various steps throughout the entire manufacturing process flow, at times potentially resulting in the preclusion of otherwise performance-enhancing process steps due to their stress characteristics.

Designed to provide a cost-effective solution for controlling wafer bow in 3D NAND manufacturing, the VECTOR DT system is the newest addition to Lam’s plasma-enhanced chemical vapor deposition (PECVD) product family. VECTOR DT provides a single-step solution for wafer shape management by depositing a tunable counter-stress film on the back of the wafer without contacting the front side, thereby enabling improved lithography results, reduced bow-induced failures, and integration of high performance but highly stressed films. With strong customer adoption since its debut, the VECTOR DT installed base continues to grow as customers are transitioning to more than 96 layers.

In addition to depositing a counter stress film, Lam provides the flexibility to remove backside films, allowing customers to adjust wafer stress during the 3D NAND manufacturing flow. Lam’s EOS GS wet etch product complements the VECTOR DT by simultaneously removing backside and bevel films with industry-leading wet etch uniformity, while fully protecting the wafer front side. As part of a comprehensive wafer bow management solution, Lam’s EOS GS has also been adopted by memory manufacturers worldwide.

“As our customers continue to dramatically increase the number of memory cell layers, the cumulative stress and wafer bow can exceed the limits of a lithography tool. Minimizing stress-induced distortion is critical for achieving the desired yield and enabling the cost-per-bit roadmap,” said Sesha Varadarajan, senior vice president and general manager of the deposition product group at Lam Research. “With the addition of the VECTOR DT and EOS GS systems, we are expanding our stress management solutions portfolio for managing global stress in support of our customers’ vertical scaling roadmap.”

Source: Lam Research LINK

---------------------
By Abhishekkumar Thakur

Applied Materials to buy Japan's Kokusai to boost memory chip business and ALD

Here are more details and analyst responses on the Applied Materials Kokusai purchase and my own thoughts at the end:

(Reuters, LINK) - U.S. chip gear maker Applied Materials Inc (AMAT.O) on Monday agreed to buy Japanese peer Kokusai Electric for $2.2 billion from KKR & Co Inc (KKR.N), as it bets on rising demand for memory chips used in data centers, 5G phones, and AI-powered devices.  

In summary:

• Kokusai is a small acquisition for Applied materials as compared to the previously failed mega-merger with Tokyo Electron, meaning that the road to approval should be easy. However, China’s willingness from a political standpoint is always a risk, Evercore analysts said. 
• Apart from China, the acquisition will need approvals from Israel, Ireland, Japan, Korea and Taiwan, Applied Materials Chief Financial Officer Dan Durn said on a call with analysts.
• Kokusai, which counts Samsung, SK Hynix, Toshiba and Micron among its top customers, reported revenue of $1.24 billion as of March 2018. 
• Kokusai’s batch wafer processing tools are less technology intensive than Applied Materials’ single wafer tools, the recent focus on ultra-thin films has driven renewed interest in this group, DA Davidson analysts said.

So this whole purchase is really about Applied Materials getting a state of the art ALD technology for the memory business (DRAM and 3DNAND). The last readout is a bit crazy, the analyst refers to ALD as an "Ultra Thin Films". Anybody who has followed the ALD business the previous 15-20 years know that Applied Materials has repeatedly failed to take a big market share in ALD and that a Japanese Large Batch ALD reactor is one of the most advanced and reliable ALD tools out there - simply because nobody would like to trash a full load of +100 product wafers. The top three domination has been by:

• ASM International
• Tokyo Electron
• Kokusai

The top 3 has been followed by Lam Research, Jusung Engineering, Wonik IPS and Applied Materials was always somewhere in this bunch. Even the inrodcution of the new Spatial ALD Olympia platform didn´t change things. It seems that Tokyo Electron took a large part of the spatial ALD market with their NT333 tool and ASM was able to defend their single wafer approach by making the XP platform super productive by adding more chamber slots (up to 16 for the latest ASM XP8 QCM).  

When it comes to IP in Spatial ALD, Tokyo Electron is No.1 followed by Applied Materials (see below).

IP Applications for spatial ALD

Magically, Kokusai settled the IP issues with ASM just before the Applied announcement (LINK). Historically, Kokusai has been masters in avoiding to call ALD ALD because of the IP situation. However, now there is a different situation and Kokusai also have single wafer ALD out there, and Applied is dominating the BEOL films deposition business so we can assume that Applied will enter top three and have a go at No 1. Exciting!

TechInsights’ Logic, NAND, DRAM and Emerging Memory Process Roadmaps are here

TechInsights’ Logic Process Roadmap offers an assessment and the anticipatory timing of new innovations from key players within the Logic space including: TSMC, Global Foundries, Intel & others. Download the roadmap here http://bit.ly/2FipHHA 

TechInsights’ technology roadmaps show you the innovations we are monitoring

For over 30 years, TechInsights has been reverse engineering semiconductors and advanced technology products, developing the world’s largest library of technical analysis. We have built this library through two approaches: by conducting analysis in response to client requests, and by proactively analyzing disruptive or innovative technologies as they are released.

We constantly monitor the consumer electronics market to determine which manufacturers are planning to release new solutions, and when. We maintain and regularly update technology roadmaps in several different areas: Logic, NAND Flash Memory, DRAM, Emerging Memory, and Internet of Things Connectivity Systems on Chips, and more.

Updates to the roadmaps shown below are released throughout the year; check this page for updates. 

What Will Come After V‐NAND—Vertical Resistive Switching Memory?

Here is a hot paper from Hwang in Advanced Materials on what may come after V-NAND/3DNAND Flash meory architecture. In the case of Vertical ReRAM we can assume that there are numerous opportunities for funky ALD materials and processes!

 

What Will Come After V‐NAND—Vertical Resistive Switching Memory?
Kyung Jean Yoon, Yumin Kim, Cheol Seong Hwang
Version of Record online:28 February 2019
https://doi.org/10.1002/aelm.201800914

 
Pathways to overcome the scaling limitation of vertical NAND flash memory (V‐NAND), the present market leading nonvolatile memory, providing new materials and array structure suggestions, are provided. Specifically, the favorable aspects of a vertical resistive random access memory (V‐ReRAM) structure, such as areal density and decoding schemes, are highlighted in comparison with the commercialized nonvolatile memories: 3D‐Crosspoint and V‐NAND.

Western Digital and Toshiba have developed a 128-layer 3D NAND die with TLC (3bits/cell) cell formatting and 512Gbit capacity.Acoording to etimates and modelling WD-Toshiba has the industry’s highest NAND density and models the suppliers at an 85 per cent wafer yield - thanks Terry Francis for sharing.

ASM International report recovery in the single-wafer ALD market due to strong 3D-NAND fab invest

Almere, The Netherlands, March 22, 2018 ASM International N.V. (Euronext Amsterdam: ASM) today publishes its 2017 Annual Report.

ASMI's Annual Report is also available on the company's website www.asm.com. The Annual Report includes the Corporate Responsibility Report and the Remuneration Report in order to increase the relevancy and quality of reporting to all stakeholders.

ASMI will hold its Annual General Meeting of Shareholders (AGM) on May 28, 2018. The AGM agenda with all related documents will be available in due time.

MESSAGE FROM THE CEO (asm.com LINK)

In 2017 we achieved significant progress against our strategic targets. Our sales benefited from a clear recovery in the single-wafer Atomic Layer Deposition (ALD) market, in particular driven by strong increases in the 3D-NAND segment. During the year we also successfully expanded our position in the epitaxy market with an important tool win from a leading foundry customer. In total, our revenue increased by 23% to a new record level. 

Please check out the financial data at a glance here (LINK).

Challenges in 3D-NAND high volume manufacturing

Planar NAND was scaled and at the end limited by the cost of lithography, wheras 3D NAND scaling is enabled by advanced deposition and etch processes defining complex high aspect ratio 3D structures. Here is an excellent article by Lam Research in Solid State Technology on the challenges in 3D-NAND fabrication.

Solis State Technology : LINK

Screen capture from Solid State Technology online magazine (LINK)

ASM International technical luncheon seminar in San Francisco at IEDM 2017, December 7

ASM International N.V. (Euronext Amsterdam: ASM) today announces that it will host a technical luncheon seminar in San Francisco, CA, US, on Wednesday, December 7, 2016, the third day of the IEDM Conference.

 

At this technology seminar ASM will highlight the challenges and potential solutions for achieving next generation 3D devices.

The agenda is as follows:

11:30 am Food and drinks

12:00 - 12:05 pm Ivo Raaijmakers (ASM) - Welcome and introduction

12:05 - 12:30 pm Invited speaker: Raghuveer Makala (SanDisk/WDC) - "Thin film deposition
challenges for 3D NAND"

12:30 - 12:55 pm Invited speaker: Jorge Kittl (Samsung) - "Perspectives on logic scaling and
implications for process requirements"

Following the presentations, there is an opportunity for open discussion and networking until 1:15 pm.

The ASM technology seminar will take place in the Golden Gate room (25th floor) at the Nikko Hotel (across from the Hilton San Francisco), San Francisco, CA 94102. The room will open at 11:30 am for invited attendees. Interested parties should contact Rosanne de Vries, +31 88 100 8569, rosanne.de.vries@asm.com.

Applied Materials to grow in 3DNAND, Logic and Materials based patterning

Applied Materials Expects higher wafer fab equipment (WFE) spending driven by :

• multi-year inflections including 3D NAND,10 and 7 nanometer logic and foundry, 
• materials-based patterning
• new factory investments in China Outlines plans to drive 50 percent growth in display business to $1.8 billion by FY2019

NEW YORK, Sept. 21, 2016 (GLOBE NEWSWIRE) -- At its 2016 Analyst Day, Applied Materials, Inc. detailed its innovation leadership strategy to drive sustainable growth and announced target non-GAAP adjusted earnings per share of $2.45 to $3.17 for fiscal 2019, with a midpoint of $2.80. This would represent compound earnings growth of approximately 17 percent over the next three years.

[UPDTAE] Lam Research launch New ALTUS(R) Max E Series for Low-fluorine, Low-stress, and Low-resistivity ALD Tungsten

[UPDATE] :  Lam Blog - Innovative Tungsten ALD Process Provides Pathway to New Memory Chip Production : http://blog.lamresearch.com/innovative-tungsten-ald-process-provides-pathway-to-new-memory-chip-production/

 ALTUS Max E Series 4 station chambers (Picture from Lam Blog)

FREMONT, CA -- (Marketwired) -- 08/09/16 -- Lam Research Corp. (NASDAQ: LRCX), an advanced manufacturer of semiconductor equipment, today introduced an atomic layer deposition (ALD) process for depositing low-fluorine-content tungsten films, the latest addition to its industry-leading ALTUS® family of products. With the industry's first low-fluorine tungsten (LFW) ALD process, the ALTUS Max E Series addresses memory chipmakers' key challenges and enables the continued scaling of 3D NAND and DRAM devices. Building on Lam's market-leading product portfolio for memory applications, the new system is gaining market traction worldwide, winning production positions at leading 3D NAND and DRAM manufacturers and placement at multiple R&D sites.

ALTUS Max E Series 4 station chambers shuffling wafers (Picture from Lamresearch.com)

"Consumer demand for ever more powerful devices is driving the need for high-capacity, high-performance storage, and deposition and etch are key process technology enablers of advanced memory chips," said Tim Archer, Lam's chief operating officer. "With the addition of the ALTUS Max E Series, we are expanding our memory portfolio and enabling our customers to capitalize on this next wave of industry drivers. Over the past twelve months, as the 3D NAND inflection has accelerated, we have doubled our shipments for these applications, leading to the largest deposition and etch installed base in our 3D NAND served markets."

As manufacturers increase the number of memory cell layers for 3D NAND, two issues have become apparent for tungsten deposition in the word line fill application. First, fluorine diffusion from the tungsten film into the dielectrics can cause physical defects. Second, higher cumulative stress in devices with more than 48 pairs has resulted in excessive bowing. The resulting defects and stress can cause yield loss, as well as degraded electrical performance and device reliability. Because of these issues, tungsten films for advanced 3D NAND devices must have significantly reduced fluorine and intrinsic stress. Further, as critical dimensions shrink, resistance scaling becomes more challenging for the DRAM buried word line, as well as for metal gate/metal contact applications in logic devices.

"As memory chip manufacturers move to smaller nodes, the features that need to be filled are increasingly narrow and have higher aspect ratios," said Sesha Varadarajan, group vice president, Deposition Product Group. "Lam's new LFW ALD solution uses a controlled surface reaction to tune stress and fluorine levels and to lower resistance, all while delivering the required tungsten fill performance and productivity. When compared to chemical vapor deposition tungsten, the ALTUS Max E Series lowers fluorine content by up to 100x, lowers stress by up to 10x, and reduces resistivity by over 30%, solving some of our customers' most critical scaling and integration challenges."

The ALTUS Max E Series with LFW ALD technology offers a unique all-ALD deposition process that leverages Lam's PNL® (Pulsed Nucleation Layer) technology, which is the industry benchmark for tungsten ALD with 15 years of market leadership and more than 1,000 modules in production. Lam led the transition of chemical vapor deposition (CVD) tungsten nucleation to ALD tungsten nucleation with its PNL technology. The company continued that leadership by advancing low-resistivity tungsten solutions with its products ALTUS® Max with PNLxT™, ALTUS® Max with LRWxT™, and ALTUS® Max ExtremeFill™ for enhanced fill performance.

The ALTUS products use Lam's quad-station module (QSM) architecture to allow per-station optimization of tungsten nucleation and fill for fluorine, stress, and resistance without compromising fill performance since station temperature can be set independently. The QSM configuration also maximizes productivity of the all-ALD process by providing up to 12 pedestals per system, enabling the highest footprint productivity in the industry.

The Future Paths for 3DNAND and ALD Opportunities

Here are brief summary of a recent interesting article in Semiconductor Engineering by Mark LaPedus on the topic of future paths for NAND Flash Memory, which is a big market for ALD with strong competition between ASM, Lam Research and others and high aspect ration Etch Technology from Applied Materials and Lam Research. I also and added some stuff that I found elsewhere.

What’s Next For NAND?

May 19th, 2016 - By: Mark LaPedus
http://semiengineering.com/whats-next-for-nand/

Scaling standard 2DNAND technology is coming to an end and all major NAND manufacturers are ramping 3DNAND today.  The NAND market leader (34%, see below) Samsung is in the lead a shipped their first 24 layer 128 gigabit chip in 2013 and have since then introduced a 32 layer are now since last year shipping the 3rd generation 48 layer chip offering a 256 gigabit storage capacity.

Intel and Micron has joined forces in NAND (joint 22% market share) and recently started shipping a 32 layer 3DNAND chip. The other duo, SanDisk (16%) and Toshiba (19%) as well as SK Hynix (10%) are trailing Samsung with their most current 48 layer chips.

Current NAND Flash Market share - Source: Semiconductor Engineering.

3DNAND Technology - Floating Gate vs. Charge Trap Flash

Floating Gate - Micron and Intel, currently uses the floating gate architecture

2015 Micron Presentation explaining the advantages with their 3D NAND floating gate technology shared with Intel.

Here you can read more about the Intel/Micron floating gate technology in an article by Dick James at Chipworks. I am not sure if ALD is used for the oxide and nitride layers but it is a possibility for sure due to high aspect ratio sttructures..


Charge Trap - Samsung, SK Hynix and the SanDisk/Toshiba are all steaming up the layers using charge trap NAND.

Samsung Promo video: Samsung's 3D V-NAND flash memory is fabricated using an innovative vertical design. Its vertical architecture stacks 32 cell layers on top of one another, rather than trying to decrease the cells' length and width to fit today's ever-shrinking form factors. [youtube.com]

A Look Ahead at IEDM 2015, Solid State Technology, By Dick James, Senior Technology Analyst, Chipworks

Many available cross sections of available on the internet show high-k material (Al2O3) and a metal nitride (TiN) gate being used for the to connect to the tungsten control gate. I can only assess it as ALD being used in these extreme aspect ratios. 

According to a statement in the article made by Applied materials 3DNAND will make the step from 48 to 64 layers in 2016 and if it can be scaled further will be limited at some point by high aspect ration etch capability of 96 or 128 layers. However, I am a bit doubtful here that actually the technology will be limited by etch unit process engineers. As a comparison, many think that deep trench DRAM scaling was killed by high aspect ratio etch but it was not, it was rather the impossibility to scale the memory cell down from 8F2 , via 6F2 down ti a most compact 4F2 cell design. In any, case these are not extreme aspect ratios for ALD so either the etchers or the device physics will have to throw in the towel for 3DNAND momentarily. - to conclude there are two possible paths according to Mark LaPedus:

The first path:

"So going forward, NAND suppliers will simultaneously follow two parallel paths. The first path is to wait for the etch tools and other manufacturing techniques to arrive. And if they arrive on time, vendors could scale today’s 3D NAND device from 32- and 48-layers, to 64 layers, to 96 and then to 128."

The second path:

"The second path is to move towards string stacking technology. This involves stacking two or more individual devices on top each other. Each device is separated by an insulating layer. String stacking is already in the works. Recently, Micron presented a paper on a new 64-layer chip. Micron, according to multiple sources, stacked two 32-layer chips on top of each other. In theory, string stacking could involve several different combinations. For example, a vendor could stack three 32-layer chips, enabling a 96-layer device. In addition, a vendor could stack three 96-layer chips, resulting in a 288-layer product."

Samsung is using an ALD Al2O3 gate dielectric for 3D V-NAND

Samsung seems to be using an ALD Al2O3 gate dielectric with a TiN/W Metal Gate according to Dick James at Chipworks who recently reported on the matter in front of IEDM 2015 (http://electroiq.com/chipworks_real_chips_blog/2015/12/02/a-look-ahead-at-iedm-2015/).

"Samsung started shipping their V-NAND last year, but that uses charge-trap storage, in which the electrons that make up the memory bits sit on a silicon nitride layer; the Intel/Micron device uses the conventional floating-gate method used in planar flash, where the electrons are stored on a polysilicon floating gate. It’ll be interesting to see the difference!"

 

Plan-view TEM images of Samsung V-NAND flash array (Chipworks) 

Looking at the rest of the stack one want to believe that also the TiN, SiO2 and SiN is deposited by ALD. However, knowing that those materials can successfully be deposited in a LPCVD or pulsed LPCVD process it can just as well be done in Large Batch furnaces from any of the companies ASM, Kokusai or Tokyo Electron. Those furnaces are for sure also capable of running the processes in a pure ALD mode though.

Below is a principal cross section of the first couple of cells in the Samsungs 3D NAND  from

Samsung SSD 850 Pro (128GB, 256GB & 1TB) Review: Enter the 3D Era by Kristian Vättö"

 

"NAND scaling in vertical dimension does not have the same limitations as scaling in the X and Y axes do. Because the cost of a semiconductor is still mostly determined by the die area and not by the height, there is no need to cram cells very close to each other. As a result, there is very little interference between the cells even in the vertical direction. Also, the usage of high-k dielectrics means that the control gate does not have to wrap around the charge trap. The result is that there is a hefty barrier of silicon dioxide (which is an insulator) between each cell, which is far more insulating than the rather thin ONO layer in 2D NAND."

Micron’s 32-layer 3D NAND for production this year

The Tool makers of advanced semiconductor processing equipment look form inflection points for new advanced processing technology such as ALD. "The inflection points include the move towards multi-patterning. That’s an enormous driver of growth,” “It’s also the move to finFET from planar. It’s planar to 3D NAND, as well as the move to 3D packaging.” - Doug Bettinger, executive vice president and chief financial officer at Lam Research

Doug must be happy to hear that besides Samsung and Toshiba, Micron will move into pilot production of a 32-layer 3D NAND device in the second half of this year according to Electronics Weekly  The entry device will be a 32-layer device (pictured below) and it is believed that 3D NAND does not become cost-competitive with the most advanced planar NAND until it reaches 48 layers and Micron intends to introduce a 2nd generation 3D NAND which is, presumably, a 48-layer device, end of next year.

Micron 3DNAND 32 layer stack device

2016 will be another growth year for OEM stocks and Atomic Layer Processing

2016 will be another growth year for OEM stocks and Atomic Layer Processing. In a report recently published by JP Morgan, analysts predicted another growth year in 2016 for Semiconductors stocks, driven by technology transitions in memory and 10nm FinFET. So this is good news for all Tier 1 OEMs with a number of ALD and ALE technologies in the game.

Technology transitions by memory companies :

• continued 3D NAND ramps
• additional 20nm conversions
• initial 1Xnm DRAM deployments

Foundry and logic companies :

• deploying FinFET technologies (especially 10nm FinFET) 
• multi-patterning steps and vertical transistors

"In general, we see capital intensity increasing by 10-15% on a per wafer basis when transitioning from 14nm/16nm FinFET to 10nm FF and by 15+% when transitioning to 20nm and below DRAM / 3D NAND. The number of critical patterning layers is increasing dramatically – in the foundry/logic segment, the number of critical layers is increasing by over 3x going from 28 nm node to the 10nm node…a significant increase," the analysts added.

Read more: http://www.benzinga.com/analyst-ratings/analyst-color/15/05/5488523/jp-morgan-sees-another-growth-year-for-semiconductors-th#ixzz3aNRgk5q0

Below is an overview of some of the ALD and ALE technologies offered by the leading OEMs. It is ion sense complete yet so please let me know what is missing (jonas.sundqvist@baldengineering.com).

LAM Research

LAM Research reported in 2014 that "The latest in Lam's market-leading tungsten deposition product line, the ALTUS Max ICEFill system controls variability by providing void-free fill of the geometrically complex 3D NAND wordlines. Using a proprietary filling technique, the new system creates the tungsten wordlines with an inside-out atomic layer deposition (ALD) process. The ICEFill process completely fills the lateral (horizontal) lines without any voids, while at the same time minimizing deposition in the vertical channel area. As a result, both electrical performance and yield are enhanced."

Lam’s ALTUS systems combine CVD and ALD technologies to deposit the highly conformal films needed for advanced tungsten metallization applications (http://www.lamresearch.com/products/deposition-products).

Lam's new ALE capability on the 2300 Kiyo F Series conductor etch system provides both the productivity and technology needed. The product leverages fast gas switching and advanced plasma techniques in the reactor to boost throughput, while dynamic RF bias enables the directional etching required to remove material in high aspect ratio (deep and narrow) features. As the latest offering in Lam's market-leading Kiyo family, the 2300 Kiyo F Series system continues to provide superior uniformity and repeatability enabled by a symmetrical chamber design, advanced electrostatic chuck technology, and independent process tuning features.

• Shallow trench isolation
• Source/drain engineering
• High-k/metal gate
• FinFET and tri-gate
• Double and quadruple patterning
• 3D NAND

To learn how atomic layer deposition (ALD) and atomic layer etch (ALE) processes work, watch this video from LAM Research (www.youtube.com).

Applied Materials

CENTURA® ISPRINT™ TUNGSTEN ALD/CVD - The Applied Centura iSprint Tungsten ALD/CVD system provides complete contact/via fill for structures with aspect ratios ranging from 4:1 to 7:1 and extends the capability of tungsten technology to 20nm/16nm for logic and memory applications.

The iSprint system also delivers high throughput and low cost of consumables with an optimized ALD chamber design featuring a proprietary rapid gas delivery system and small chamber volume that enable fast, effective gas purging that uses less gas (www.appliedmaterials.com).

CENTURA® INTEGRATED GATE STACK - The system consists of an ALD HfO2 (hafnium oxide) deposition chamber and specialized chambers for interface layer oxide formation, post high-k nitridation, and post-nitridation anneal

The Centura Integrated Gate Stack system with ALD high-k chamber technology for 22nm and below uses Applied’s production-proven Centura Gate Stack platform to deliver the complete high-k process sequence in a controlled high vacuum environment without an “air break” (www.appliedmaterials.com).

Steven Hung, Ph.D. who specializes in integrating ALD into the transistor manufacturing process, dives deep into the chip to show what tomorrow's transistors look like, how they work, and how Applied can help the industry meet the challenges of fabricating these ultra-tiny structures to make faster, more power-efficient microchips (www.youtube.com).

Tokyo Electron

Tokyo electron has a number of ALD technologies and are very strong in batch processing that is used to large extent in DRAM production to get the cost per wafer down since DRAM is a commodity product.

• TEL Formula - Mini batch, thermal processes including ALD for High-k, SiO2, SiN.
• TEL INDY Plus - Large batch, thermal processes including ALD for High-k, SiO2, SiN.
• TEL INDY IRad - Large batch, PEALD for ultra low temperature SiO2 and SiN.
• TEL NT333 - Single wafer cluster tool for high t-put SiO2.

TEL INDY Large batch furnace for thermal processing and ALD (www.tel.com)

The NT333 applies inherent ALD concepts against conventional ALD processing to address the critical performance needs imposed by aggressive geometries. The NT333 can effectively deposit with a very tight thickness control, a range of less than 1A, while maintaining a productivity of 100+ wafers per hour. With a very unique reactor design, each of the ALD duty cycles enables the NT333 to deliver the high film quality which is typically compromised at low temperature regimes (<400C). (www.tel.com)

ASM International

ASM's ALD technologies, includes thermal ALD (Pulsar) for FinFET high-k metal gate stacks, and various applications of Plasma Enhanced ALD (Emerald) as an enabler for low temperature processing such as multiple patterning on resist and deposition of doped silicon oxide for solid state doping of FinFETs.

​ASM’s Pulsar uses ALD to deposit the high-k dielectric materials required for advanced CMOS transistor gates ​and other applications. Pulsar is the benchmark ALD high-k tool for the industry. It was the first ALD system to be used for high-volume production at advanced customers for high-k metal gate transistors (www.asm.com).

EmerALD XP is a process module designed to deposit thin conformal metal and dielectric ​layers by atomic layer deposition (ALD) used for advanced CMOS gate stacks and other applications (www.asm.com).

​​​Eagle XP8 is a high productivity 300mm tool for PEALD applications. The Eagle XP8 PEALD system can be configured with up to four Dual Chamber Modules (DCM), enabling eight chambers in high volume production within a very compact footprint (www.asm.com).

ASM Chip Making Process (www.youtube.com)

LAM Research MMP Technology Etch for Advanced Memory

"MMP technology enables atomic layer etching (ALE), providing extendibility and repeatability with atomic-scale fidelity"

Atomic-scale fidelity - Can you put it more beautiful?

LAM Research has developed a mixed-mode pulsing (MMP) technology that enables critical conductor etch for advanced memory like 3D NAND and DRAM. The technology is available for their Kiyo Product F Series chambers. 

LAM Research reports: The Kiyo F Series delivers high productivity while minimizing variability for advanced memory applications. Lam's MMP technology provides advanced profile and CD control for vertical profiles with good selectivity and tuning controls for consistent etch depths. These capabilities enable higher trim rate for 3D NAND staircase etch along with excellent repeatability, which is needed for manufacturing environments. Symmetric chamber design and radial tuning provide best-in-class uniformity, which is essential for minimizing CD variability. 

In addition, for new generations of advanced memory as well as logic devices, MMP technology enables atomic layer etching (ALE), providing extendibility and repeatability with atomic-scale fidelity.

By stacking memory cells vertically, NAND flash manufacturers can pack more storage capacity onto a smaller device, ease lithography requirements, and reduce manufacturing cost per bit. For multilayer 3D NAND structures, critical conductor etch processes include staircase etch and high aspect ratio (HAR) mask open for vertical channels. This mask open is crucial since it defines the CD and CD uniformity for subsequent etching of the vertical transistor channels. For staircase etch, equal-width "steps" are created at the edge of each dielectric-film pair throughout the 3D stack to form a staircase-shaped structure. Because of extensive repetition of these steps during device processing, etching at high throughput with stringent process control is vital. CD variability must be tightly managed since wordline contacts may otherwise miss landing on a step that is too narrow or uneven. 

Just for visualisation for the reader of this blog, here the advance HAR etch that is required and mastered by LAM MMP Technology described in a reverse engineering cross section by Chipworks from a SAMSUNG V-NAND Flash array (published here)

LAM Research further reports with respect to DRAM : For advanced DRAM devices, depth control is a key parameter, particularly for HAR front-end-of-line silicon etch applications. Concerns include aspect ratio loading, where etch rates vary because of differences in feature dimensions, and depth loading, where different etch depths may occur due to pattern density variations.

More detailed information on mixed-mode plasma pulsing (MMP) can be found in this patent by LAM Research:

Mixed mode pulsing etching in plasma processing systems US 20130168354 A1