- Gapfill dielectrics
- Conformal liners
- Patterning spacers and masks
- Hermetic encapsulation
- Etch stop layers
- Optical films
Wednesday, December 9, 2020
ALD to take over more and more as CVD and spin-on processes no longer are viable for 3D NAND
Wednesday, October 28, 2020
TechInsights Webinar: ALD/ALE Process in Commercially Available Memory Devices
Friday, September 18, 2020
Process Power: The New Lithography - Advanced Energy
Here is a very insightful article by PETER GILLESPIE, VP & GM, Semiconductor Products, Advanced Energy Industries on the progress of Plasma RF Generators and Matching Networks. The article looks at applications in 3DNAND High Aspect Ratio Contacts (HARC) and Logic FinFET transitor fabrication using reactive ion etching and plasma CVD using the latest plasma technology. This is a an articel in a series of three in SEMICONDUCTOR DIGEST entitled “Process Power Steps Out from the Shadows,” looking at the leading edge technology node process challenges to highlight key drivers that are fundamentally transforming the role and importance of process power.
Process Power: The New Lithography (SEMICONDUCTOR DIGEST, LINK)
"Evolution of RF power supplies (plasma generators) and RF matching networks. Today’s RF power delivery systems are highly sophisticated with frequency tuning, complex pulsing regimes, and agile micro-second response." (Below)
Wednesday, September 2, 2020
TechInsights’ Memory Process: 3D NAND Word Line Pad webinar
TechInsights’ ‘Memory Process: 3D NAND Word Line Pad‘ #webinar compares 9x-layer 3D NAND devices from major manufacturers and discusses the process sequence with emphasis on the word line pad (WLP). Watch on demand here LINK
Monday, April 20, 2020
Choppy Waters for Shipping $50B of Semiconductor Materials in 2020
Risky Sailing on the Global Supply-Chain Seas
San Diego, CA, Apr 17, 2020:TECHCET announces that:• Impact of COVID-19 pandemic on the global economy is creating choppy waters for shipping and supplying critical materials, as highlighted in recent Critical Materials Council (CMC) monthly meetings, and
• With a return of global economic growth by 2021, compound annual growth rate (CAGR) through 2025 is forecast at 3.5% as shown in the Figure (below).
“From our market research, materials suppliers are increasing production and sales to ensure safety-stock throughout the supply-chain in case there are further disruptions due to COVID-19 cases,” remarked Lita Shon-Roy, TECHCET President and CEO. “Even without further disruptions, we can already see leading economic indicators such as unemployment levels, metal prices and container shipping indices point toward a significant decline in global GDP.” This is supported by the International Monetary Fund’s (IMF’s) current outlook on 2020.
Currently, almost all chip fabs appear to be running at normal levels, with a few exceptions. During this difficult period, YMTC in Wuhan, China reportedly has maintained R&D and grown production of 3D-NAND chips. However, chip fabs in Malaysia report that the government required companies to request permission to continue operating at 50% staffing levels. One company in France had to temporarily reduce production due to their labor union insisting on temporary workforce reductions.
Significant value-added engineered materials including specialty gases, deposition precursors, wet chemicals, chemical-mechanical planarization (CMP) slurries & pads, silicon wafers, PVD/sputtering targets, and photoresists & ancillary materials for lithography are reporting healthy orders and in some cases will see better than expected revenues for 1Q2020 and April 2020. However, more than 60% of all materials are expected to be negatively impacted before year-end.
Overall demand for commodity materials, such as silane and phosphoric acid, is expected to decline YoY in 2020 by an average of 3% due to softening of the global economy. Average selling prices (ASP) for electronic-grade commodities may drop due to cost reductions in feed-stocks; for example, the global helium (He) gas market which had been forecasted to be in shortage with high ASPs throughout 2020 has already improved due to COVID-19 slowing down helium demand.
DRAM, 3D-NAND, and MPU chips for server / cloud-computing applications are now in high demand for virtual meetings and remote work. It is yet unclear how much of an increase in materials shipments will be needed to support this segment, however from TECHCET’s modeling of prior cycles it will likely be >7%. Despite such an increase in the materials used to make leading-edge ICs to build out data centers, shipments in support of legacy node IC fabrication are expected to decline this year.
Consequently, cloud-computing growth may not compensate for overall reduced semiconductor materials demands caused by economic downturns this year. By 2021 the global economy and all chip fabs should return to healthier growth, with materials markets for all IC devices expected to increase at a CAGR of +3.5% through 2025.
Critical Materials Reports™ and Market Briefings: TECHCET Shop
CMC Events: Click here to view all Events
Friday, August 9, 2019
Lam Research Adds Global Wafer Stress Management Solutions to Portfolio to 3D NAND Scaling
Designed to provide a cost-effective solution for controlling wafer bow in 3D NAND manufacturing, the VECTOR DT system is the newest addition to Lam’s plasma-enhanced chemical vapor deposition (PECVD) product family. VECTOR DT provides a single-step solution for wafer shape management by depositing a tunable counter-stress film on the back of the wafer without contacting the front side, thereby enabling improved lithography results, reduced bow-induced failures, and integration of high performance but highly stressed films. With strong customer adoption since its debut, the VECTOR DT installed base continues to grow as customers are transitioning to more than 96 layers.
In addition to depositing a counter stress film, Lam provides the flexibility to remove backside films, allowing customers to adjust wafer stress during the 3D NAND manufacturing flow. Lam’s EOS GS wet etch product complements the VECTOR DT by simultaneously removing backside and bevel films with industry-leading wet etch uniformity, while fully protecting the wafer front side. As part of a comprehensive wafer bow management solution, Lam’s EOS GS has also been adopted by memory manufacturers worldwide.
“As our customers continue to dramatically increase the number of memory cell layers, the cumulative stress and wafer bow can exceed the limits of a lithography tool. Minimizing stress-induced distortion is critical for achieving the desired yield and enabling the cost-per-bit roadmap,” said Sesha Varadarajan, senior vice president and general manager of the deposition product group at Lam Research. “With the addition of the VECTOR DT and EOS GS systems, we are expanding our stress management solutions portfolio for managing global stress in support of our customers’ vertical scaling roadmap.”
Tuesday, July 2, 2019
Applied Materials to buy Japan's Kokusai to boost memory chip business and ALD
- Kokusai is a small acquisition for Applied materials as compared to the previously failed mega-merger with Tokyo Electron, meaning that the road to approval should be easy. However, China’s willingness from a political standpoint is always a risk, Evercore analysts said.
- Apart from China, the acquisition will need approvals from Israel, Ireland, Japan, Korea and Taiwan, Applied Materials Chief Financial Officer Dan Durn said on a call with analysts.
- Kokusai, which counts Samsung, SK Hynix, Toshiba and Micron among its top customers, reported revenue of $1.24 billion as of March 2018.
- Kokusai’s batch wafer processing tools are less technology intensive than Applied Materials’ single wafer tools, the recent focus on ultra-thin films has driven renewed interest in this group, DA Davidson analysts said.
- ASM International
- Tokyo Electron
- Kokusai
Wednesday, June 19, 2019
TechInsights’ Logic, NAND, DRAM and Emerging Memory Process Roadmaps are here
TechInsights’ technology roadmaps show you the innovations we are monitoring
We constantly monitor the consumer electronics market to determine which manufacturers are planning to release new solutions, and when. We maintain and regularly update technology roadmaps in several different areas: Logic, NAND Flash Memory, DRAM, Emerging Memory, and Internet of Things Connectivity Systems on Chips, and more.
Updates to the roadmaps shown below are released throughout the year; check this page for updates.
Saturday, March 9, 2019
What Will Come After V‐NAND—Vertical Resistive Switching Memory?
Kyung Jean Yoon, Yumin Kim, Cheol Seong Hwang
Version of Record online:28 February 2019
https://doi.org/10.1002/aelm.201800914
Pathways to overcome the scaling limitation of vertical NAND flash memory (V‐NAND), the present market leading nonvolatile memory, providing new materials and array structure suggestions, are provided. Specifically, the favorable aspects of a vertical resistive random access memory (V‐ReRAM) structure, such as areal density and decoding schemes, are highlighted in comparison with the commercialized nonvolatile memories: 3D‐Crosspoint and V‐NAND.
Saturday, March 24, 2018
ASM International report recovery in the single-wafer ALD market due to strong 3D-NAND fab invest
ASMI's Annual Report is also available on the company's website www.asm.com. The Annual Report includes the Corporate Responsibility Report and the Remuneration Report in order to increase the relevancy and quality of reporting to all stakeholders.
ASMI will hold its Annual General Meeting of Shareholders (AGM) on May 28, 2018. The AGM agenda with all related documents will be available in due time.
MESSAGE FROM THE CEO (asm.com LINK)
Thursday, August 3, 2017
Challenges in 3D-NAND high volume manufacturing
Friday, December 2, 2016
ASM International technical luncheon seminar in San Francisco at IEDM 2017, December 7
The agenda is as follows:
11:30 am Food and drinks
12:00 - 12:05 pm Ivo Raaijmakers (ASM) - Welcome and introduction
12:05 - 12:30 pm Invited speaker: Raghuveer Makala (SanDisk/WDC) - "Thin film deposition
challenges for 3D NAND"
12:30 - 12:55 pm Invited speaker: Jorge Kittl (Samsung) - "Perspectives on logic scaling and
implications for process requirements"
Following the presentations, there is an opportunity for open discussion and networking until 1:15 pm.
The ASM technology seminar will take place in the Golden Gate room (25th floor) at the Nikko Hotel (across from the Hilton San Francisco), San Francisco, CA 94102. The room will open at 11:30 am for invited attendees. Interested parties should contact Rosanne de Vries, +31 88 100 8569, rosanne.de.vries@asm.com.
Thursday, September 22, 2016
Applied Materials to grow in 3DNAND, Logic and Materials based patterning
- multi-year inflections including 3D NAND,10 and 7 nanometer logic and foundry,
- materials-based patterning
- new factory investments in China Outlines plans to drive 50 percent growth in display business to $1.8 billion by FY2019
Wednesday, August 10, 2016
[UPDTAE] Lam Research launch New ALTUS(R) Max E Series for Low-fluorine, Low-stress, and Low-resistivity ALD Tungsten
FREMONT, CA -- (Marketwired) -- 08/09/16 -- Lam Research Corp. (NASDAQ: LRCX), an advanced manufacturer of semiconductor equipment, today introduced an atomic layer deposition (ALD) process for depositing low-fluorine-content tungsten films, the latest addition to its industry-leading ALTUS® family of products. With the industry's first low-fluorine tungsten (LFW) ALD process, the ALTUS Max E Series addresses memory chipmakers' key challenges and enables the continued scaling of 3D NAND and DRAM devices. Building on Lam's market-leading product portfolio for memory applications, the new system is gaining market traction worldwide, winning production positions at leading 3D NAND and DRAM manufacturers and placement at multiple R&D sites.
"Consumer demand for ever more powerful devices is driving the need for high-capacity, high-performance storage, and deposition and etch are key process technology enablers of advanced memory chips," said Tim Archer, Lam's chief operating officer. "With the addition of the ALTUS Max E Series, we are expanding our memory portfolio and enabling our customers to capitalize on this next wave of industry drivers. Over the past twelve months, as the 3D NAND inflection has accelerated, we have doubled our shipments for these applications, leading to the largest deposition and etch installed base in our 3D NAND served markets."
As manufacturers increase the number of memory cell layers for 3D NAND, two issues have become apparent for tungsten deposition in the word line fill application. First, fluorine diffusion from the tungsten film into the dielectrics can cause physical defects. Second, higher cumulative stress in devices with more than 48 pairs has resulted in excessive bowing. The resulting defects and stress can cause yield loss, as well as degraded electrical performance and device reliability. Because of these issues, tungsten films for advanced 3D NAND devices must have significantly reduced fluorine and intrinsic stress. Further, as critical dimensions shrink, resistance scaling becomes more challenging for the DRAM buried word line, as well as for metal gate/metal contact applications in logic devices.
"As memory chip manufacturers move to smaller nodes, the features that need to be filled are increasingly narrow and have higher aspect ratios," said Sesha Varadarajan, group vice president, Deposition Product Group. "Lam's new LFW ALD solution uses a controlled surface reaction to tune stress and fluorine levels and to lower resistance, all while delivering the required tungsten fill performance and productivity. When compared to chemical vapor deposition tungsten, the ALTUS Max E Series lowers fluorine content by up to 100x, lowers stress by up to 10x, and reduces resistivity by over 30%, solving some of our customers' most critical scaling and integration challenges."
The ALTUS Max E Series with LFW ALD technology offers a unique all-ALD deposition process that leverages Lam's PNL® (Pulsed Nucleation Layer) technology, which is the industry benchmark for tungsten ALD with 15 years of market leadership and more than 1,000 modules in production. Lam led the transition of chemical vapor deposition (CVD) tungsten nucleation to ALD tungsten nucleation with its PNL technology. The company continued that leadership by advancing low-resistivity tungsten solutions with its products ALTUS® Max with PNLxT™, ALTUS® Max with LRWxT™, and ALTUS® Max ExtremeFill™ for enhanced fill performance.
The ALTUS products use Lam's quad-station module (QSM) architecture to allow per-station optimization of tungsten nucleation and fill for fluorine, stress, and resistance without compromising fill performance since station temperature can be set independently. The QSM configuration also maximizes productivity of the all-ALD process by providing up to 12 pedestals per system, enabling the highest footprint productivity in the industry.
Wednesday, June 15, 2016
The Future Paths for 3DNAND and ALD Opportunities
What’s Next For NAND?
May 19th, 2016 - By: Mark LaPedushttp://semiengineering.com/whats-next-for-nand/
3DNAND Technology - Floating Gate vs. Charge Trap Flash
Floating Gate - Micron and Intel, currently uses the floating gate architecture2015 Micron Presentation explaining the advantages with their 3D NAND floating gate technology shared with Intel.
Here you can read more about the Intel/Micron floating gate technology in an article by Dick James at Chipworks. I am not sure if ALD is used for the oxide and nitride layers but it is a possibility for sure due to high aspect ratio sttructures..
Charge Trap - Samsung, SK Hynix and the SanDisk/Toshiba are all steaming up the layers using charge trap NAND.
The first path:
The second path:
Saturday, December 5, 2015
Samsung is using an ALD Al2O3 gate dielectric for 3D V-NAND
Sunday, June 28, 2015
Micron’s 32-layer 3D NAND for production this year
Sunday, May 17, 2015
2016 will be another growth year for OEM stocks and Atomic Layer Processing
Technology transitions by memory companies :
- continued 3D NAND ramps
- additional 20nm conversions
- initial 1Xnm DRAM deployments
- deploying FinFET technologies (especially 10nm FinFET)
- multi-patterning steps and vertical transistors
"In general, we see capital intensity increasing by 10-15% on a per wafer basis when transitioning from 14nm/16nm FinFET to 10nm FF and by 15+% when transitioning to 20nm and below DRAM / 3D NAND. The number of critical patterning layers is increasing dramatically – in the foundry/logic segment, the number of critical layers is increasing by over 3x going from 28 nm node to the 10nm node…a significant increase," the analysts added.Read more: http://www.benzinga.com/analyst-ratings/analyst-color/15/05/5488523/jp-morgan-sees-another-growth-year-for-semiconductors-th#ixzz3aNRgk5q0
LAM Research
- Shallow trench isolation
- Source/drain engineering
- High-k/metal gate
- FinFET and tri-gate
- Double and quadruple patterning
- 3D NAND
Applied Materials
Tokyo Electron
- TEL Formula - Mini batch, thermal processes including ALD for High-k, SiO2, SiN.
- TEL INDY Plus - Large batch, thermal processes including ALD for High-k, SiO2, SiN.
- TEL INDY IRad - Large batch, PEALD for ultra low temperature SiO2 and SiN.
- TEL NT333 - Single wafer cluster tool for high t-put SiO2.
ASM International
Thursday, May 14, 2015
LAM Research MMP Technology Etch for Advanced Memory
"MMP technology enables atomic layer etching (ALE), providing extendibility and repeatability with atomic-scale fidelity"
Atomic-scale fidelity - Can you put it more beautiful?
LAM Research has developed a mixed-mode pulsing (MMP) technology that enables critical conductor etch for advanced memory like 3D NAND and DRAM. The technology is available for their Kiyo Product F Series chambers.
Mixed mode pulsing etching in plasma processing systems US 20130168354 A1