Saturday, November 17, 2018

Researchers from University of Groningen, the Netherlands confirm ferroelectricity in nanosized HfO2 crystals

Since the finding of ferroelectricity in HfO2 films of sub 10 nm thickness by Tim Böscke*,  (US8304823B2 NaMLab gGmbH) more then 10 years ago many leading R&D teams and semiconductor companies has confirmed the findings. Now also ferroelectricity in nanosized HfO2 crystalsby has been confirmed by the "Hafnia team” within the Nanostructures of Functional Oxides group, Zernike Institute for Advanced Materials, University of Groningen (UG), the Netherlands (LINK). 

* then at the DRAM Company Qimonda

Figure shows inside view of vacuum chamber in which the process of 'pulsed laser deposition' takes place, used to create the hafnium oxide crystals in this study. On the left the glowing substrate on which the film is growing with atomic control; in the center the blue plasma of ions that is created by shooting a laser on a target with the right chemical composition (target visible on the right side of the figure). | Photo Henk Bonder, University of Groningen

Ferroelectric materials have a spontaneous dipole moment which can point up or down. This means that they can be used to store information, just like magnetic bits on a hard disk. The advantage of ferroelectric bits is that they can be written at a low voltage and power. Magnetic bits require large currents to create a magnetic field for switching, and thus more power. However, according to the scientific community, the aligned dipoles in ferroelectric materials are only stable in fairly large groups; thus, shrinking the crystals results into the loss of dipole moment obstructing ferroelectricity based storage devices.

Nevertheless, eight years ago, the first publication by ex-Qimonda experts and researchers from Fraunhofer and RWTH Aachen (Appl. Phys. Lett. 99, 102903 (2011); announced that hafnium oxide thin films were ferroelectric when thinner than ten nanometres and that thicker films actually lost their ferroelectric properties. This triggered many groups across the globe to dig deeper and confirm the claim of researchers from NamLab. Noheda and her group at University of Groningen was also one of them. Since the ferroelectric hafnium oxide samples used in the study carried out at NaMLab were polycrystalline and showed multiple phases, obscuring any clear fundamental understanding of such an unconventional phenomenon, Noheda and her group decided to study these crystals by growing clean (single-phase) films on a substrate.

Using X-ray scattering and high-resolution electron microscopy techniques, the group observed that very thin films (under ten nanometres) grow in an entirely unexpected and previously unknown polar structure, which is necessary for ferroelectricity. Combining these observations with meticulous transport measurements, they confirmed that the material was indeed ferroelectric. Surprisingly, they noticed that the crystal structure changed when the layers exceeded 10 nm, thus reaching the same conclusion as of the Namlab.

In the substrate that UG researchers used, the atoms were a little bit closer than those in hafnium oxide which strained hafnium oxide crystals a little. Moreover, at a very small size, particles have a very large surface energy, creating pressures of up to 5 GPa in the crystal. This altogether forces a different crystal arrangement and in turn polar phase in the HfO2 film.

One contradicting finding of the UG researchers is that the HfO2 crystals do not need a ‘wake-up’ cycle to become ferroelectric. The thin films investigated at NamLab turned ferroelectric only after going through a number of switching cycles (wake-up cycles) needed to align the dipoles in “uncleaned” samples grown via other techniques. In case of the pulsed laser deposition setup and the substrate used at UG, the alignment is already present in the crystals.

Meanwhile, NaMLab has explored ferroelectric properties in atomic layer deposition (ALD) based thin-films of doped HfO2, and has achieved revolutionary results (LINK). A variety of dopant materials (Si, Al, Ge, Y, Gd, La and Sr) with a crystal radius ranging from 50 to 130 pm has been studied in addition to a mixed Hf1-xZrxO2. The aim is to develop a memory concept with the HfO2 based ferroelectric transistors (FeFET) as building blocks. The FeFET is a long-term contender for an ultra-fast, low-power and non-volatile memory technology. In these devices the information is stored as a polarization state of the gate dielectric and can be read non-destructively as a shift of the threshold voltage. The advantage of a FeFET memory compared to the Flash memory is its faster access times and much lower power consumption at high data rates. In the framework of a project together with GLOBALFOUNDRIES and Fraunhofer IPMS, which was funded by the Free State of Saxony, a one-transistor (1T) FeFET eNVM was successfully implemented at NaMLab in a 28 nm gate-first super low power (28SLP) CMOS technology platform using only two additional structural masks (LINK). The electrical baseline properties remain the same for the FeFET integration, demonstrating the feasibility of FeFET as low-cost eNVM.

Guest Blog by: Abhishekkumar Thakur, Fraunhofer IKTS / TU Dresden
Location: Dresden, Germany


ALD at SEMICON Europa 2018

This year was the first time in a long time that we did not organize an ALD Symposium at SEMICON Europa. We decided to keep it as a Dresden event and it will be held 10th of December (LINK) followed by a visit to the famous Dresden Christmas market..

This year, I was invited together with a number of other ALD people to present at the Materials session in the Tech Arena and there was a great program with impressive presentations chaired by Johan Dekoster from Imec.


Materials Technology

Chair Johan Dekoster, Program Manager, imec
15:00 Introduction
15:05 New conductors – What are the options for N5, N3 and beyond?
Marleen van der Veen, Senior Scientist Nanointerconnects Metallization, imec
15:30 ALD/CVD applications, equipment and precursors in high volume manufacturing
Jonas Sundqvist, Group Leader, Fraunhofer IKTS
15:55 Advancing Atomic Layer Deposition and Atomic Layer Etching
Harm Knoops, Atomic Scale Segment Specialist, Oxford Instruments Plasma Technology
16:20 Atomic layer deposition for the synthesis and integration of 2D materials for nanoelectronics
Ageeth A. Bol, Associate Professor, Eindhoven University of Technology
16:45 Innovative Compound Semiconductor Based Engineered Substrates for Photonics, Power, Solar and RF Applications
Eric Guiot, Product Development Manager, Soitec
17:10 Kokusai Electric Corporation new products offering for 2018
Yoshio Kitahara, New Products offereing as Kokusai Electric, Kokusai Semiconductor Europe GmbH

Below here are some picture from the ALD Session, Exhibition and Show.

Heavy traffic on the Autobahn in to Munich - obviously more people are interested in ALD!

Friday, November 16, 2018

Beneq is expanding and looking for ALD professionals!

Beneq careers - come and join us at the Home of ALD

Join Us at Beneq!

The Beneq factory, the Home of ALD, is an extraordinary pool of thin film and display experience.
We strongly believe there is a thin solution for every challenge. And if somebody says it is impossible to do and others find the task too difficult, it only makes us more motivated. That is what Turning Innovations into Success is all about.

The future of Beneq is being built on the same character that defined the company.

Come and make Finnish high tech history with us! You can see the open positions below. You can also apply by sending us your open application and CV by clicking the link Open application below.

4th Area Selective Deposition (ASD) workshop April 4th – 5th, 2019 in IMEC

[Announcment LINK] ASM and IMEC are proud to announce that the 4th Area Selective Deposition (ASD) Workshop will be held on April 4th – 5th, 2019 in IMEC, Leuven (Belgium).

News tip by Henrik Pedersen - Tack så mycket

This workshop will bring together leading experts from both academia and industry to share their vision and results about: fundamental aspects of surface chemistry, new processes, metrology, fields of applications, technology needs and integration challenges for ASD. Based on a series of successful workshops at the North Carolina State University in 2018, Eindhoven University of Technology in 2017 and at IMEC in 2016, the two-days program will include invited and contributed speakers, a poster session and a reception on the evening of April 4th.

Tuesday, November 13, 2018

Spin Memory Teams With Applied Materials to Produce a Comprehensive Embedded MRAM Solution

FREMONT, Calif. — Spin Memory, Inc. (Spin Memory), the leading MRAM developer, today announced a commercial agreement with Applied Materials, Inc. (Applied) to create a comprehensive embedded MRAM solution. The solution brings together Applied’s industry-leading deposition and etch capabilities with Spin Memory’s MRAM process IP.

Key elements of the offering include Applied innovations in PVD and etch process technology, Spin Memory’s revolutionary Precessional Spin CurrentTM (PSCTM) structure (also known as the Spin Polarizer), and industry-leading perpendicular magnetic tunnel junction (pMTJ) technology from both companies. The solution is designed to allow customers to quickly bring up an embedded MRAM manufacturing module and start producing world-class MRAM-enabled products for both non-volatile (flash-like) and SRAM-replacement applications. Spin Memory intends to make the solution commercially available from 2019.

“In the AI and IoT era, the industry needs high-speed, area-efficient non-volatile memory like never before,” said Tom Sparkman, CEO at Spin Memory. “Through our collaboration with Applied Materials, we will bring the next generation of STT-MRAM to market and address this growing need for alternative memory solutions.”

“Our industry is driving a new wave of computing that will result in billions of sensors and a dramatic increase in data generation,” said Steve Ghanayem, senior vice president of New Markets and Alliances at Applied Materials. “As a result, we are seeing a renaissance in hardware innovation, from materials to systems, and we are excited to be teaming up with Spin Memory to help accelerate the availability of a new memory.”
About the PSC

NCD launch new updated website for ALD technology and equipment

Updated website NCD for ALD technology and equipment:

NCD updated its website with re-formation and company promotional video clip for the introduction and main equipment.

Saturday, November 10, 2018

Directed self-assembly of block copolymers for 7 nanometre FinFET technology and beyond

Globalfoundries recently announced that they have dropped all plans on putting 7 nm FinFET technology in production (LINK). Presumably this means that any advanced development for 7nm and beyond patterning has been stopped as well. In any case here is an excellent publication submitted before that announcment coming from the collaborative development from some of the most advanced semiconductor development centers in the USA - IBM Research at Albany NanoTech, TEL Technology Center, America in Albany, GlobalFoundries, and IBM Research TJ Watson in Yorktown Heights and IBM Research Almaden, San Jose.

They use different versions of directed self assembly (DSA) of block co-polymers (BCP) and spacer defined double patterning. ALD is used for spacers as well as very thin ALD SiN hardmasks. All this is all done without EUV like in the Samsung 2nd Generation 7nm FinFET or self aligned quadruple patterning (SAQP) like in the Intel 10 nm FinFET) - Impressive!

Some details are given in the Supplementary info (below).

Directed self-assembly of block copolymers for 7 nanometre FinFET technology and beyond

Nature Electronics volume 1, pages562–569 (2018)

Supplementary information : LINK (OPEN)

SAVE the DATE for the 2019 CMC Conference, scheduled for April 25-26 in the Malta/Albany, New York

SAVE the DATE for the 2019 CMC Conference, scheduled for April 25-26 in the Malta/Albany, New York area. Driven by the needs of the Critical Materials Council of semiconductor fabricators and associates (CMC), after three successful years, the CMC Conference is proven as one of the best forums for discussing actionable information relating to semiconductor fab materials.

The CMC Conference is where business meets technology. Find out which materials markets are growing fastest, the drivers behind those materials and which are being constrained or limited by local or international supply-chains. Click here to submit an abstract or get more information.

Interested in SPONSORSHIP, please contact Meena Sher by clicking here: Sponsorship Info Request

For an example agenda, from 2018, please click here.

The Critical Materials Council is a membership-based organization collectively working toward anticipating and solving Critical Materials Issues in a non-competitive environment by identifying/alleviating supply problems, sharing best practices, and working on industry standards for the benefit of the semi device fabrication community. The CMC is an integral part of TECHCET CA LLC, an advisory service firm focused on electronic materials supply-chains and markets.

Friday, November 9, 2018

ALD/ALE 2019 Call for Abstracts Deadline February 15, 2019

Imec to present scaled Superduper High-k Ruthenium/Strontium titanate capacitor at IEDM

Here is another interesting IEDM 2018 paper from Imec. It is a classical paper obn DRAM capacitor scaling featuring the almost impossible Superduper High-k Ruthenium/Strontium titanate capacitor! It is an ALD integration, the patterning the capacitor everything - no need to involve anyone else - it is up to the Litho and ALD people to get the job done.

Paper #2.7, "High-Performance (EOT<0.4nm, Jg~10-7 A/cm2) ALD-Deposited Ru/SrTiO3 Stack for Next-Generation DRAM Pillar Capacitor," M. Popovici et al, Imec)

I have not seen the abstract but it has been reviewed by CDRInfo (see paragraph below) and I am sure there will be more details available soon (LINK):

"Scaling DRAM Technology To 16nm And Beyond: DRAM memory technology is used in virtually all electronic systems because of its speed and density. DRAM memory comprises arrays of capacitor-transistor pairs which store data as electrical charge in the capacitor; the presence of charge indicates "1" and its absence "0." Manipulation of these digits is the basis of computer programming. It’s difficult to scale DRAM to the 16nm generation and beyond because of space limitations which make it hard to pack enough capacitance within the pitch. Imec researchers used an atomic layer deposition (ALD) process to pattern and build a novel 11nm pillar-shaped capacitor using new dielectric materials (SrTiO3, or STO). By tailoring the material properties of the capacitor and the SrRuO3 (SRO) epitaxial template on which it was grown, the researchers achieved a very high dielectric constant (k~118) and low electrical leakage (10-7 A/cm2 at ±1V). This means that pillar-shaped capacitors can be used instead of existing cup-shaped capacitors, without paying too great a penalty in terms of reduced data-storage capability. These results make the STO capacitors suitable for continued scaling for 16nm and smaller DRAMs."
Construction work at Imec, Leuven, June 2013. The tower looks a bit like a DRAM Capacitor but somehow I do not think that the architect know that and I bet they were working on Ru/STO ALD well before that!

Samsung will give insights to their 3nm CMOS technology at IEDM2018

The 64th IEDM conference will be held December 1-5, 2018 in San Francisco (LINK). This year Samsung will give insights to their 3nm CMOS technology that will feature the so calle gate-all-around (GAA) transistors. The GAA is trasistors ar realized by having channels made from horizontal layers of nanosheets that are completely surrounded by gate structures. 

Samsung has recently stated (LINK) that they have started wafer production on its new 7LPP node (FinFET). According to the press release the process uses EUV lithography technology and demonstrates that Samsung's Foundry can follow its roadmap reaching down to 3 nm.

Samsung Foundry Roadmap as shown at SFF Japan 2018.
Samsung refers to this architecture as a Multi-Bridge-Channel architecture, and claims "that it is highly manufacturable as it makes use of ~90% of the company’s existing FinFET fabrication technology, requiring only a few revised photomasks" (LINK). 
Paper #28.7, "3nm GAA Technology Featuring Multi-Bridge-Channel FET for Low-Power and High-Performance Applications," G. Bae et al, Samsung

Coverage, Composition and Band Gap Analysis of ALD-Grown Ultra Thin Films

[AZO Network News E-mail] Analyzing and developing ultra-thin film materials requires multiple data points typically from multiple instruments and techniques. Find out how one surface analysis instrument provides a complete picture of an ALD-grown ultra-thin film with information on composition and thickness, surface coverage and band gap measurements.


The Thermo Scientific™ Nexsa XPS System is not only a fully automated and intuitively programmed device, but has the advantage of being able to offer multi-technique analysis as well. This has made it a still more efficient and useful machine than its predecessor, the highly successful Thermo Scientific™ K-Alpha XPS system.

The Nexsa makes coincident analysis possible because it uses multiple methods, namely, UV photoelectron spectroscopy (UPS), ion scattering spectroscopy (ISS), reflected energy loss spectroscopy (REELS) and Raman spectroscopy. Taking advantage of this capability, the Nexsa was used to investigate various properties of a set of samples of HfO2. Each sample was made up of a thin layer of HfO2 laid down using a graded number of atomic layer deposition (ALD) cycles. Initially, the mass of Hf laid down on the substrate was measured quantitatively using XPS, as well as the thickness of the layers of HfO2 and SiO2. ISS and REELS were then used to carry out further analysis to obtain surface coverage and band gap readings respectively.

Full article : LINK

Introductory lecture on ALD available as "Panopto" lecture capture, and slides in SlideShare

Introductory lecture on ALD available as "Panopto" lecture capture, and slides in SlideShare by Prof. Riikka Puurunen, Aalto University, Finland.

SlideShare : LINK

Panopto Open Teaching Video : LINK

RASIRC : Effective Silicon and Metal Nitride Deposition at Reduced Temperature

[RASIRC Technical Brief] Silicon and metal nitrides are extensively used in the semiconductor industry in logic and memory chip manufacturing. PEALD approaches have found success in this area but carry significant risk of poor step coverage and surface damage in 3D and HAR structures. When non-line-of-sight deposition is required, thermal ALD is the preferred solution along with co-reactants that can deposit high quality films at temperatures below 430°C.
Source: RASIRC Technical Brief (LINK)

Imec to present Highest-Density 3DS Stacked FinFETs at IEDM 2018

Here is an interesting paper to be presented by Imec at the upcoming IEDM 2018 in San Fransisco. Imec has managed to stack the complete FinFET front end module on top of a "standard" bulk silicon FinFET Module demonstrating also good threshold voltage tuning, reliability and low-temperature performance. 

So just imagine if this would be used in high volume manufacturing - it would mean that all those ALD processes used in patterning and for the high-k metal gate module, spacers, local interconnect etc. etc. would come twice meaning a 2X need for ALD process chambers. And lets say you can run this twice - is there any reasons why you can´t run it yet another time? Woah!

Also as a note, Imec is here using a LaSiOx layer an a dipole inserted in the HKMG stack - presumably it is an ALD process since it will have to conformally coat this fins and ensure precise thickness control and uniformity.

So just enjoy seeing double - it is Friday!

Paper #7.1, “First Demonstration of 3D Stacked FinFETs at a 45nm Fin Pitch and 110nm Gate Pitch Technology on 300mm Wafers,” A. Vandooren et al, Imec

Highest-Density 3DS Stacked FinFETs: Imec researchers will report on 3D stacked FinFETs that have the tightest pitches ever reported in such a stacked architecture – 45nm fin pitch and 110nm gate pitch. The 3D architecture makes use of a sequential integration process yielding tight alignment between very thin top and bottom Si layers. The junction-less devices in the top layer were fabricated and transferred using low-temperature (≤525ºC) processes to avoid performance degradation, and a 170nm dielectric was used to bond the two wafers. The top layer is so thin that the bottom layer could be patterned right through it by means of 193nm immersion lithography, which connects the two via local interconnect. The researchers evaluated various gate stacks, ultimately choosing TiN/TiAl/TiN/HfO2 with a LaSiOx dipole inserted into the stack. The combination demonstrated good threshold voltage tuning, reliability and low-temperature performance.

At left above is a cross-sectional electron microscope image of the fabricated 3D stacked FinFETs along fins and across gates, showing the tight alignment achieved by the top processed layers (Gate Li1, Li2) toward the bottom layers. At right is a cross-sectional image of the final devices across fins with the gates covering the fins.

“First Demonstration of 3D Stacked FinFETs at a 45nm Fin Pitch and 110nm Gate Pitch Technology on 300mm Wafers,” A. Vandooren et al, Imec (IEDM 2018 Press kit)

Source: IEDM Press kit (LINK)

Tuesday, November 6, 2018

Beneq to present new automated wafer batch ALD platform at Semicon Europa

Beneq is presenting their new automated wafer batch ALD platform Beneq C2 at Semicon Europa in Munich November 13 to 16, 2108.

[From Beneq News Letter] Come and visit us in Semicon Europa and hear all about the latest version of our award-winning Beneq C2 automated wafer batch ALD platform with a special focus on emerging ALD markets, such as moisture barriers, passivation, insulators, anti-corrosion coatings for Power Si & WBG, RF GaAs, GaN and Si, MEMS sensors and actuators, Image sensors, LED and OLED.

Book a meeting with the Beneq team in Semicon Europa

La 4ème édition du colloque RAFALD aura lieu du mardi 6 au jeudi 8 novembre 2018 à Lyon.

La 4ème édition du colloque RAFALD aura lieu du mardi 6 au jeudi 8 novembre 2018 à Lyon.

1ère édition de l'école d'automne de l'ALD le mardi 6 novembre matin

Ce workshop dédié à la technologie ALD (Dépôt de Couches Atomiques - Atomic Layer Deposition) a pour but de fédérer une communauté française (industrielle et académique) pour initier la création d’un réseau national.

Pour cela nous organisons un colloque annuel réunissant tous les acteurs français actuels de l'ALD (universitaires et industriels) et également les techniciens, ingénieurs, doctorants, chercheurs et enseignants chercheurs potentiellement intéressés par l'ALD.

Ce colloque regroupe à la fois des sessions de formation et également des exposés scientifiques oraux et par affiches.
Public visé : Laboratoires académiques, industriels
Domaines visés : microélectronique, énergie, textile, biologie, nanotechnologies.
Niveau : Tous niveaux.


Review Article - ALD for oxide semiconductor thin film transistors

Review Article: Atomic layer deposition for oxide semiconductor thin film transistors: Advances in research and development

Jiazhen Sheng, Jung-Hoon Lee, Wan-Ho Choi, TaeHyun Hong, MinJung Kim, and Jin-Seong Park
Journal of Vacuum Science & Technology A 36, 060801 (2018)


Sunday, November 4, 2018

Foundry investment in 5nm has started according to ASM

Here are some take aways form the ASM International Earnings Call for Q3/2018 [Full transcript by Seeking Alpa, LINK]. Interestingly there was no talk about "The end of Moore´s Law" at all. On the contrary ASM see that Foundry investment in 5nm has started and will increase in 2019 and incearsed number of additional new ALD applications will be deployed.

For ASM the equipment sales were led by their ALD business, but they also recorded healthy sales levels in our other product lines. By industry segment, revenue in the quarter was led by foundry, followed by memory and then logic. Within memory the larger part of sales was related to DRAM investments, while NAND sales decreased compared to the second quarter. 
"The structural outlook for the ALD market remains strong. ALD continues to be a key enabler of Moore's Law. An increasing number of ALD steps will be needed to help create the smaller geometries, new materials, and more complex device architectures that are on our customers' roadmap." 
- Chuck del Prado, President and CEO of ASMI.
  • Spending in the advanced logic segment is clearly higher in 2018 compared to last year.
  • Foundry spending is lower this year and is driven by further 7-nanometer investments as well as the first investments in 5-nanometer. 
  • Investments for the 5-nanometer node are likely to further increase in the course of next year.
  • ASM expectation is that the 5-nanometer foundry node is going to be an important transition for the company, with good opportunities to expand with multiple new ALD applications/layers. 
  • The DRAM segment is to show solid growth for the wafer equipment market in in 2018. For ASM, DRAM is also one of the drivers behind higher sales this year. ASM remain strongly focused on broadening our position in DRAM to new ALD solutions.
  • 3D NAND spending is coming down significantly in the second half of this year. Also, for the full year of 2018 NAND spending is expected to be lower.
  • A recovery in investments in the NAND segment will likely be driven by the transition to the next device generations of 90-plus layers. These next device generations are expected to need an increased number of advanced single wafer ALD applications.

LIST invites you to the EuroCVD 22 – Baltic ALD 16 | 2019 conference in Luxembourg on 24-28 June 2019

AP Systems to supply Thin Film Encapsulation to Samsung Display QD-OLED line

DIGITimes China reports [LINK] that Samsung Display is building a large-scale quantum dot organic light-emitting diode (QD-OLED) panel pilot production line. The line is scheduled to be finished in December 2018 and will be activated after 6 months (mid 2019). According to the report the supply ration from Korean equipment manufacturers has increased significantly for this line.

As an example the the report claims that AP Systems beat Applied Materials to supply the Thin Film Encapsulation (TFE) equipment. AP Systems has previously supplied TFE equipment for the 8th generation RGB OLED TV panel production line (V1) of Samsung Display. In the past Samsung Display has used TFE equipment supplied by Applied Materials in the 6th generation flexible OLED production line, but has now switched and for its AP Systems in this 8th generation QD-OLED test production line.

Also according to the report, the PECVD equipment will be supplied by Wonik IPS from Korea whereas the blue OLED material evaporation equipment will be supplied by Canon Tokki (Japan) and the red and green QD material inkjet printing machine will come from Kateeva (USA).
The KORONA™ TFE System running PEALD with "Multi-linear Nozzle" technology and ICP antenna design technology (high density/low damage plasma).
For TFE AP Systems are using a Plasma enhanced Atomic Layer Deposition (PEALD) technology on their KORONA™ TFE System. The system is capable of depositing a film structure that acts as a sealant to prevent oxygen and moisture penetration into OLED device. Based on a 1000Å, SiNx/SiOx multi-layer structure the Water Vapor Permeability is less than 5e-5 g/m2/day.
According to AP Systems they can also apply the film as a flexible sealant to realize flexible, rollable, and foldable displays. 

Thursday, November 1, 2018

Welcome To The World's First Open ALD Blog Platform: BALD Engineering Guest Blog

Are you willing to get recognition and attention in the ALD community? Do you hold ALD news, articles, presentations, podcasts, videos, conference/workshop/tutorial invitation or promotion in your pocket that you want to share with the ALD community?

Then, here is the world's best ALD platform: BALD Engineering Guest Blog. No matter at what stage you are in your career; this is for you if ALD or ALE is your cup of tea. Write your own blog and share your own content or interesting news on the BALD Engineering Guest Blog; also, feel free to promote it in your social media network.

Content Guidelines:

- Up to 1000 words, including html-links.
- Up to 3 images (without copyright violation).
- References as links or as DOI number for journal references.
Keep the most relevant and attention grabbing image at first as it will be the thumbnail picture for your post while sharing in your social media platforms (LinkedIn, Twitter).

Blog ending includes:

Guest blog by [first name] [last name], [affiliation] (optional)
Location: [city], [country]
Web page: (optional)
LinkedIn link: (optional)
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You can also submit:

Videos through YouTube stream or Twitter tweet or LinkedIn embedded feeds.

How to Submit:

Click on to directly write or copy+paste the content or attach content file (up to 10 MB in size).


This is the first version of the open guest blog. Therefore, we are constantly looking forward to get feedback and suggestions to make it even handier for the users and to widespread it further. Please write your comments to us on or through any social media.