Showing posts with label Tokyo Electron. Show all posts
Showing posts with label Tokyo Electron. Show all posts

Friday, September 15, 2023

Tokyo Electron Integrated Report/Annual Report 2023 available for download

Tokyo Electron (TEL) issues an integrated report for the purpose of reporting our medium- to long-term profit expansion and continuous corporate value enhancement to their stakeholders.

As they celebrate their 60th anniversary this year, the 2023 report looks back at the history of our business expansion. It also details our efforts to continuously create value by the value chain of their business activities anchored around material issues, in conjunction with their sustainability initiatives.

For anyone involved in the semiconductor industry or those eager to gain fresh perspectives in this dynamic field, this report is a must-read. It not only showcases TEL's history and strategies but also sheds light on industry trends, sustainability practices, and the exciting developments shaping the future of semiconductor technology. Dive into this comprehensive report and unlock valuable knowledge about TEL's journey and the semiconductor industry at large.

TEL also have great training material and a Nanotech Museum:

Monday, August 28, 2023

The Future of Nanoimprint Lithography: Exploring Possibilities and Challenges for High-Volume Production

Nanoimprint lithography (NIL) has emerged as a promising technique for the replication of intricate nano-scale features, offering higher resolution and uniformity compared to traditional photolithography methods. As semiconductor technology advances towards smaller and more complex structures, NIL holds the potential to revolutionize high-volume production processes. In this blog post, we'll delve into the current status of nanoimprint lithography and the possibilities it presents for future high-volume productions, as well as the main issues and concerns that need to be addressed.

NIL utilizes a process where a patterned mask is brought into contact with a resist-coated substrate. The resist fills the relief patterns in the mask through capillary action, creating precise nano-scale features. With a focus on simplicity and cost-effectiveness, NIL doesn't require the complex optics found in traditional photolithography, making it an attractive option for semiconductor memory applications.

Early work on combining NIL and Atomic Layer Etching by AlixLabs Founders

AlixLabs (  founders and Lund Nano Lab (Lund University, Sweden) collaborated 2018 to exploit Atomic Layer Etching (ALE) for improved NIL quality and resolution. ALE involved Cl2 monoatomic layer adsorption on silicon, followed by controlled Cl2-modified silicon layer removal using argon bombardment. This precision process allowed diverse nanopatterns to be etched onto silicon wafers with electron beam lithography. The treated wafers served as robust nanoimprint stamps in a thermal process, transferring features as small as 30 nm into a poly(methyl methacrylate) layer. ALE's potential for ultrahigh-resolution nanoimprint stamp fabrication advances nanofabrication techniques significantly.

Most Recent Achievements:

Recent study by TEL and Canon have demonstrated NIL's resolution capabilities of better than 10 nm, positioning the technology as a candidate for printing multiple generations of critical memory levels using a single mask. The potential to eliminate material waste by applying resist only where necessary adds to its appeal. Moreover, the simplicity and compactness of NIL equipment allow for clustered setups, enhancing productivity.

NIL Addressing Challenges in DRAM Scaling:

Dynamic Random Access Memory (DRAM) memory faces the challenge of continued scaling, with roadmap targets aiming at half pitches of 14 nm and beyond. The complexities of achieving tighter overlays, greater precision in critical dimensions, and edge placement errors demand innovative solutions. In DRAM fabrication, overlay requirements are even more stringent than in NAND Flash, with an error budget of 15-20% of the minimum half pitch.

Edge Placement Error (EPE):

EPE, the difference between intended and printed features, poses a significant challenge in modern semiconductor manufacturing. The intricacies of multiple patterning schemes and intricate device layouts contribute to EPE's complexity. Ensuring accurate placement of features is critical for maintaining device yield and performance.

The Quasi-Atomic Layer Etch (Quasi-ALE) process

The process is a specialized etching technique employed in advanced semiconductor manufacturing, particularly in processes like Nanoimprint Lithography (NIL). Quasi-ALE combines elements of Atomic Layer Etching (ALE) and conventional etching methods to achieve precise and controlled material removal. In the context of Nanoimprint Lithography, Quasi-ALE is used to etch materials with exceptional precision, targeting nanoscale features while minimizing damage to the surrounding areas. It involves a cyclic process where alternating etching and passivation steps are applied to the substrate. Each cycle removes a controlled layer of material, ensuring highly uniform etching and minimal lateral etch. One can discribe Quasi-ALE as a more productive way of performing ALE.

The key steps of the Quasi-ALE process typically involve:

1. Etch Step: During this step, a reactive gas is introduced into the etch chamber, which chemically reacts with the material to be removed. This reaction results in the selective removal of the material layer.

2. Passivation Step: In this step, a passivating species is introduced, forming a protective layer on the substrate surface. This layer prevents further etching and preserves the material beneath.

3. Purge and Repeat: The chamber is purged to remove any excess gases, and the process is repeated in a cyclical manner. Each cycle removes a controlled atomic layer of material.

Quasi-ALE is particularly advantageous for applications requiring high precision and control, such as in Nanoimprint Lithography, where maintaining accurate pattern dimensions and minimizing damage is critical. By combining the benefits of both ALE and traditional etching, Quasi-ALE enables advanced semiconductor manufacturing processes to achieve unprecedented levels of accuracy and uniformity.

Addressing EPE with Nanoimprint Lithography:

Researchers are actively exploring techniques to mitigate edge placement errors in nanoimprint lithography. This includes focusing on overlay accuracy, critical dimension uniformity (CDU), and local CDU. Compensatory methods such as dose control and reverse tone pattern transfer are being investigated to improve CDU and minimize errors.

The Role of Dose Control:

Varying the exposure dose offers a means of achieving small shifts in critical dimensions. Initial studies suggest that dose variations could lead to CD shifts of one to 2 nm. This strategy holds promise for enhancing CDU in the imprint process.

Reverse Tone Pattern Transfer:

Reverse tone processes, involving spin-on hard mask (SOHM) application and etch-back, offer an alternative approach to pattern transfer. While this method provides advantages such as reduced resist erosion and improved wall angles, trade-offs between CDU and line width roughness (LWR) need to be addressed.

Looking Ahead: The Possibilities and Challenges:

While NIL exhibits impressive potential, there are key challenges to overcome before it can be effectively integrated into high-volume semiconductor manufacturing. Ensuring precise overlay accuracy, managing complex CDU requirements, and effectively addressing edge placement errors remain pivotal. As the industry strives to achieve the roadmap's aggressive scaling targets, the evolution of nanoimprint lithography will undoubtedly play a crucial role.

Nanoimprint lithography is poised to reshape the semiconductor manufacturing landscape, offering higher resolution and cost-efficiency compared to traditional methods. With ongoing research and development, addressing challenges such as overlay accuracy, CDU, and EPE, the path to successful high-volume production through NIL seems promising. As technology continues to advance, the journey towards perfecting nanoimprint lithography is an exciting one, holding the potential to shape the future of chip fabrication.

Tokyo Electron (TEL): 

TEL specializes in Nanoimprint Lithography (NIL) technology, offering precision equipment, advanced etching solutions, and expertise in process control. They excel in alignment, overlay correction, CDU management, and etching technology.

TEL has previously demonstrated that for sub 7  nm CMOS technology, ALE and ALD integration improves SAC and patterning processes, achieving precise CD shrinking and enhanced selectivity.


Canon contributes to Nanoimprint Lithography (NIL) advancement by leveraging TEL's strengths in alignment, overlay correction, CDU management, and advanced etching solutions. They integrate these capabilities with the Reverse Tone Pattern Transfer, ensuring precise pattern replication and fidelity. Canon's focus on innovation drives high-resolution, cost-effective solutions for semiconductor manufacturing.

Canon has introduced a groundbreaking solution in the field of semiconductor technology with the development of the world's first mass-production equipment called the "FPA-1200NZ2C." This innovative tool utilizes nanoimprint lithography, a cutting-edge technique that involves imprinting nanometer-scale mask patterns onto substrates. By adopting this novel approach, Canon aims to overcome the limitations of conventional miniaturization methods. The FPA-1200NZ2C is already in use by Toshiba Memory, a prominent semiconductor memory manufacturer. This advancement marks a significant step forward in semiconductor manufacturing, enabling the creation of more intricate and advanced circuit patterns.


High-Definition Nanoimprint Stamp Fabrication by Atomic Layer Etching — Lund University

Nanoimprint post processing techniques to address edge placement error (

Nanoimprint Lithography | Canon Global

FPD Lithography Equipment | Canon Global

Benefits of atomic-level processing by quasi-ALE and ALD technique - IOPscience

Acknowledgement :

Thanks for sharing the SPIE article on LinkedIn and giving insights Frederick Chen!

Tuesday, August 22, 2023

Tokyo Electron's Q1 2024 Earnings Call Unveils Resilient Performance and Strategic Focus

Tokyo Electron Limited (OTCPK: TOELF), a prominent semiconductor equipment manufacturer, recently held its Q1 2024 Earnings Conference Call, revealing a resilient financial performance and strategic initiatives. Key representatives including Toshiki Kawai (CEO) and Hiroshi Kawamoto (Finance Division GM) presented the company's consolidated financial summary and insights into the business environment.

Financial Highlights:
- Q1 2024 sales reached ¥391.7 billion, showing a 29.8% decline due to reduced customer WFE spending.
- Gross profit at ¥162.3 billion and operating income at ¥82.4 billion represented drops of 35.5% and 46.0% from the prior quarter, respectively.
- Tokyo Electron invested in R&D, allocating ¥43.6 billion, while capital expenditures amounted to ¥39.3 billion, reflecting its commitment to innovation and expansion.

Market Outlook:
- Tokyo Electron discussed the WFE market's projected growth to $200 billion within 2024-2025.
- The company foresees opportunities in server, leading-edge CPU, DRAM, NAND, GPU for AI, HBM, power semiconductors for EV, and more.

Fiscal 2024 Estimates:
- Financial estimates remain unchanged, with ¥580 billion and ¥690 billion projected for the first and second halves of FY 2024, respectively, in SPE new equipment sales.
- Tokyo Electron aims for record-high R&D investment of ¥200 billion and CapEx of ¥124 billion to align with growth projections.

Share Repurchase and Dividend:
- Tokyo Electron's ongoing share repurchase program bought 3,069,200 shares worth ¥60.9 billion by July 31.
- The company plans to continue repurchase up to ¥120 billion by December 31, 2023.
- A consistent dividend forecast maintains a full-year dividend per share of ¥320.

Tokyo Electron's Q1 2024 Earnings Call provided a comprehensive overview of its robust performance and strategic direction, positioning the company to capitalize on growth opportunities in the semiconductor sector.

Monday, June 12, 2023

Tokyo Electron Introduces Breakthrough Memory Channel Hole Etch Technology for 3D NAND Flash, Reducing Global Warming Potential by 84%

Tokyo Electron's Innovative Etch Process Enables Ultra-fast 10-µm-deep Etching for 3D NAND Flash with Over 400 Layers, Showcased at Symposium on VLSI Technology and Circuits

Tokyo Electron (TEL) has achieved a significant technological milestone by developing a cutting-edge etch technology capable of creating memory channel holes in advanced 3D NAND devices with over 400 layers. This breakthrough process, pioneered by the development team at Tokyo Electron Miyagi, leverages cryogenic temperatures to achieve exceptionally high etch rates, marking the first time dielectric etch application has been utilized in this temperature range.

The groundbreaking technology not only enables the etching of memory channel holes up to 10 µm deep with a high aspect ratio in just 33 minutes but also boasts an impressive 84% reduction in global warming potential compared to previous methods. The etched structure exhibits well-defined geometry, as demonstrated by cross-section SEM and FIB cut images.

Cross section SEM image of memory channel hole pattern after etching, and FIB cut image at the hole bottom.

TEL's research team behind this groundbreaking technology will present their findings at the prestigious 2023 Symposium on VLSI Technology and Circuits, a renowned international conference on semiconductor research. Their contribution showcases the potential for even larger capacity 3D NAND flash memory.

The presentation, titled "Beyond 10 µm Depth Ultra-High Speed Etch Process with 84% Lower Carbon Footprint for Memory Channel Hole of 3D NAND Flash over 400 Layers," will be delivered by Y. Kihara, M. Tomura, W. Sakamoto, M. Honda, and M. Kojima from Tokyo Electron Miyagi Ltd. The session, scheduled for Tuesday, June 13, from 2 p.m. to 3:40 p.m., will take place in the NAND Flash section of the Technology Session 3 [Shunju II].

For detailed event information about the 2023 Symposium on VLSI Technology and Circuits, please click here. Stay tuned for TEL's technology presentation, which combines semiconductor advancements and environmental protection efforts. 2023 Symposium on VLSI Technology and Circuits

Source: Tokyo Electron Develops Memory Channel Hole Etch Technology That Enables Ultra-fast 10-µm-deep Etching for 3D NAND Flash with Over 400 Layers and an 84% Reduction of Global Warming Potential | News Room | Tokyo Electron Ltd. (

Sunday, September 4, 2022

Tokyo Electron is forcastiong high continued sales in semiconductor equipment sales 2023 - slow down in DRAM

Tokyo electron forecast for FY2023 SPE Division New Equipment Sales Forecast - DRAM is retracting in 2023 but you can´t say that about Logic and Non-Volatile Memory (3DNAND Flash). Full power ahead for ALD and its friends!

One good freind of ALD is Etch. Tokyo Electron is spending quite some development Yen Billions by building a new facility just for etch development.

Thursday, April 8, 2021

Why China denied Applied Materials take over of Hitachi Kokusai

According to a recent analysis by Robert Castellano (Seeking Alpha/The Information Network LINK), Hitachi Kokusai holds a strong position in tube/non-tube LPCVD and oxidation/diffusion semiconductor equipment. For some time Applied Material has planned the acquisition of Kokusai that would have increased its global market share, for silicon wafer processing equipment by adding a big segment that it does not have in its product portfolio - LPCVD, Diffusion, and ALD Furnaces. According to the market assessment, Hitachi Kokusai holds a leading market share in this segment over No. 2. Tokyo Electron. 

Castellano brings up the interesting observation that "China blocked Applied Materials' acquisition of Kokusai while permitting the Marvell-Inphi deal the same week". Basically meaning that there are more than just US-China Trade issues behind the decision. He concludes that "China is developing a home-grown equipment industry infrastructure, and the deal would impede on that effort." and follows up by breaking up the segments and global competitive situation as below.

Summary by Castellano of China OEM active in LPCVD, Diffusion, and ALD segments vs. the global leaders

China’s NAURA makes oxidation and diffusion furnaces and its products have captured a significant share (40-50%) of YMTC’s thermal process equipment purchases, per our channel checks. In RTP, major players include Applied Materials, Tokyo Electron, and Mattson Technology.

NAURA is developing etchers and deposition equipment for 7nm and 5nm nodes. NAURA has a large product offering, and its customers consist of SMIC, Hua Hong, YMTC, and GTA Semiconductors.

NAURA also makes thermal furnaces and has a 45% share of China’s memory maker YMTC purchases. Whereas NAURA sold 8 etch systems and 6 CVD and ALD deposition systems to Chinese semiconductor companies, the company sold 34 furnaces in 2019 as well as 16 cleaning systems.

Shenyang Piotech also supplies PECVD and ALD deposition equipment. Piotech received orders for 4 PECVD (for SiN, SiO2) systems from YMTC, and is also receiving repeat orders from Hua Hong, and SMIC.

The size of the semiconductor equipment market and the small share China's equipment suppliers currently enjoy compared to foreign suppliers (source: The Information Network LINK)

Wednesday, March 24, 2021

Canon, SCREEN and Tokyo Electron to join Japan advanced chipmaking project for 2nm

Canon has partnered with Tokyo Electron and Screen Semiconductor Solutions to develop advanced chipmaking production technology with support from the Japanese government according to a report by Nikkei Asia.

♦ The $386mil USD funding from the Japanese government is through the National Institute of Advanced Industrial Science and Technology, along with the Ministry of Economy, Trade and Industry (METI).
♦ Japans semiconductor production industry has lost ground in recent years to Taiwanese chipmakers and companies like Intel.
The goal is to develop and implement a 2-nanometer or smaller process for chips by the mid-2020s.

Source (Paywall): LINK

Tokyo Electron semiconductor fab professionals shuffling wafers (credit: Tokyo Electron)

Wednesday, February 3, 2021

LIVE Stream - Advanced Process Technologies to Enable Future Devices and Scaling (invited), Rob Clark Tokyo Electron

SEMICON Korea SEMI Technology Symposium (STS) 2021 - The invited presentation titled "Advanced Process Technologies to Enable Future Devices and Scaling" can be streamed starting Feb. 3 in S. Korea (2/2 evening U.S.). 

This is an overview of new processing technologies required for continued scaling of leading-edge and emerging semiconductor devices. The main drivers and trends affecting future semiconductor device scaling are introduced to explain how these factors are influencing and driving process technology development. Topics explored in this presentation include atomic layer deposition (ALD), atomic layer etching (ALE), selective deposition and etching. In order to enable self-aligned and multiple patterning schemes as well as emerging devices for future manufacturing, atomic level process technologies need to be leveraged holistically. Real-world examples of current and future integration schemes, as well as emerging devices, will be presented and explained so that attendees can understand how advanced process technologies will be used in future device manufacturing as well as what benefits and tradeoffs may be encountered in their use.

Saturday, November 28, 2020

Applied Materials will regain its No. 1 ranking in the semiconductor equipment market in 2020 from ASML

According to recent published data by The Information Network (Seeking Alpha LINK), Applied Materials will regain its top ranking in the semiconductor equipment market in 2020 from ASML. Fab equipment spend in 2020 was enhanced from pull-ins of sales into China and Taiwan, with 3Q QoQ increases of 22.5% and 36.2%, respectively.

As is well known ASML and Applied Materials does not compete in their  business segments, Lithography (ASML) resp. Deposition & Etch (Applied Materials). Applied Materials has a number 1 spot in PVD, CVD, Epi, CMP and Implant/Doping. However, business segments where Applied Materials so far has not been successful to reach a top 3 position in the past years include:
  • Atomic Layer Deposition
  • Furnace 
  • Dielectric Etch  
  • Spray Processing
  • Dielectric Etch (including ALE)
  • Wet Stations
As is known, Applied Materials have several times made very serious attempts to enter the ALD segment, but failed several times to compete with ASMI, Tokyo Electron and the South Korean OEMs (Jusung Engineering, Wonik IPS and Eugene Technology. In 2019 Applied Materials announced that it will acquire Japanese Kokusai (LINK) but the final agreement is yet not settled. If successful Applied will have an opportunity to kill 2 birds with one stone:

1. Move in to top 3 spot in ALD
2. Take number 2 spot in Furnace business

Table based on information and own assumptions in the article (Seeking Alpha LINK)

Sunday, July 7, 2019

Rapid and Selective Deposition of Patterned Thin Films on Heterogeneous Substrates via Spin Coating

[Tokyo Electron] Researchers at UC Santa Barbara along with TEL and SRC have collaborated to develop new methods for selective spin coating. With wide-ranging applications in the future of semiconductor patterning as device makers are challenged to build more complex transistors and simultaneously lower costs. 

They demonstrate that accurate control over the process parameters allows incomplete trichlorosilane self-assembled monolayers (SAMs) to induce spin dewetting on both homogeneous (SiO2) and heterogeneous (Cu/SiO2 or TiN/SiO2) surfaces. Under optimal conditions, spin dewetting on line–space patterns results in the selective deposition of polymer over regions not functionalized with SAM.  

Source: "Rapid and Selective Deposition of Patterned Thin Films on Heterogeneous Substrates via Spin CoatingLINK

Saturday, March 16, 2019

VLSIresearch released its list of the top Semiconductor Equipment Suppliers for 2018 shown big wins for Japanese OEMs

VLSI Research report well above average growth for ASML (NL), Tokyo Electron (JPN), Advantest (JPN), Kokusai (JPN), Daifuku (JPN) and Canon (JPN) so a big win for Japan and the Netherlands last year. All Japanese companies outperform the market growth 2018!

Dan Hutchenson: "VLSIresearch released its list of the top Semiconductor Equipment Suppliers for 2018. Notable shifts were TEL passing Lam to take the top spot. Advantest past Screen for 7th with the highest growth of any chip equipment manufacturer. While ASM Pacific passed SEMES. For details, see:

Most growth is seen in Litho as for each Immersion or EUV tool that is installed a bunch of Tokyo Electron tools come as well like e.g. the TEL Track platform.

With respect to ALD, judging by ASMI, TEL and Kokusai it seems that ALD was able to capture all of the growth in 2018 and maybe a bit more. In April the Japanese companies start their 2018 annual reporting so then we will know more for now we have the ASMI report to study (LINK).

Wednesday, May 2, 2018

Tokyo Electron is Challenging ASM International as The Leader in ALD Market share

Tokyo Electron recently (APR 25, 2018) presented their Q1/2018 numbers to share holders and released a slide deck (LINK) with some interesting new numbers on market share. For the first time it seems that another OEM is up there seriously challenging ASM International on the No.1 spot in ALD Equipment market share. ASM International has dominated the ALD segment with a share of >70% in 2014, but this share has slipped down year by year and they have lost their market share to well below 50% in 2017 due to strong competition in a rapidly expanding ALD market from Tokyo Electron, Lam Research, Kokusai, The Korean OEMs (Jusung Engineering, Wonik IPS and Eugene Technology) and also to some extent by Applied Materials.

According to the latest estimate based on Gartner research (released April 18, 2018), Tokyo Electron as of 2017 holds a 31% total market share of ALD wafer based processing equipment. That should include all wafer based ALD platforms, however some companies hide their ALD revenue in the CVD segments so you can not know for sure if you don´t know the data in detail. The segments are:
  • ALD Tube - Large batch furnaces, typically loading 100 or more wafers
  • Single wafer platforms
  • Multi wafer platforms, spatial or multi station

TEL Market share for 2017, Based on Gartner research (TEL Q1/2018 Earnings call slide deck) 

One explanation why Tokyo Electron has taken market share in ALD is because of a lot of the recent investment is coming from DRAM and 3DNAND Fabs and not Logic Fabs (see below). Traditionally Tokyo Electron has been much stronger in Memory than ASM International. Here the Japanese have very attractive tools for commodity product manufacturing (DRAM and Flash memory chips) like their ALD Large Batch Furnaces and relatively new and successful NT333 Spatial ALD platforms.
TEL sales their FY 2016 to 2018 by segment (TEL Q1/2018 Earnings call slide deck) 

Also interesting is that Tokyo Electron presents a rather bright future with growth not only in DRAM and 3DNAND but also in Logic due to 10/7nm investments from the IDMs and Foundries.

Saturday, March 31, 2018

Tokyo Electron reports on patterning technology for advancements in scaling

If you are interested in the latest patterning technology you should read this excellent online publication by Ken Nawa at the Process Integration Center, Tokyo Electron. Tokyo Electron is one of the top supplier for wafer based advanced etch, deposition and clean (and more) tools for the semiconductor industry. Besides the evolution of semiconductor by scaling technology, he covers all the latest advanced technologies:
  • Introduction of advanced patterning technology and challenges
  • SADP – Scaling by thin film formation on sidewall  
  • SAQP – Scaling by extending SADP technology 
  • SAB – Scaling by etch selectivity to multiple materials

Full article: LINK 

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