Tuesday, November 21, 2023
Revolutionizing Power Technology: Intel's Integrated CMOS Driver-GaN (DrGaN) Power Switch for Enhanced Efficiency and Density in Data Centers and Networks
Sunday, October 22, 2023
Hamas' Brutal Attacks on Israel Could Disrupt Global Tech Supply Chain and Intel's Expansion Plans
Saturday, October 21, 2023
Intel Unveils Breakthrough 3D CFET Design at IEDM: Setting the Stage for Next-Gen Compact and Efficient Electronics
Intel researchers developed a 3D monolithic CFET device* with 3 n-FET nanoribbons atop 3 p-FET nanoribbons, separated by 30 nm gap. This industry-first device enabled the creation of functional inverters at a 60 nm gate pitch. Notably, it incorporated vertically stacked dual-Source/Drain epitaxy, dual metal work function gate stacks, and backside power delivery with direct device contacts. They also introduced a nanoribbon "depopulation" method for varying n-MOS/p-MOS device numbers. This research advances the understanding of CFET scalability for logic and SRAM applications and highlights key process enablers. The paper will be presented at the upcoming IEDM conference in San Francisco.
Comment: The stacked CMOS inverter at a 60 nm gate pitch represents an advancement in semiconductor design, allowing for denser circuits. The 60 nm distance between gates indicates a highly miniaturized design. Power vias provide vertical power connections to different layers, while direct backside device contacts enhance efficiency and heat dissipation. This development offers a glimpse into the future electronic devices being more compact, efficient, and high-performing than deploying "planar" designs in one layer like the FinFETs and GAA-FETs of today.
ALD plays a key role in manufacturing 3D monolithic CFET devices by assisting in crafting the architecture and providing atomically precise and even thin film layers at small scales. ALD ensures even coverage, which is important for 3D designs, especially on vertical areas and inside deep gaps. It's used to put down important materials in transistor gate stacks (High-k/Metal Gates or HKMG), as well as barrier and seed layers. ALD also helps in doping (SSD - solid state doping), which changes how semiconductors behave, and in creating spacers, important for separating and defining parts of transistors. In brief, ALD helps improve the CFET design and its overall performance.
* A 3D monolithic CFET device combines three-dimensional stacking and the Complementary Field-Effect Transistor (CFET) design within a single semiconductor structure. This approach vertically integrates both n-type and p-type transistors on the same substrate, promoting tighter integration and reduced interconnect delays. By leveraging the complementary operation of CFET and the benefits of 3D stacking, the device aims to enhance performance, miniaturization, and efficiency in semiconductor technology.
Friday, October 20, 2023
The Semiconductor Showdown: TSMC's GAA FETs vs. Intel's RibbonFET
As the semiconductor race intensifies, both companies are heavily invested in outpacing each other, with TSMC focusing on technology maturity and cost-effectiveness, and Intel aiming to regain its technology leadership. The dynamics between these tech giants will shape the semiconductor industry's future.
Comparison of Advanced Semiconductor Technology Nodes: TSMC N3P & N2 vs. Intel 20A & 18A, highlighting the competitive landscape of the semiconductor industry for the years 2024-2026 based on Toms Hardware article below.
Sources:
TSMC: Our 3nm Node Comparable to Intel's 1.8nm Tech | Tom's Hardware (tomshardware.com)
Intel and TSMC company web pages
Wednesday, September 13, 2023
Intel to Sell 10% Stake in IMS Nanofabrication to TSMC for $4.3 Billion
Wednesday, September 6, 2023
ASML Remains on Track to Deliver High NA EUV Machines in 2023
Friday, June 30, 2023
Intel Takes Strategic Steps to Regain Semiconductor Chip Leadership
Diversifying into New Markets
Emulating the TSMC Playbook
Competing for Internal Fab Capacity
Reviving Manufacturing Prowess
Intel is expanding as a foundry in Europe
Conclusion
Tuesday, May 4, 2021
CBS 60 Minutes - Chip shortage highlights U.S. dependence on fragile supply chain
- Pat Gelsinger: 25 years ago, the United States produced 37% of the world's semiconductor manufacturing in the U.S. Today, that number has declined to just 12%
- Within the world of global collaboration, there's intense competition. Days after Intel announced spending $20 billion on two new fabs, TSMC announced it would spend $100 billion over three years on R&D, upgrades, and a new fab in Phoenix, Arizona, Intel's backyard, where the Taiwanese company will produce the chips Apple needs but the Americans can't make.
Taiwan-based TSMC, which supplies microchips for most U.S. cars, tells 60 Minutes it will be caught up with car chip production by the end of June. So, does that mean the dire shortage will end in two months? Well, not quite. https://t.co/Wj1yFffaKS pic.twitter.com/Zx3dnRwU0o
— 60 Minutes (@60Minutes) May 2, 2021
Wednesday, March 24, 2021
Intel is spending $20 billion to build two new chip plants in Arizona
Alex Tregub, PhD Staff Engineer Intel Corporation "From Egyptian Royal Cubit to SEMI Guides for CMP consumables – Industry Standards"
- Intel invests $20 billion in two Arizona factories, 7nm chips coming in 2023
- Intel announces steps to boost chip manufacturing
- ‘Intel is back:’ New CEO’s plan to make chips for others excites investors
- Stocks making the biggest moves after the bell: GameStop, Adobe, Intel
- Intel is spending $20 billion to build two new chip plants in Arizona
Saturday, November 28, 2020
Intel remains in the lead in 2020 semiconductor sales
Thursday, November 19, 2020
Intel to present 3D stacked Nanoribbon Transistors for Continued Moore’s Law Scaling at IEDM 2020
Paper Information (IEDM 2020) : LINK
·
(1) shows
the evolution of transistor architectures from planar, to FinFETs, to
nanoribbons and to a 3D CMOS architecture.
·
(2) (a)
shows a 3D schematic diagram of stacked CMOS Si nanoribbon transistors with
NMOS on PMOS, (b) describes the process flow; (c) is a TEM image of a stacked
multiple-nanoribbon CMOS inverter with a 40-nm gate length and inner (Vss)
and outer (Vcc) contacts, a common gate input (VIN) and
an inverter output node (VOUT); while (d) is a TEM image of two Si
NMOS nanoribbons atop 3 Si PMOS nanoribbons.
·
(3) (a)
is a process flow of the vertically stacked dual S/D EPI process, while (b)
shows P-EPI selectively grown on the bottom three nanoribbons, (c) shows N-EPI
selectively grown on the top two nanoribbons, and (d) features TEM and EDS
images showing selective N-EPI and P-EPI growth on the stacked nanoribbon
transistors.
·
(4)
(a) is a process flow of the vertically stacked dual metal gate process; (b) is
a TEM image and (c, d) are EDS images of the dual metal gate with N-WFM (WFM =
work function metal) on the top two nanoribbons and P-WFM on the bottom three
nanoribbons.
Friday, September 18, 2020
Process Power: The New Lithography - Advanced Energy
Here is a very insightful article by PETER GILLESPIE, VP & GM, Semiconductor Products, Advanced Energy Industries on the progress of Plasma RF Generators and Matching Networks. The article looks at applications in 3DNAND High Aspect Ratio Contacts (HARC) and Logic FinFET transitor fabrication using reactive ion etching and plasma CVD using the latest plasma technology. This is a an articel in a series of three in SEMICONDUCTOR DIGEST entitled “Process Power Steps Out from the Shadows,” looking at the leading edge technology node process challenges to highlight key drivers that are fundamentally transforming the role and importance of process power.
Process Power: The New Lithography (SEMICONDUCTOR DIGEST, LINK)
"Evolution of RF power supplies (plasma generators) and RF matching networks. Today’s RF power delivery systems are highly sophisticated with frequency tuning, complex pulsing regimes, and agile micro-second response." (Below)
Wednesday, September 2, 2020
TechInsights’ Memory Process: 3D NAND Word Line Pad webinar
TechInsights’ ‘Memory Process: 3D NAND Word Line Pad‘ #webinar compares 9x-layer 3D NAND devices from major manufacturers and discusses the process sequence with emphasis on the word line pad (WLP). Watch on demand here LINK
Wednesday, December 18, 2019
2020 CMC Conference New Session on Advanced Packaging Materials - CHIPS & EMIB for SiP
|
|
|
|
|
|
|
|
|