Intel researchers have developed an integrated CMOS Driver-GaN (DrGaN) power switch, combining gallium nitride (GaN) and silicon CMOS technologies on a 300mm GaN-on-Si platform. This innovation is designed to meet the increasing power density and efficiency needs of data centers and networking platforms. The new device, termed DrGaN, features an e-mode HEMT and an integrated 3D monolithic Si PMOS. It's capable of addressing the power requirements of future CPUs and GPUs, showing excellent resistance and leakage performance. A key advancement is the development of a new gate-last process flow for 3D monolithic integration of GaN and Si CMOS through layer transfer.
Intel researchers have developed an integrated CMOS Driver-GaN (DrGaN) power switch, combining gallium nitride (GaN) and silicon CMOS technologies on a 300mm GaN-on-Si platform.
This process involves completing the high-temperature activation steps for the Si CMOS transistors before depositing the GaN transistor's gate dielectric, solving a major challenge in integrating these two technologies. This method also allows GaN and Si CMOS transistors to share the same backend interconnect stack, which reduces resistance and mask count. The new technology demonstrates great promise for scaling, evidenced by a figure of merit of 0.59 (mΩ-nC)-1 for a 30nm gate-length GaN MOSHEMT. The paper includes images of the new process flow, the 3D monolithic integration, and the layout of a DrGaN unit cell, illustrating the advanced integration and circuitry of this novel power device.
The escalating Israel-Hamas war, after Hamas brutal attack on Israel and innocent civilians, is affecting the global tech sector. Many professionals, including top executives, are now serving as reservists in the Israel Defense Forces, as highlighted by EPSNews. Intel, a major private employer in Israel, along with other tech giants like Nvidia, Apple, Amazon, and Microsoft, faces potential disruptions, especially with facilities near conflict zones. The blockade in Gaza and transportation interruptions further strain the supply chain, emphasizing the tech industry's vulnerability to geopolitical challenges.
Intel factory in Kiryat Gat, employing about 5000 workers, which manufactures computer chips (wWikipedia), Location of Intel Fabs in Israel (Google)
Kiryat Gat, situated in Israel's Southern District, is known for Intel's semiconductor fabrication plants, including Fab 28 and the upcoming Fab 38. Founded in 1954, the city has grown significantly due to Jewish immigration over the decades and it remains an educational hub with 25 schools serving over 10,000 students.
The Israel-Hamas conflict has intensified concerns over the global semiconductor supply chain, as CNBC reports. With Israel being a key player in chip production, the geopolitical unrest poses risks to the semiconductor industry. The recent kidnapping of an Nvidia engineer further accentuates these threats, prompting tech firms to prioritize their employees' safety in the region.
Bloomberg reported this summer of Intel Corp.'s initiative to set up a new manufacturing facility in Israel. This move is part of Intel's strategy to diversify its production sources. While details remain undisclosed, the facility will focus on wafer fabrication. Intel's CEO, Pat Gelsinger, intends to expand manufacturing bases outside Asia. The plant, expected to operate from 2027, will be located in Kiryat Gat and is seen as a significant foreign investment in Israel. This development aligns with the global shift in chip manufacturing, as seen with Intel's investment in Poland and Micron Technology's potential investment in India.
Intel researchers developed a 3D monolithic CFET device* with 3 n-FET nanoribbons atop 3 p-FET nanoribbons, separated by 30 nm gap. This industry-first device enabled the creation of functional inverters at a 60 nm gate pitch. Notably, it incorporated vertically stacked dual-Source/Drain epitaxy, dual metal work function gate stacks, and backside power delivery with direct device contacts. They also introduced a nanoribbon "depopulation" method for varying n-MOS/p-MOS device numbers. This research advances the understanding of CFET scalability for logic and SRAM applications and highlights key process enablers. The paper will be presented at the upcoming IEDM conference in San Francisco.
Comment: The stacked CMOS inverter at a 60 nm gate pitch represents an advancement in semiconductor design, allowing for denser circuits. The 60 nm distance between gates indicates a highly miniaturized design. Power vias provide vertical power connections to different layers, while direct backside device contacts enhance efficiency and heat dissipation. This development offers a glimpse into the future electronic devices being more compact, efficient, and high-performing than deploying "planar" designs in one layer like the FinFETs and GAA-FETs of today.
ALD plays a key role in manufacturing 3D monolithic CFET devices by assisting in crafting the architecture and providing atomically precise and even thin film layers at small scales. ALD ensures even coverage, which is important for 3D designs, especially on vertical areas and inside deep gaps. It's used to put down important materials in transistor gate stacks (High-k/Metal Gates or HKMG), as well as barrier and seed layers. ALD also helps in doping (SSD - solid state doping), which changes how semiconductors behave, and in creating spacers, important for separating and defining parts of transistors. In brief, ALD helps improve the CFET design and its overall performance.
* A 3D monolithic CFET device combines three-dimensional stacking and the Complementary Field-Effect Transistor (CFET) design within a single semiconductor structure. This approach vertically integrates both n-type and p-type transistors on the same substrate, promoting tighter integration and reduced interconnect delays. By leveraging the complementary operation of CFET and the benefits of 3D stacking, the device aims to enhance performance, miniaturization, and efficiency in semiconductor technology.
The semiconductor industry is witnessing a fierce competition between TSMC and Intel, as they advance transistor designs with TSMC's Gate-All-Around (GAA) FETs and Intel's RibbonFET. Atomic Layer Deposition (ALD) plays an instrumental role in crafting these intricate designs. As the race to dominate the microelectronics realm heats up, the innovations from these giants foretell a transformative phase for technology between 2024 and 2026. This article dives into their respective technologies, comparing their strategies and highlighting the future implications for the semiconductor industry.
Both TSMC and Intel are pushing the boundaries of semiconductor innovation with advanced transistor designs. TSMC's GAA (Gate-All-Around) FET (Field-Effect Transistor) technology and Intel's RibbonFET are prime examples of this evolution. ALD is crucial for GAA FET production, ensuring precision and atomically thin, conformal or on purpose non-conformal or selectively deposited films. As transistors miniaturized, ALD replaced traditional silicon dioxide gate dielectrics with high-k materials, reducing gate leakage and offering enhanced uniformity. One of the challenges in GAA FETs is accurately aligning the gate material around the channel; ALD facilitates this through self-aligned processes. Additionally, in configurations with multiple gates or nanosheets, ALD accurately deposits spacer materials, preserving the necessary separation between nanosheets. ALD also offers precise doping for GAA FETs, including NMOS and PMOS. With atomic-level control, ALD introduces dopants like phosphorus for NMOS and boron for PMOS. Given the shrinking device dimensions, ALD's precision becomes vital, especially when considering techniques like solid-state doping to achieve ultra-shallow profiles.
TSMC's Gate-All-Around (GAA) FET technology represents a significant shift from the traditional FinFET transistor design. In a GAA FET, the gate material wraps entirely around the channel, unlike the FinFET where the gate is only on three sides of a vertical fin. This complete encirclement provides enhanced control over the current flow through the channel, reducing leakage current and allowing for lower voltage operation. The result is improved energy efficiency and performance.
TSMC's roadmap to N2. (Image: TSMC)
On the other hand, Intel's RibbonFET introduces a similar gate-all-around design but with a unique twist. Instead of a traditional vertical fin, RibbonFET uses nanosheet technology, where multiple flat nano-sheets are stacked to form the channel. This design offers even better control of the current flow, leading to significant gains in performance and efficiency. RibbonFET is one of Intel's flagship innovations for its advanced nodes, emphasizing the company's commitment to reclaiming technology leadership in the semiconductor space.
Intel 20A Ribbon FET (intel.com)
In a recent article Tom´s Hardware (Anton Shilow, link below) compares the advanced semiconductor technology nodes from industry TSMC and Intel, focusing on TSMC's N3P and N2 nodes against Intel's 20A and 18A nodes. Forecasted for release between 2024 and 2026, these nodes represent the forefront of semiconductor innovation. TSMC's N3P, a 3nm-class node, is set to be available by 2025 and offers performance comparable to Intel's 18A. Interestingly, TSMC's 2nm-class N2, expected in the second half of 2025, is anticipated to outpace Intel's 18A in terms of power, performance, and area advantages. Intel's 20A, arriving in 2024, promises significant advancements by introducing RibbonFET gate-all-around transistors and a backside power delivery network. The subsequent 18A will further refine these innovations. While TSMC leans on its proven FinFET technology for the N3P, it plans to introduce nanosheet GAA transistors in the N2.
As the semiconductor race intensifies, both companies are heavily invested in outpacing each other, with TSMC focusing on technology maturity and cost-effectiveness, and Intel aiming to regain its technology leadership. The dynamics between these tech giants will shape the semiconductor industry's future.
Comparison of Advanced Semiconductor Technology Nodes: TSMC N3P & N2 vs. Intel 20A & 18A, highlighting the competitive landscape of the semiconductor industry for the years 2024-2026 based on Toms Hardware article below.
Intel will sell a 10% stake in IMS Nanofabrication to TSMC, valuing IMS at $4.3 billion, maintaining Intel's majority ownership. IMS leads in multi-beam mask writing tools for advanced extreme ultraviolet lithography, crucial for AI and mobile applications. This investment enhances IMS' independence and fosters innovation, including high-numerical-aperture EUV technology. The deal is set to close in Q4 2023. IMS is vital for semiconductor industry growth, with the market projected to reach $1 trillion by 2030. Intel acquired IMS in 2015 and sold a 20% stake to Bain Capital earlier in 2023, while TSMC's partnership with IMS dates back to 2012.
About IMS Nanofabrication
IMS Nanofabrication Global, LLC, a majority-owned subsidiary of Intel Corporation, is the global technology leader for multi-beam mask writers. Its customers are the largest chip manufacturers in the world, who rely on its technology to produce current and future chip generations. IMS’ innovative multi-beam writers play a key role in chip manufacturing and provide significant added value to the semiconductor industry. They are continually customized and refined by an interdisciplinary team, in line with the latest market demands. Over the last 10 years, IMS has perfected its electron-based multi-beam technology. The first-generation multi-beam mask writer, MBMW-101, is successfully operating all over the world. The second-generation multi-beam mask writer, MBMW-201, entered the mask writer market in the first quarter of 2019 for the 5nm technology node. And this year, IMS is launching MBMW-301, a fourth-generation multi-beam mask writer that delivers unprecedented performance. Learn more at www.ims.co.at/en/.
ASML, the leading semiconductor equipment manufacturer, is set to ship the first pilot tool from its next product line in 2023, despite some supplier delays, according to CEO Peter Wennink. These High NA EUV machines, crucial for top chipmakers to create smaller and better chips in the coming decade, will cost over $300 million euros each and provide up to 70% better resolution. ASML currently dominates the lithography market, a pivotal step in chipmaking, and is seeing strong demand for its older DUV machines, with 30% sales growth forecasted in 2023, primarily driven by Chinese customers.
ASML's High NA EUV machines are used by a range of prominent semiconductor manufacturers, including TSMC, Intel, Samsung, SK Hynix, and Micron. These chipmakers rely on ASML's cutting-edge lithography equipment to manufacture semiconductor chips, from microprocessors to memory chips.
"High NA" stands for "High Numerical Aperture." Numerical Aperture (NA) is a measure of the ability of an optical system, such as a lens or mirror, to gather and focus light. A higher numerical aperture indicates a greater ability to capture light and provide finer detail and resolution in imaging or lithography processes. ASML's High NA EUV machines, are designed to gather light from a wider angle compared to their previous generation tools. This wider angle collection of light allows for significantly improved resolution in the semiconductor manufacturing process, making it possible to create smaller and more advanced semiconductor chips with greater precision required for the Ångström Era - basically the sub 2 nm nodes.
Intel plans to separate its manufacturing and fabless units to regain its semiconductor chip leadership. The move aims to serve emerging markets and make chip manufacturing more efficient. Intel seeks to emulate TSMC's success and become the second-largest external foundry by 2030.
In an effort to reclaim its position as a leader in the semiconductor chip industry, Intel has announced plans to separate its manufacturing and fabless units. This strategic move aims to address evolving market dynamics and capitalize on emerging sectors such as cloud computing, edge computing, and artificial intelligence (AI). By granting independence to its foundry business and diversifying its chip production, Intel aims to regain its competitive edge and accelerate chip development.
Diversifying into New Markets
Intel's factories have traditionally focused on serving the PC and server markets, but the company recognizes the need to adapt to the changing landscape. By separating fabless and manufacturing operations, Intel can now cater to a broader customer base, including external clients. The new fabs, set to be operational by early 2024, will manufacture chips for non-Intel customers, making Intel a potential competitor to contract chip manufacturers like TSMC.
Emulating the TSMC Playbook
Intel's strategy shares similarities with Taiwan Semiconductor Manufacturing Co. (TSMC), which has successfully produced chips for companies like Nvidia, Apple, and AMD. TSMC's approach of guaranteeing capacity to long-term partners during the recent chip shortage has proven effective. Intel aims to replicate this success by becoming the second-largest external foundry by 2030 and generating more than $20 billion in manufacturing revenue.
Competing for Internal Fab Capacity
The separation of fabless and manufacturing units introduces a new dynamic within Intel. Internal chip design units will now compete with external customers for fab capacity, potentially accelerating Intel's internal chip design efforts. The competition for volume will drive efficiency and faster innovation, as internal business units can leverage third-party foundries if they are willing to pay top dollar for guaranteed capacity.
Reviving Manufacturing Prowess
Intel's ability to deliver chips on time has been a key challenge, allowing TSMC to emerge as a leader in the industry. However, Intel aims to regain its position by focusing on advanced nodes such as the Intel 18A process, which incorporates cutting-edge technologies like gate-all-around (GAA) transistors. By emphasizing more efficient manufacturing processes and performance improvements, Intel intends to win back customers and regain its reputation as a reliable chip manufacturer.
Intel is expanding as a foundry in Europe
Intel's expansion plans in Europe took a significant step forward as the company signed a deal with the German government to build a €30 billion chip manufacturing site in Magdeburg. Germany will cover a third of the investment, marking the largest foreign direct investment in the country's modern history. The agreement was signed during a meeting between German Chancellor Olaf Scholz and Intel CEO Pat Gelsinger in Berlin. The investment will significantly expand Intel's production capacity in Europe and is seen as a crucial strategic move for Germany and Europe to establish self-sufficiency in strategic technologies. The project, known as the "Silicon Junction," is expected to create 3,000 high-quality jobs and additional positions in supplier networks. The EU's executive branch will review the plan to ensure fair competition. With this expansion, Germany aims to become one of the major global semiconductor production sites and reduce its dependence on imported chips and global supply chains. The completion of the twin semiconductor plants is expected by 2027 and will contribute to the EU's goal of decreasing reliance on China and the US for microchip production.
Conclusion
Intel's decision to separate its manufacturing and fabless units marks a strategic shift aimed at regaining its leadership in the semiconductor chip industry. By diversifying into emerging markets, emulating successful models like TSMC's, and focusing on advanced manufacturing processes, Intel hopes to reclaim its competitive edge and position itself as a leading player in the evolving landscape of chip manufacturing.
Seventy-five percent of semiconductors, or microchips — the tiny operating brains in just about every modern device — are manufactured in Asia. Lesley Stahl talks with leading-edge chip manufacturers, TSMC and Intel, about the global chip shortage and the future of the industry.
Pat Gelsinger: 25 years ago, the United States produced 37% of the world's semiconductor manufacturing in the U.S. Today, that number has declined to just 12%
Within the world of global collaboration, there's intense competition. Days after Intel announced spending $20 billion on two new fabs, TSMC announced it would spend $100 billion over three years on R&D, upgrades, and a new fab in Phoenix, Arizona, Intel's backyard, where the Taiwanese company will produce the chips Apple needs but the Americans can't make.
Intel CEO Pat Gelsinger shows CBS correspondent Lesley Stahl a silicon wafer.
Taiwan-based TSMC, which supplies microchips for most U.S. cars, tells 60 Minutes it will be caught up with car chip production by the end of June. So, does that mean the dire shortage will end in two months? Well, not quite. https://t.co/Wj1yFffaKSpic.twitter.com/Zx3dnRwU0o
Intel announced on Tuesday that it will spend $20 billion to build two major factories in Arizona. The news comes amid a worldwide chip shortage that is snarling industries from automobiles to electronics and worries the U.S. is falling behind in semiconductor manufacturing. The announcement signals that Intel will continue to focus on manufacturing.
Next chance to get deep insights to Intel quality demands and advanced metrology & analytic for the material supply chain will be at the CMC2021 Conference, broadcasted from San Diego, USA, APril 14-15:
KEYNOTE : Jeanne Yuen-Hum, Vice President of Manufacturing & Operations, and Director of Global Supply-Chain Quality & Reliability, Intel Corporation "The Cost of Quality"
Alex Tregub, PhD Staff Engineer Intel Corporation "From Egyptian Royal Cubit to SEMI Guides for CMP consumables – Industry Standards"
IC Insights’ November shows the forecasted top-25 semiconductor suppliers in 2020. Seven top-15 semiconductor suppliers forecast to show ≥22% growth this year with Nvidia expected to post a huge 50% increase. The top-15 companies semiconductor sales are broken out into IC and O-S-D (optoelectronic, sensor, and discrete) device categories for 2019 and 2020. The forecasted 2020 top-15 semiconductor supplier ranking includes eight suppliers headquartered in the U.S., two each in South Korea, Taiwan, and Europe, and one in Japan.
Intel remains No 1. followed by Samsung and TSMC. 2020 show a very high growth for Fabless companies Qualcomm, Nvidia, MediaTek, Apple and AMD.
The Memory segment (DRAM and Flash) is led by SK Hynix +14% followed by Samsung +9% (incl. foundry) and Micron is down by -3%.
Please read the full IC Insights report here: LINK
Intel to present stacked gate-all-around FET (GAA-FET) technology, i.e., a complementary FET (CFET) at IEDM2020. In CFETs, the idea is to stack both nFET and pFET wires on each other. A CFET could stack one nFET on top of a pFET wire, or two nFETs on top of two pFET wires. This ‘folding’ of the nFET and pFET eliminates the n-to-p separation bottleneck, reducing the cell active area footprint (LINK). Please find the announcement below:
Home-2020 - IEDM 2020 ieee-iedm.org IEDM Conference 2020. To Be Held Virtually December 12-18. The on demand portion of the conference will begin on December 5th. Intel to present 3D stacked Nanoribbon Transistors for Continued Moore’s Law Scaling:
Stacked NMOS-on-PMOS Nanoribbons: From planar MOSFETs, to FinFETs, to gate-all-around (GAA) or nanoribbon devices, novel transistor architectures have played a critical role in driving performance predicted by Moore’s Law. Intel researchers will describe what may be the next step in that evolution: NMOS-on-PMOS transistors built from multiple self-aligned stacked nanoribbons. This architecture employs a vertically stacked dual source/drain epitaxial process and a dual metal gate fabrication process, enabling different conductive types of nanoribbons to be built so that threshold voltage adjustments can be made for both top and bottom nanoribbons. The approach combines excellent electrostatics (subthreshold slope of <75 mV/dec) and DIBL (<30mV/V for gates ≥30nm) with a path to significant cell size reduction due to the self-aligned stacking. These devices were used to build a functional CMOS inverter with well-balanced voltage transfer characteristics. (Paper #20.6, “3-D Self-Aligned Stacked NMOS-on-PMOS Nanoribbon Transistors for Continued Moore’s Law Scaling,” C.-Y. Huang et al, Intel)
Paper #20.6, “3-D Self-Aligned Stacked NMOS-on-PMOS Nanoribbon Transistors for Continued Moore's Law Scaling,” C.-Y. Huang et al, Intel
Figures from IEDM 2020 Press briefing Material -Press kit : LINK
In the images
above:
·(1) shows
the evolution of transistor architectures from planar, to FinFETs, to
nanoribbons and to a 3D CMOS architecture.
·(2) (a)
shows a 3D schematic diagram of stacked CMOS Si nanoribbon transistors with
NMOS on PMOS, (b) describes the process flow; (c) is a TEM image of a stacked
multiple-nanoribbon CMOS inverter with a 40-nm gate length and inner (Vss)
and outer (Vcc) contacts, a common gate input (VIN) and
an inverter output node (VOUT); while (d) is a TEM image of two Si
NMOS nanoribbons atop 3 Si PMOS nanoribbons.
·(3) (a)
is a process flow of the vertically stacked dual S/D EPI process, while (b)
shows P-EPI selectively grown on the bottom three nanoribbons, (c) shows N-EPI
selectively grown on the top two nanoribbons, and (d) features TEM and EDS
images showing selective N-EPI and P-EPI growth on the stacked nanoribbon
transistors.
·(4)
(a) is a process flow of the vertically stacked dual metal gate process; (b) is
a TEM image and (c, d) are EDS images of the dual metal gate with N-WFM (WFM =
work function metal) on the top two nanoribbons and P-WFM on the bottom three
nanoribbons.
Here is a very insightful article by PETER GILLESPIE, VP & GM, Semiconductor Products, Advanced Energy Industries on the progress of Plasma RF Generators and Matching Networks. The article looks at applications in 3DNAND High Aspect Ratio Contacts (HARC) and Logic FinFET transitor fabrication using reactive ion etching and plasma CVD using the latest plasma technology. This is a an articel in a series of three in SEMICONDUCTOR DIGEST entitled “Process Power Steps Out from the Shadows,” looking at the leading edge technology node process challenges to highlight key drivers that are fundamentally transforming the role and importance of process power.
Process Power: The New Lithography (SEMICONDUCTOR DIGEST, LINK)
"Evolution of RF power supplies (plasma generators) and RF matching
networks. Today’s RF power delivery systems are highly sophisticated
with frequency tuning, complex pulsing regimes, and agile micro-second
response." (Below)
TechInsights’ ‘Memory Process: 3D NAND Word Line Pad‘ #webinar compares 9x-layer 3D NAND devices from major manufacturers and discusses the process sequence with emphasis on the word line pad (WLP). Watch on demand here LINK
Advanced Packaging Materials. Scheduled for April 23-24 in Hillsboro, Oregon, the 5th CMC Conference, will explore actionable technical and value-chain trends of critical materials for global semiconductor fabs and feature keynotes from leaders in semiconductor technology and materials. The conference keynote address this year will be:
"Critical Materials Pushing the Limits for Semiconductor Manufacturing"
by Bruce Tufts,Vice President of Technology and Director of Fab Materials Organization, Intel Corp.
Sessions will cover:
I. Global Value-chain Issues, Including Economics and Regulations,
II. Immediate Challenges of Materials & Manufacturing,
III. Emerging Materials in R&D and Pilot Fabrication, and
New this year is a fourth session,
IV. Advanced Packaging Materials
Lead by Session Chairman Jim Hannah, Product Development and Applications Manager of SEH, the Advanced Packaging Materials Session will address, system level performance scaling issues and the increased reliance on packaging. As explained by Mr. Hannah, “We see the lines starting to blur between packaging and the back-end wiring on-chip. The CMC Conference will cover both current challenges and future requirements of packaging materials needed to support this middle-ground."
A keynote address on “The Future of Silicon as a Packaging Material" for this new session will be provided by Dr. Subramanian Iyer, principle of UCLA’s Center for Heterogeneous Integration and Performance Scaling (CHIPS) consortium, IEEE Fellow, IBM Fellow, IIT Distinguished Alumnus, and UCLA Distinguished Chancellor's Professor of both Electrical and Computer Engineering and Materials Science and Engineering.
Dr. Lauren Link, Intel's Technical Program Manager, Substrate Business Group, will present on materials to enable Embedded Multi-die Interconnect Bridge (EMIB) connections between silicon chiplets in advanced Heterogeneous Integration (HI) System-in-Package (SiP) products.
CMC member companies will be attending the public CMC Conference, which follows the annual members-only CMC meeting to be sponsored by Intel and held April 21-22. Conference attendees will include industry experts handling supply-chains, business-development, R&D, and product management, as well as academics and analysts. Business drives our world, but technology enables the profitable manufacturing of semiconductor devices and facilitates the introduction of new materials.
To submit a paper for consideration, send a 1-page abstract focusing on critical materials supply dynamics by January 15, 2020 to
For more information on CMCFabs or CMC Associate Memberships, please contact Diane Scott at dscott@techcet.com. For information on sponsoring the CMC Conference please contact Yvonne Brown at ybrown@techcet.com, +1-480-382-8336 x1.
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