CBS 60 Minutes - Chip shortage highlights U.S. dependence on fragile supply chain

Seventy-five percent of semiconductors, or microchips — the tiny operating brains in just about every modern device — are manufactured in Asia. Lesley Stahl talks with leading-edge chip manufacturers, TSMC and Intel, about the global chip shortage and the future of the industry.

• Pat Gelsinger: 25 years ago, the United States produced 37% of the world's semiconductor manufacturing in the U.S. Today, that number has declined to just 12%
• Within the world of global collaboration, there's intense competition. Days after Intel announced spending $20 billion on two new fabs, TSMC announced it would spend $100 billion over three years on R&D, upgrades, and a new fab in Phoenix, Arizona, Intel's backyard, where the Taiwanese company will produce the chips Apple needs but the Americans can't make.

Intel CEO Pat Gelsinger shows CBS correspondent Lesley Stahl a silicon wafer.

Taiwan-based TSMC, which supplies microchips for most U.S. cars, tells 60 Minutes it will be caught up with car chip production by the end of June. So, does that mean the dire shortage will end in two months? Well, not quite. https://t.co/Wj1yFffaKS pic.twitter.com/Zx3dnRwU0o

— 60 Minutes (@60Minutes) May 2, 2021

Intel is spending $20 billion to build two new chip plants in Arizona

Intel announced on Tuesday that it will spend $20 billion to build two major factories in Arizona. The news comes amid a worldwide chip shortage that is snarling industries from automobiles to electronics and worries the U.S. is falling behind in semiconductor manufacturing. The announcement signals that Intel will continue to focus on manufacturing.

Next chance to get deep insights to Intel quality demands and advanced metrology & analytic for the material supply chain will be at the CMC2021 Conference, broadcasted from San Diego, USA, APril 14-15:

KEYNOTE : Jeanne Yuen-Hum, Vice President of Manufacturing & Operations, and Director of Global Supply-Chain Quality & Reliability, Intel Corporation "The Cost of Quality"

Alex Tregub, PhD Staff Engineer Intel Corporation "From Egyptian Royal Cubit to SEMI Guides for CMP consumables – Industry Standards"

Conference: https://cmcfabs.org/agenda-2021/

• Intel invests $20 billion in two Arizona factories, 7nm chips coming in 2023
• Intel announces steps to boost chip manufacturing
• ‘Intel is back:’ New CEO’s plan to make chips for others excites investors
• Stocks making the biggest moves after the bell: GameStop, Adobe, Intel
• Intel is spending $20 billion to build two new chip plants in Arizona

Intel remains in the lead in 2020 semiconductor sales

IC Insights’ November shows the forecasted top-25 semiconductor suppliers in 2020. Seven top-15 semiconductor suppliers forecast to show ≥22% growth this year with Nvidia expected to post a huge 50% increase. The top-15 companies semiconductor sales are broken out into IC and O-S-D (optoelectronic, sensor, and discrete) device categories for 2019 and 2020. The forecasted 2020 top-15 semiconductor supplier ranking includes eight suppliers headquartered in the U.S., two each in South Korea, Taiwan, and Europe, and one in Japan.

Intel remains No 1. followed by Samsung and TSMC. 2020 show a very high growth for Fabless companies Qualcomm, Nvidia, MediaTek, Apple and AMD.

The Memory segment (DRAM and Flash) is led by SK Hynix +14% followed by Samsung +9% (incl. foundry) and Micron is down by -3%.

Please read the full IC Insights report here: LINK

Intel to present 3D stacked Nanoribbon Transistors for Continued Moore’s Law Scaling at IEDM 2020

Intel to present stacked gate-all-around FET (GAA-FET) technology, i.e., a complementary FET (CFET) at IEDM2020. In CFETs, the idea is to stack both nFET and pFET wires on each other. A CFET could stack one nFET on top of a pFET wire, or two nFETs on top of two pFET wires. This ‘folding’ of the nFET and pFET eliminates the n-to-p separation bottleneck, reducing the cell active area footprint (LINK). Please find the announcement below:

Home-2020 - IEDM 2020 ieee-iedm.org IEDM Conference 2020. To Be Held Virtually December 12-18. The on demand portion of the conference will begin on December 5th. Intel to present 3D stacked Nanoribbon Transistors for Continued Moore’s Law Scaling: 

Stacked NMOS-on-PMOS Nanoribbons: From planar MOSFETs, to FinFETs, to gate-all-around (GAA) or nanoribbon devices, novel transistor architectures have played a critical role in driving performance predicted by Moore’s Law. Intel researchers will describe what may be the next step in that evolution: NMOS-on-PMOS transistors built from multiple self-aligned stacked nanoribbons. This architecture employs a vertically stacked dual source/drain epitaxial process and a dual metal gate fabrication process, enabling different conductive types of nanoribbons to be built so that threshold voltage adjustments can be made for both top and bottom nanoribbons. The approach combines excellent electrostatics (subthreshold slope of <75 mV/dec) and DIBL (<30mV/V for gates ≥30nm) with a path to significant cell size reduction due to the self-aligned stacking. These devices were used to build a functional CMOS inverter with well-balanced voltage transfer characteristics. (Paper #20.6, “3-D Self-Aligned Stacked NMOS-on-PMOS Nanoribbon Transistors for Continued Moore’s Law Scaling,” C.-Y. Huang et al, Intel) 

Paper #20.6, “3-D Self-Aligned Stacked NMOS-on-PMOS Nanoribbon Transistors for Continued Moore's Law Scaling,” C.-Y. Huang et al, Intel

Paper Information (IEDM 2020) : LINK

Figures from IEDM 2020 Press briefing Material -Press kit : LINK

In the images above:

·        (1) shows the evolution of transistor architectures from planar, to FinFETs, to nanoribbons and to a 3D CMOS architecture.

·        (2) (a) shows a 3D schematic diagram of stacked CMOS Si nanoribbon transistors with NMOS on PMOS, (b) describes the process flow; (c) is a TEM image of a stacked multiple-nanoribbon CMOS inverter with a 40-nm gate length and inner (V_ss) and outer (V_cc) contacts, a common gate input (V_IN) and an inverter output node (V_OUT); while (d) is a TEM image of two Si NMOS nanoribbons atop 3 Si PMOS nanoribbons.

·       (3) (a) is a process flow of the vertically stacked dual S/D EPI process, while (b) shows P-EPI selectively grown on the bottom three nanoribbons, (c) shows N-EPI selectively grown on the top two nanoribbons, and (d) features TEM and EDS images showing selective N-EPI and P-EPI growth on the stacked nanoribbon transistors.

·       (4) (a) is a process flow of the vertically stacked dual metal gate process; (b) is a TEM image and (c, d) are EDS images of the dual metal gate with N-WFM (WFM = work function metal) on the top two nanoribbons and P-WFM on the bottom three nanoribbons.

Process Power: The New Lithography - Advanced Energy

Here is a very insightful article by PETER GILLESPIE, VP & GM, Semiconductor Products, Advanced Energy Industries on the progress of Plasma RF Generators and Matching Networks. The article looks at applications in 3DNAND High Aspect Ratio Contacts (HARC) and Logic FinFET transitor fabrication using reactive ion etching and plasma CVD using the latest plasma technology. This is a an articel in a series of three in SEMICONDUCTOR DIGEST entitled “Process Power Steps Out from the Shadows,” looking at the leading edge technology node process challenges to highlight key drivers that are fundamentally transforming the role and importance of process power. 

Process Power: The New Lithography (SEMICONDUCTOR DIGEST, LINK) 

 

"Evolution of RF power supplies (plasma generators) and RF matching networks. Today’s RF power delivery systems are highly sophisticated with frequency tuning, complex pulsing regimes, and agile micro-second response." (Below)

 

 

TechInsights’ Memory Process: 3D NAND Word Line Pad webinar

TechInsights’ ‘Memory Process: 3D NAND Word Line Pad‘ #webinar compares 9x-layer 3D NAND devices from major manufacturers and discusses the process sequence with emphasis on the word line pad (WLP). Watch on demand here LINK 

 

Screendump from Webinar

2020 CMC Conference New Session on Advanced Packaging Materials - CHIPS & EMIB for SiP

San Diego, CA, December 17: The Critical Materials Council (CMC) of semiconductor fabricators and TECHCET announce a new addition to the 2020 CMC Conference:  Advanced Packaging Materials. Scheduled for April 23-24 in Hillsboro, Oregon, the 5th CMC Conference, will explore actionable technical and value-chain trends of critical materials for global semiconductor fabs and feature keynotes from leaders in semiconductor technology and materials. The conference keynote address this year will be: "Critical Materials Pushing the Limits for Semiconductor Manufacturing" by Bruce Tufts, Vice President of Technology and Director of Fab Materials Organization, Intel Corp. Sessions will cover:  I. Global Value-chain Issues, Including Economics and Regulations, II. Immediate Challenges of Materials & Manufacturing, III. Emerging Materials in R&D and Pilot Fabrication, and   New this year is a fourth session, IV. Advanced Packaging Materials Lead by Session Chairman Jim Hannah, Product Development and Applications Manager of SEH, the Advanced Packaging Materials Session will address, system level performance scaling issues and the increased reliance on packaging. As explained by Mr. Hannah, “We see the lines starting to blur between packaging and the back-end wiring on-chip. The CMC Conference will cover both current challenges and future requirements of packaging materials needed to support this middle-ground." A keynote address on “The Future of Silicon as a Packaging Material" for this new session will be provided by Dr. Subramanian Iyer, principle of UCLA’s Center for Heterogeneous Integration and Performance Scaling (CHIPS) consortium, IEEE Fellow, IBM Fellow, IIT Distinguished Alumnus, and UCLA Distinguished Chancellor's Professor of both Electrical and Computer Engineering and Materials Science and Engineering.

Dr. Lauren Link, Intel's Technical Program Manager, Substrate Business Group, will present on materials to enable Embedded Multi-die Interconnect Bridge (EMIB) connections between silicon chiplets in advanced Heterogeneous Integration (HI) System-in-Package (SiP) products. CMC member companies will be attending the public CMC Conference, which follows the annual members-only CMC meeting to be sponsored by Intel and held April 21-22. Conference attendees will include industry experts handling supply-chains, business-development, R&D, and product management, as well as academics and analysts. Business drives our world, but technology enables the profitable manufacturing of semiconductor devices and facilitates the introduction of new materials. To submit a paper for consideration, send a 1-page abstract focusing on critical materials supply dynamics by January 15, 2020 to  cmcinfo@techcet.com For more information and registration: cmcfabs.org/cmc-conference-2020

For more information on CMCFabs or CMC Associate Memberships, please contact Diane Scott at dscott@techcet.com. For information on sponsoring the CMC Conference please contact Yvonne Brown at ybrown@techcet.com, +1-480-382-8336 x1.

CMC Fab members include:

Copyright 2019 TECHCET CA LLC all rights reserved

IEDM 2019 News - Intel roadmap to 1.4 nm by 2029

Limitless - Intel disclosed its extended roadmap to 1.4 nm process node by 2029 including back porting: One of the interesting disclosures at the IEEE International Electron Devices Meeting (IEDM) was that Intel expects to be on 2 year cadence with its manufacturing process node technology, starting with 10nm in 2019 and moving to 7 nm EUV in 2021, then 5 nm in 2023, 3 nm in 2025, 2 nm in 2027, and 1.4 nm in 2029. 

 

In between each process node, as Intel has stated before, there will be iterative + and ++ versions of each in order to extract performance from each process node. The only exception to this is 10nm, which is already on 10+, so we will see 10++ and 10+++ in 2020 and 2021 respectively. The interesting element is the mention of back porting. This is the ability for a chip to be designed with one process node in mind, but perhaps due to delays, can be remade on an older ‘++’ version of a process node in the same timeframe.

 

Intel's slide with ASML's animations overlayed, as shown in the slide deck distributed by ASML. Note by Anandtech: "After some emailing back and forth, we can confirm that the slide that Intel's partner ASML presented at the IEDM conference is actually an altered version of what Intel presented for the September 2019 source. ASML added animations to the slide such that the bottom row of dates correspond to specific nodes, however at the time we didn't spot these animations (neither did it seem did the rest of the press). It should be noted that the correlation that ASML made to exact node names isn't so much a stretch of the imagination to piece together, however it has been requested that we also add the original Intel slide to provide context to what Intel is saying compared to what was presented by ASML. Some of the wording in the article has changed to reflect this. Our analysis is still relevant." Please see the full article in Anandtech for all the details: LINK

 

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By Abhishekkumar Thakur

Intel Oregon is looking for young CVD, ALD and PVD experts

[Intel, Hillsboro Oregon, USA] We are hiring Ph.D. candidates or recently received a Ph.D. degree in the metals thin-film area. We are giving priorities to the candidates who have exceptional backgrounds in physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and/or Electrodeposition fields. Strong plasma physics and vacuum science knowledge will be needed for PVD, CVD, and ALD deposition area candidates. 

 

 

 Intels Fab D1X in Oregon USA (Intel.com)

 

We are also looking for candidates with synthetic chemistry backgrounds for CVD/MOCVD (metal-organic chemical vapor deposition) precursor development. In the Electrodeposition area, we are looking for candidates with a strong background in electrochemistry, plating related thin film deposition.

Generic Job description can be found here - https://jobs.intel.com/ListJobs/ByKeyword/JR0099326/

Please send me your resume directly to shaestagir.chowdhury@intel.com

 

------------

Guest Blog by Dr. Shaestagir Chowdhury, Principal Engineer at Intel Corporation, Hillsboro, Oregon

 

Intel at EECS Colloquium "Moore’s Law Is Not Dead"

Intel’s Jim Keller: “We’re all building nanowires… Intel, TSMC, Samsung” Keller in his "Moore’s Law Is Not Dead" talk at UC Berkeley this week said, “We had planar transistors, we went to FinFET. We’re all building nanowires in the fab. Intel, TSMC, Samsung, everybody’s working on it. There’s a really interesting thing. While the world thinks Moore’s Law’s dead, the fabs and the technologists think it’s not and everybody’s announced now a 10-year roadmap for Moore’s Law.” 

The UC Berkeley EECS Events team has live streamed the entire talk over on YouTube and you can catch up on this fascinating, intimate little talk (below).

 

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By Abhishekkumar Thakur

Intel 2019 Investor Meeting: 7 nm Product in 2021

Intel held its 2019 investor meeting May 8, 2019 (LINK), it's first since 2017, and CEO Bob Swan announced that Intel would launch its 7 nm process in 2021 to challenge TSMC's 5 nm products.

Intel's Xe graphics will be the leading 7 nm product, which will come on the heels of Intel's first discrete 10 nm GPU that arrives in 2020. The company also unveiled its first block diagram of the Ice Lake architecture and announced that its new 10nm Tiger Lake processors will come to market in 2020.

Source: Tom´s Hardware LINK

 (intel.com)

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By Abhishekkumar Thakur

Innovation and IP filing in Atomic Layer Deposition has moved from Memory to Logic

By studying the filing of IP world wide one can clearly see the trend how innovation in Atomic Layer Deposition (ALD) has moved from Memory to Logic. During the introduction of ALD (2003 to 2006) in high volume manufacturing of DRAM on 300 mm wafers most IP was filed by Samsung, Micron and SK Hynix. 10 years later (2013-2018) the IP filing lead has been taken over by Logic MPU manufacturers TSMC, Intel and Globalfoundries.

The patent application assignee from the past 25 years.

Intel 10 nm Logic Process Analysis (Cannon Lake) by TechInsight

[TechInsight, LINK] TechInsights has found the long-awaited Cannon Lake - the Intel 10 nm logic process inside the i3-8121U CPU, used in the Lenovo IdeaPad330.

 
This innovation boasts the following:

• Logic transistor density of 100.8 mega transistors per mm², increasing 10nm density 2.7X over the 14nm node
• Utilizes third generation FinFET technology
• Minimum gate pitch of Intel’s 10 nm process shrinks from 70 nm to 54 nm
• Minimum metal pitch shrinks from 52 nm to 36 nm

Process Highlights:

• Deepest scaled pitches of current 10 nm and upcoming 7 nm technologies
• First Co metallization and Ru usage in BEOL
• New self-aligned patterning schemes at contact and BEOL

Design Highlights:

• Hyperscaling via 6.2-Track high density library
• Contact on active gate (COAG) cell-level usage

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By Abhishekkumar Thakur

Cobalt and Ruthnium confirmed in Intel 10nm Cannon Lake BEOL

TechInsights has found the long-awaited Cannon Lake - the Intel 10 nm logic process inside the i3-8121U CPU, used in the Lenovo IdeaPad330.

 
This innovation boasts the following:

• Logic transistor density of 100.8 mega transistors per mm², increasing 10nm density 2.7X over the 14nm node
• Utilizes third generation FinFET technology
• Minimum gate pitch of Intel’s 10 nm process shrinks from 70 nm to 54 nm
• Minimum metal pitch shrinks from 52 nm to 36 nm

Process Highlights:

• Deepest scaled pitches of current 10 nm and upcoming 7 nm technologies
• First Co metallization and Ru usage in BEOL
• New self-aligned patterning schemes at contact and BEOL

Source: TechInsight (LINK)

By reading this it is not possible to determine exactly how Ruthenium is used or how it has been deposited and there are several options like barrier and seed layer for plating Copper or Cobalt. What is known is that Intel presented already at IEDM2017 the use of cobalt in their 10 nm MOL/BEOL process flow as contacts and M0/M1 lines as well as barrier/seed for copper and copper cap for complete encapsulation of copper up to M5.

Intel 10nm mid end of line cobalt and copper metallization as presented at IEDM 2017.

Intel shifts high volume 10 nm shipments to 2019 due to yield issues from multi-patterning

As reported by Reuters [LINK], Intel bet the earnings expectations for the first quarter driven by the biggest-ever quarterly jump in its data centre business and small-but-steady growth in its personal computer business.However, Intel also announced that they are pushing out volume production of their 10 nm Logic process to 2019, which was most recently announced for the 2nd half of 2018. during the 1Q 2018 earnings conference calls more details were given:

[Seeking Alpha, LINK] "We continue to make progress on our 10-nanometer process. We are shipping in low volume and yields are improving, but the rate of improvement is slower than we anticipated. As a result, volume production is moving from the second half of 2018 into 2019. We understand the yield issues and have defined improvements for them, but they will take time to implement and qualify. We have leadership products on the roadmap that continue to take advantage of 14-nanometer, with Whiskey Lake for clients and Cascade Lake for the data center coming later this year.

Moore's Law is essential to our strategy and our product leadership. It continues to create significant value for Intel and our customers. While it's taking longer and costing more to deliver and yield advanced process technologies, we are able to optimize our process and products within the node to deliver meaningful performance improvements.

For example, 14-nanometer process optimizations and architectural improvements have resulted in performance gains of more than 70% since the first 14-nanometer products were launched. We combine these advances in manufacturing technology and architecture to produce truly leadership products. And it's that product leadership that ultimately matters most to our customers and end users."

Brian M. Krzanich - Intel Corp.

Earnings call slides [Seeking Alpha, LINK]

In the Q&A Mr. Krzanich elaborated on the reason behind the 10 nm push out and he explained how it is mainly due to yield issues coming from multiple patterning (SADP and SAQP):

- Intel have 10 nm product and process leadership and are shipping 10 nm products today. 

- Those are the densest, highest performing products out there.

- Intel is slowing the ramp down to fix yield issues related to patterning.

- In multi-multi-patterning (SAQP) there are six layers of patterning to produce a feature. 

- Intel understand the yield issues, which are tied to 10 nm being the last technology tied to not using EUV and the amount of multi-patterning and the effects of that on defects.

Intel’s 10 nm Platform Process was presented in detail at the IEDM 2017 (Dec 2017) “A 10nm High Performance and Low-Power CMOS Technology Featuring 3rd Generation FinFET Transistors, Self-Aligned Quad Patterning, Contact over Active Gate and Cobalt Local Interconnects” and you may study the details in this excellent article by Dick James [Solid State Technology, LINK]

Media coverage:

Intel Delays 10-nm Volume Production Until 2019
EE Times
 

Intel Delays Mass Production of 10 nm CPUs to 2019
AnandTech

Intel Delays Broken 10nm Into 2019, Hires Jim Keller to Fix It
ExtremeTech 

 

Did you guess 2019 for Intel's 10nm chip ramp up? Congratulations

The Register
 

Intel's 10nm Cannon Lake CPUs won't arrive in mass quantities until ...
Highly Cited-PC Gamer
 

Intel Chooses A New Path And It Feels Like The Right One
In-Depth-Forbes