Germany to fund the Semiconductor industry with 400 milion Euro

"Every second chip made in Europe comes from Saxony!"

Happy days in Dresden, Silicon Saxony and Germany today - Yesterday Globalfoundries announced that they are investing in Fab 1 in Dresden to ramp 22 nm FD-SOI and today Angela Merkel and Johanna Wanka comes for a visit to Dresden and promises 400 million Euro support package until 2020 for the semiconductor industry!

"Um Innovationen in der Halbleiterindustrie auch künftig voranzutreiben, erarbeitet das Bundesforschungsministerium bis Ende des Jahres zusammen mit weiteren Ressorts ein neues Rahmenprogramm. Das Programm soll mit einem Volumen von 400 Millionen Euro bis 2020 ausgestattet werden. Das hat Bundesforschungsministerin Wanka bei ihrem Besuch in Dresden angekündigt. " - http://www.bmbf.de/de/28961.php

Chancellor Angela Merkel entering the helicopter in Berlin to fly 200 km south to Dresden. (Twitter, BMBF)

Rutger Wijburg (VP and General Manager Fab1, Dresden) explains factory physics for Sanjay Jha (CEO Globalfoundries) Chancellor Angela Merkel, Ministerpräsident Stanislaw Tillich and Bundesforschungsministerin Johanna Wanka using a model Globalfoundries Fab 1 in Dresden. (Photo: Heiko Weckbrodt)

More details for those of you reading German can be found in the excellent coverage by Heiko Weckbrodt :

Bund sagt 400 Millionen € für Mikroelektronik zu

Kanzlerin Merkel debattiert in Dresden Mikroelektronik-Strategie

MDR Sachsen Video in German:

Overview
http://www.mdr.de/sachsenspiegel/video284012.html

Silicon Saxony
http://www.mdr.de/sachsenspiegel/video284020.html

Globalfoundries
http://www.mdr.de/sachsenspiegel/video283788.html

Later Frau Bundeskanzlerin Dr Merkel also stopped by Fraunhofer to meet with The Fraunhofer President Prof. Dr. Reimund Neugebauer.

Angela Merkel also visited Infineon’s Dresden 300 and 200 mm fabs today and discussed the political framework for a competitive development and production in Germany with CEO Reinhard Ploss. - See more at: http://www.electronicsweekly.com/news/business/merkel-visits-infineon-dresden-fab-2015-07/#sthash.XHTLv12Y.dpuf

 

Yesterday, flanked by two clean room engineers posing with 300 mm device wafers the Globalfoundries Managers Gregg Bartlett, Sanjay Jha (CEO) und Rutger Wijburg (VP and General Manager Fab1, Dresden) announce that Globalfoundries will invest $250 million for 22nm FD-SOI production in Fab 1 Dresden, Germany. From the press conference in Dresden (photo by Heiko Weckbrodt, www.computer-oiger.de)

UPDATE: ASM International technology briefing SEMICON West 2015

ASM International N.V.  announces that it will be hosting an analyst and investor technology briefing on Wednesday, July 15, 2015 at 8:00 - 9:30 a.m. (PDT) in San Francisco, US, coinciding with SEMICON West 2015. The presentation will be held in Room 301, Esplanade, Moscone Center.

 

ASMi is operating in a very close relationship with leading IDMs and Imec on CMOS scaling. In this technology seminar Han Westendorp, Vice President Corporate Marketing, will present "Advanced wafer processing with new materials". The presentation will include highlights of ASM's 

• Advanced thermal ALD
• Plasma enhanced ALD products and technologies
• CVD, PECVD and epitaxy technologies

The excellent presentation has now been released and can be downloaded here and some highlights you can find below: 

http://www.asm.com/Downloads/2015_Semicon_West_investor_technology_seminar_presentation.pdf

How scaling has been enabled by the introduction of new material and 3D integration.

Density scaling (continuing Moore’s law) driving towards higher mobility materials and alternate device architectures. Future systems will integrate much wider variety of materials and device structures

Here is a nice growing list of the materials and processes that has been introduced until now to drive scaling forward. Many of these process are perfumed by either Epitaxy, CVD/PECVD or ALD/PEALD.

Applied Materials announced a next-generation etch tool at SEMICON West

 Applied Materials, Inc. announced a next-generation etch tool at SEMICON West, the Applied Centris(TM) Sym3(TM) Etch system, featuring an entirely new chamber for atomic-level precision manufacturing. To overcome within-chip feature variations, the Centris Sym3 system leapfrogs current tools to provide chipmakers with the control and precision needed to pattern and create densely packed 3D structures in advanced memory and logic chips.

Applied Materials Centris Sym3 - an entirely new chamber for atomic-level precision manufacturing

"Drawing on over 20 years of etch learning and our expertise in precision materials removal, the Sym3 system represents a brand new design, built from the ground up, that solves persistent and impending industry challenges," said Dr. Raman Achutharaman, vice president and general manager of Applied's Etch business unit. "Customer traction has been remarkable, resulting in the fastest adoption rate we've seen for an etch tool in the company's history, with record ramp to production at leading-edge fabs."

The Centris Sym3 etch chamber employs Applied's unique True Symmetry(TM) technology with multiple tuning controls for optimizing global process uniformity to the atomic level. Key to the design is a focus on controlling and removing etch byproducts, which are increasingly hampering within-chip patterning uniformity. The system mitigates byproduct re-deposition to overcome the challenges of line edge roughness, pattern loading and defects - issues that are becoming more limiting for each successive technology node. Combined with an advanced RF technology that controls ion energy and angular distributions, the Sym3 system delivers unsurpassed vertical profiles for high aspect ratio 3D structures.

The Centris Sym3 platform's six etch and two plasma clean process chambers feature system intelligence software to ensure that every process in every chamber matches precisely, enabling repeatability and high productivity for high-volume manufacturing.

Imec and Panasonic Demonstrate Breakthrough RRAM Cell

Imec and Panasonic Corp. announced today that they have fabricated a 40nm TaOx-based RRAM (resistive RAM) technology with precise filament positioning and high thermal stability. This breakthrough result paves the way to realizing 28nm embedded applications. The results were presented at this year’s VLSI technology symposium (Kyoto, June 15-19 2015).

Cross-sectional TEM of 40-nm Ir(TE)/Ta2O5/TaOx/TaN (BE) RRAM

One of today’s most promising concepts for scaled memory is RRAM which is based on the electronic (current-or voltage-induced) switching of a resistor element material between two metals. Imec and Panasonic developed a method that overcomes filament instability in RRAM, one of the critical parameters that impacts the memory state during read operation in resistive memory. 

The method was realized using a combination of process technologies such as low-damage etching, cell side oxidation, and an innovative encapsulated cell structure with an Ir/Ta2O5/TaOx/TaN stacked film structure featuring a filament at the cell center. With these methods, a 2-Mbit 40nm TaOx-based RRAM cell with precise filament positioning and high thermal stability was achieved. The memory array showed excellent reliability of 100k cycles and 10 years’ retention at 85°C. Additionally, the filament control and thermal stability technologies offer the potential to realize 28nm cell sizes.

Gosia Jurczak, director of imec’s research program on RRAM devices stated: “With these breakthrough results, we have proven the potential of this promising memory concept as embedded nonvolatile memory in 28nm technology node where conventional NOR Flash shows scaling limitations. This result is a confirmation of our leadership position in research and development on resistive memory.”

Lam Research Releases High-Productivity VECTOR(R) ALD Oxide Deposition System

Lam Research Corp a major global supplier of innovative wafer fabrication equipment and services to the semiconductor industry, today announced it has released its high-productivity VECTOR® ALD Oxide system on the Extreme platform. The new product uses atomic layer deposition (ALD) to create highly conformal dielectric films with an emphasis on advanced patterning, in particular spacer-based multiple patterning. One key challenge is managing thickness variability of the self-aligned spacers that define critical dimensions (CDs). By delivering superior CD control, VECTOR ALD Oxide has been winning volume-production decisions for multi-patterning applications. Now leveraging Lam's Extreme platform, the latest system meets productivity requirements for continued scaling, where additional steps increase process time, cost, and complexity. As a result, VECTOR ALD Oxide is gaining rapid adoption by a number of leading chipmakers for advanced multi-step patterning applications.

"Multiple patterning continues to be a key inflection for the industry, and spacer-based multi-patterning remains an enabling strategy for chipmakers for both current immersion and future EUV lithography schemes," said Sesha Varadarajan, group vice president, Deposition Product Group. "With this in mind, we are working closely with our customers to deliver cost-effective, extendible solutions required for further scaling, such as the high-productivity atomic-scale control from our VECTOR ALD Oxide product."

By repeating lithography/etch/deposition steps, multiple patterning techniques create smaller features and higher feature densities compared to the capability of current optical lithography using single patterning. To enable scaling for 14 nm and below, chipmakers are adopting self-aligned schemes, including self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP), where deposition plays a critical role in forming the pattern-defining spacers. These deposition processes are challenging since they must form high-quality conformal and very uniform films. For example, a 200-300 angstrom-thick film can have only a few angstroms thickness variation across the wafer. For next-generation 10 nm processes, the manufacturing complexity will continue to increase as additional multi-patterning process steps are added, with each step contributing to overall CD variability.

Using Lam's advanced ALD capabilities, the latest VECTOR ALD Oxide system delivers the uniformity required for CD control of the ultra-thin films critical to SADP and SAQP schemes. The quad-station modules process four wafers simultaneously and share components to improve reliability and chamber matching, contributing to industry-leading wafer-to-wafer repeatability performance. The system's compact design delivers as much as 20% higher footprint productivity compared with other solutions. Process hardware has also been optimized to enable fast gas and RF switching, increasing throughput and reducing precursor usage for improved running costs. These innovative process module features combined with the high-productivity platform deliver the performance and cost-efficiency needed for manufacturing. Consequently, VECTOR ALD Oxide is winning development and production tool of record positions at leading manufacturers for advanced multi-patterning applications. This momentum is being successfully expanded to other applications, such as high-aspect ratio liners for through-silicon vias (TSVs) and image sensors.

Applied Materials to introduce a new system for Atomic Layer Deposition - Olympia™ ALD

Woah - this one we all have been waiting for - a paradigm shift in ALD processing by Applied Materials! I have not checked out all the details yet and yes it is a Spatial ALD machine and I am stunned with what I have seen so far : As announced today - Applied Materials to introduce a new system for Atomic Layer Deposition - Olympia™ ALD. Continued process scaling is driving new levels of device performance. ALD is essential for a growing number of the device-critical process steps in 3D NAND and logic FinFET fabrication. However, while the conformality and uniform film thickness achieved with ALD is still vital for CD control, additional demands are being made on ALD to deliver a growing range of high-quality, robust films within restrictive thermal budgets of next-generation nodes.

The Applied Olympia™ ALD system for stand-alone deposition of dielectric and metal films solves the significant challenge of obtaining high-quality ALD films at the low deposition temperatures needed to fabricate planar and 3D devices at next-generation nodes, delivering a new class of high-performance ALD.

Today’s ALD involves not only laying down a film by depositing a succession of layers each one atom thick. The process is also often accompanied by materials engineering (treatments) required to impart specific properties to these films. The Olympia system’s capabilities extend well beyond conventional solutions, performing the dual functions of deposition and materials engineering through flexible modular design. This modularity offers unmatched sequencing capabilities that solve the significant challenge of obtaining high-quality films at the low deposition temperatures required to manufacture today’s leading-edge memory and logic chips. The flexible design also enables the system to accommodate the wide variety of precursors and process/treatment combinations that will be needed to deliver the quality, diversity and thermal range of ALD processes anticipated for future generations of devices.

Video - In the Olympia chamber, wafers rotate through isolated zones of different chemistries. Here, each wafer is exposed to two chemistries in series; they react at the wafer surface to create a conformal monolayer of film. An additional monolayer is deposited with every exposure cycle. Treatment processes can be incorporated into the sequence for atomic-level materials engineering to meet specific customer needs. 

The Olympia ALD system is differentiated by innovative chemistry management that ensures absolute separation of the individual precursors used in the deposition process. This unique feature is crucial for minimizing the creation of potentially damaging byproducts and particles that can form when chemistries mix freely. Consequently, the system generates exceptionally few defects, running for extended periods between chamber cleanings. Furthermore, the system offers a more than 50 percent productivity benefit over conventional, time-separated ALD by eliminating the pump/purge step after each chemistry.

According to Solid State Technology Applied Materials formed a Patterning Group about a year ago, led by Prabu Raja, group vice president. The group handles etch, CVD, selective material removal and ALD. “The growth there has been tremendous,” Dickerson said. Dickerson said they have moved $400 million of investment in the company into these opportunities and into new products.

GLOBALFOUNDRIES Launches Industry’s First 22nm FD-SOI Technology Platform in Dresden

GLOBALFOUNDRIES today launched a new semiconductor technology developed specifically to meet the ultra-low-power requirements of the next generation of connected devices. The “22FDX™” platform delivers FinFET-like performance and energy-efficiency at a cost comparable to 28nm planar technologies, providing an optimal solution for the rapidly evolving mainstream mobile, Internet-of-Things (IoT), RF connectivity and networking markets.

Flanked by two clean room engineers posing with 300 mm device wafers the Globalfoundries Managers Gregg Bartlett, Sanjay Jha (CEO) und Rutger Wijburg today announced at a press event that Globalfoundries will invest $250 million for 22nm FD-SOI production in Fab 1 Dresden, Germany.

Flanked by two clean room engineers posing with 300 mm device wafers the Globalfoundries Managers Gregg Bartlett, Sanjay Jha (CEO) und Rutger Wijburg (VP and General Manager Fab1, Dresden) announce that Globalfoundries will invest $250 million for 22nm FD-SOI production in Fab 1 Dresden, Germany. From the press conference in Dresden (photo by Heiko Weckbrodt, www.computer-oiger.de)

While some applications require the ultimate performance of three-dimensional FinFET transistors, most wireless devices need a better balance of performance, power consumption and cost. 22FDX provides the best path for cost-sensitive applications by leveraging the industry’s first 22nm two-dimensional, fully-depleted silicon-on-insulator (FD-SOI) technology. It offers industry’s lowest operating voltage at 0.4 volt, enabling ultra-low dynamic power consumption, less thermal impact, and smaller end-product form-factors. The 22FDX platform delivers a 20 percent smaller die size and 10 percent fewer masks than 28nm, as well as nearly 50 percent fewer immersion lithography layers than foundry FinFET.

“The 22FDX platform enables our customers to deliver differentiated products with the best balance of power, performance and cost,” said Sanjay Jha, chief executive officer of GLOBALFOUNDRIES. “In an industry first, 22FDX provides real-time system software control of transistor characteristics: the system designer can dynamically balance power, performance, and leakage. Additionally, for RF and analog integration, the platform delivers best scaling combined with highest energy efficiency.”

"The 22nm process overcomes some challenges at 28nm. The transistor is better and the 20 percent area scaling we get makes up for the cost of the substrate," Jha said. "That means we can offer better performance at the same cost as 28nm [alternatives to FD-SOI]," Jha added in EE Times Europe.

 

The Dresden Fab 1 with a capacity: 60,000 wafers/month (300 mm)Technology: 45nm to 28nm and now also 22 nm (www.globalfoundries.com)

22FDX leverages the high-volume 28nm platform in GLOBALFOUNDRIES’ state-of-the-art 300mm production line in Dresden, Germany. This technology heralds a new chapter in the “Silicon Saxony” story, building on almost 20 years of sustained investment in Europe’s largest semiconductor fab. GLOBALFOUNDRIES launches its FDX platform in Dresden by investing $250 million for technology development and initial 22FDX capacity. This brings the company’s total investment in Fab 1 to more than $5 billion since 2009. The company plans to make further investments to support additional customer demand. GLOBALFOUNDRIES is partnering with R&D and industry leaders to grow a robust ecosystem and to enable faster time-to-market as well as a comprehensive roadmap for its 22FDX offering. 

Full story here: http://globalfoundries.com/newsroom/press-releases/2015/07/13/globalfoundries-launches-industry-s-first-22nm-fd-soi-technology-platform

Furthermore, Rutger Wijburg, senior vice president and general manager of the Dresden Fab 1, acknowledged that Globalfoundries is taking part in European Commission administered projects such as Horizon 2020. "We plan to extend that activity," Wijburg said according to EE Times Europe. As far as I know one of them is WAY-TO-GO CMOS headed by ST Microelectronics

GLOBALFOUNDRIES Webinar: Extending Moore's Law with FD-SOI Technology

"Extending Moore's Law with FD-SOI Technology" is part of the GLOBALFOUNDRIES Technical Webinar Series. Jamie Schaeffer, Ph.D. explains how FDSOI (Fully Depleted Silicon On Insulator) technology is extending the life of Moore's Law.

Only available by this link : https://www.youtube.com/watch?v=7VmQlpXKtHE#t=100

It has previously been announced this year that Globalfoundries will entry FDSOI at 22 nm and today there will be a press conference in Dresden in front of the Bundeskanslerin Angela Merkels visit to the Dresden Fab tomorrow (Fab 1).

News & Analysis

GlobalFoundries’ FD-SOI Revolution

Junko Yoshida

6/23/2015 06:16 PM EDT 
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GRENOBLE, France — The appearance of Gerd Teepe, director and design engineering at GlobalFoundries, at a CEA-Leti-sponsored FD-SOI workshop here has confirmed, once again, rumors surrounding the company’s upcoming “big announcement” about FD-SOI.
Teepe offered, in broad strokes, GlobalFoundries' FD-SOI time schedule. While it was no formal announcement, his presentation implied the company’s oft-leaked but never confirmed big plans in FD-SOI.
Teepe came to Grenoble, ostensibly, to end the suspense.
He said, “We are developing 22nm FD-SOI process technology right now.” The plan is to qualify the process by early 2016 and start volume production by the end of 2016. Asked about what the company’s 22nm FD-SOI process entails, Teepe explained, “We are using STMicroelectronics’ 14nm FD-SOI in our frontend, while using 28nm FD-SOI in the backend.”

[...]

Chalmers show Graphene-based film that be used for efficient cooling of electronics

Researchers at Chalmers University of Technology have developed a method for efficiently cooling electronics using graphene-based film. The film has a thermal conductivity capacity that is four times that of copper. Moreover, the graphene film is attachable to electronic components made of silicon, which favours the film’s performance compared to typical graphene characteristics shown in previous, similar experiments.

Graphene-based film on an electronic component with high heat intensity. Image: Johan Liu

Electronic systems available today accumulate a great deal of heat, mostly due to the ever-increasing demand on functionality. Getting rid of excess heat in efficient ways is imperative to prolonging electronic lifespan, and would also lead to a considerable reduction in energy usage. According to an American study, approximately half the energy required to run computer servers, is used for cooling purposes alone.

A couple of years ago, a research team led by Johan Liu, professor at Chalmers University of Technology, were the first to show that graphene can have a cooling effect on silicon-based electronics. That was the starting point for researchers conducting research on the cooling of silicon-based electronics using graphene.

“But the methods that have been in place so far have presented the researchers with problems”, Johan Liu says. “It has become evident that those methods cannot be used to rid electronic devices off great amounts of heat, because they have consisted only of a few layers of thermal conductive atoms. When you try to add more layers of graphene, another problem arises, a problem with adhesiveness. After having increased the amount of layers, the graphene no longer will adhere to the surface, since the adhesion is held together only by weak van der Waals bonds."

“We have now solved this problem by managing to create strong covalent bonds between the graphene film and the surface, which is an electronic component made of silicon,” he continues.

The stronger bonds result from so-called functionalisation of the graphene, i.e. the addition of a property-altering molecule. Having tested several different additives, the Chalmers researchers concluded that an addition of (3-Aminopropyl) triethoxysilane (APTES) molecules has the most desired effect. When heated and put through hydrolysis, it creates so-called silane bonds between the graphene and the electronic component (see picture).

Moreover, functionalisation using silane coupling doubles the thermal conductivity of the graphene. The researchers have shown that the in-plane thermal conductivity of the graphene-based film, with 20 micrometer thickness, can reach a thermal conductivity value of 1600 W/mK, which is four times that of copper.

“Increased thermal capacity could lead to several new applications for graphene,” says Johan Liu. "One example is the integration of graphene-based film into microelectronic devices and systems, such as highly efficient Light Emitting Diodes (LEDs), lasers and radio frequency components for cooling purposes. Graphene-based film could also pave the way for faster, smaller, more energy efficient, sustainable high power electronics."

Facts about the research:

The results were recently published in the renowned journal Advanced Functional Materials:

Improved Heat Spreading Performance of Functionalized Graphene in Microelectronic Device Application

The research was conducted in collaboration with Shanghai University in China, Ecole Centrale Paris and EM2C – CNRS in France, and SHT Smart High Tech in Sweden.

Chalmers University of Technology conducts research and offers education in technology, science, shipping and architecture with a sustainable future as its global vision. Chalmers is well-known for providing an effective environment for innovation and has eight priority areas of international significance – Built Environment, Energy, Information and Communication Technology, Life Science Engineering, Materials Science, Nanoscience and Nanotechnology, Production, and Transport. 

Graphene Flagship, an FET Flagship initiative by the European Commission, is coordinated by Chalmers. Situated in Gothenburg, Sweden, Chalmers has 10,300 full-time students and 3,100 employees.

TEL Begins Accepting Orders for Triase+™ EX-II™ TiN Plus, a Single-Wafer Metallization System

As announced today - Tokyo Electron Limited (TEL) announced today that it began accepting orders for the Triase+TM EX-IITM TiN* Plus, a successor to the Triase+ EX-II TiN single-wafer metallization system, in July, 2015.

The existing Triase+ EX-II TiN is a high-speed single-wafer ASFD (Advanced Sequential Flow Deposition) system with an optimized reactor chamber and unique gas injection mechanism. Since its introduction in January 2013, the Triase+ EX-II TiN has established itself as a standard for single-wafer ASFD TiN metallization systems, and has been adopted by customers throughout the world for manufacturing memory and logic devices.

As the latest memory and logic designs require increasingly smaller feature sizes and higher aspect ratios, manufacturers today need the key technology to deposit uniform TiN thin films on complex surface structures in order to improve device yield. The Triase+ EX-II TiN Plus features new reactor chamber and gas injection mechanism designs, significantly improving within-wafer uniformity, step coverage, and productivity. Customers can also upgrade their existing Triase+ EX-II TiN systems to Triase+ EX-II TiN Plus, which helps them save investment costs.

"The Triase+ EX-II TiN Plus is the latest system that fully incorporates the technical expertise we have gained with the Triase+ EX-II TiN, and represents a major improvement over its predecessor," said Takeshi Okubo, Executive Officer and General Manager, SDBU at TEL. "The technology we adopted for this system will also be used in the upcoming Triase+ EX-II series of tools, extending the ASFD processing capability to materials other than TiN. We also challenge ourselves to develop even more sophisticated technologies and continue to provide high value-added systems for a wide range of thin film applications."

Summer school on Atomic Layer Deposition in Brescia, Italy

Yet another great ALD event has been successfully organized with partial support by the European ALD network HERALD! If you have additional pictures from the event please send them to me and I will post them below (jonas.sundqvist@baldengineering.com).

Picture of the course delegates (Maria Berdova, LinkedIn, Original photo courtesy to Bence Parditka)

The Summer school “Atomic Layer Deposition: Method and Applications” was held in Brescia, from the 6th to 10th July 2015 at Collegio Universitario Luigi Lucchini.

The event wa organized by INSTM in collaboration with Department of Mechanical and Industrial Engineering (DIMI, University of Brescia) and COST (European Cooperation in Science and Technology, HERALD COST Action MP1402).

The Scientific Coordinator is prof. Laura Depero, Department of Mechanical and Industrial Engineering, University of Brescia.

Course objectives:

• learn the fundamentals of ALD based on sequential self-limiting surface reactions
• understand the important advantages of ALD and comparison with other deposition techniques
• learn about ideal and non-ideal ALD and thermal and plasma-enhanced ALD.
• understand how ALD surface chemistry and growth are studied using in situ probes
• learn how ALD can be used for thin film nanoengineering
• understand the many current and potential applications of ALD

Thermo Scientific present Angle resolved XPS Metrology solution for ALD High-k Dielectrics

Many of you in the ALD and High-k business have used or are using XPS to analyze high-k material like HfO2 - pure, mixed or doped with other oxides and elements like SiO2, Al2O3, La2O3, Cl, F, ...

I know for sure that XPS is use as a standard metrology method post high-k deposition in many 300 mm fabs. This is not restricted to mapping just blanket monitor wafers but also to measurement directly on product wafers. In advanced logic and DRAM memory this can be done at different positions in the integration flow depending on the technology (High-k first or last or hybrid, DRAM capacitors) - so it is an established method for high-k in production.

Now the gate stack or advanced stacks for various memory devices (e.g. DRAM, RRAM, FRAM) does not really consist of any bulk material anymore - it has come down to be a extremely advanced stack of ultra thin interfaces. Not even the substrate is bulk any more id you think about HALO doping profiles and FD-SOI technology. That it is why it is interesting to read those application paper from Thermo Scientific – Surface Analysis and Microanalysis on mapping High-k wafers using Angle Resolved XPS of 200 mm wafers. I have included some of the information below for the full paper please download it here from the Thermo Scientific application library : Characterization of high-k dielectric materials on silicon using Angle Resolved XPS

Thickness line scan across the diameter of the 200 mm wafer showing the variation of the thickness of the mixed Al2O3 and HfO2 layer and the thickness of the SiO2 interfacial layer.

XPS maps of Al 2p (upper left) and Hf 4f (lower left) from a 200 mm wafer. XPS maps of O 1s. The lower right map is oxygen in a state with a low binding energy (usually associated with hafnium). The upper right map is oxygen in a state with a high binding energy (usually associated with aluminum and silicon). 

Example of a depth profile through a sample HfO2 on SiO2 on Si. The profile was constructed from ARXPS data.

Thermo Scientific Theta Probe and Theta 300 provide essential information for the next generation of gate dielectrics:

• Layer thickness 

• Thickness of the intermediate layer

• Chemical states of the layer and the intermediate layer • Uniformity of the layers

• Distribution of the material within the layer 

ARXPS is non-destructive and avoids the use of sputtering with an ion beam. Sputtering has been shown to alter the composition of the layer and causes atomic mixing both of which can cause a misinterpretation of the data.

ALD equipment market keeps on booming!

Good news guys - the deposition equipment market will continue to grow, which is good news for our friends at CVD, Epitaxy and PVD. This is in spite of that The Merge was called off and probably most people are happy about this. So now to the real, relay good news ALD will outperform them all in growth, yep ALD is growing faster than CVD and PVD!

To put it in perspective and summarize:

45 nm - check
32 nm - check, check

20/22 nm - check, check, check

14/16 nm - check, check, check, check, check, check, check

7/10 nm - check, check, check, check, check, check, check, check, check, check, check, check, check, check

According to Solid State Technology and Global Industry Analysts (GIA) forecasts the global deposition equipment market will hit $13.6 billion by 2020. Atomic layer deposition (ALD) will be the fastest growing segment, with a compound annual growth rate of 19.9 percent, the market research firm estimates.

The main players are:

Applied Materials and Tokyo Electron f.k.a Eteris - together holding almost 60% of the worldwide market and after the non-merger Applied will remain in the lead followed by Lam Research (acquired Novellus Systems 2012), AIXTRON, ASM International, and other competitors.

"Chemical vapor deposition (CVD) will be the second largest deposition segment through the end of this decade, followed by physical vapor deposition (PVD) and epitaxy, according to GIA. Japanese vendors, namely Hitachi Kokusai Electric/Kokusai Semiconductor Equipment and Tokyo Electron, dominate the worldwide CVD market, with significant market shares held by Applied Materials, ASM International, and Lam Research, the market research firm states."

Geographically Taiwan is the world’s largest market for deposition equipment according to SEMI (above). Interesting here is to see that China is growing at a steady right and is about half in spending as compared to Taiwan.

Let´s assume there will be more of this coming from SEMICON West 2015!

Etching: A crucial step in semiconductor manufacturing

As published recently by Solid State Technology : Plasma etching is a key step in wafer fabrication, from deposition to the patterning of photolithography to dry or wet etch. As such, it is a crucial and hotly-contested area for vendors of semiconductor manufacturing equipment.

Lam Research holds about half of the worldwide etch equipment market and principally competes with Applied Materials, Tokyo Electron, and Hitachi High-Technologies.

In May, Lam introduced the Kiyo F Series conductor etch system for volume production of advanced DRAMs and 3D NAND flash memory devices. Lam says the Kiyo F Series is employed for critical conductor etch applications at “all major memory manufacturers.”

A year ago, Lam brought out the 2300 Kiyo F Series with the Hydra Uniformity System, which corrects for critical-dimension non-uniformities on the incoming wafer. The company also unveiled an atomic layer etch (ALE) capability on the 2300 Kiyo F Series conductor etch system, which is paired with Lam’s atomic layer deposition (ALD) systems, the VECTOR ALD Oxide system for dielectric film ALD and the ALTUS system for tungsten metal film ALD.

Applied Materials and Tokyo Electron set plans in 2013 to merge their companies. The merged company, to be called Eteris, would have commanded about one-third of the worldwide etching equipment market. The merger was called off in April, however, as U.S. antitrust regulators indicated that they would not approve the transaction.

SEMI cheered a decision by the U.S. Department of Commerce in February to remove export controls on certain etch equipment, concluding a four-month investigation. SEMI had petitioned the federal government agency in July 2014 to look at the foreign availability of anisotropic plasma dry etching equipment.

“SEMI stands for free trade and open markets to support the development and success of the global semiconductor manufacturing industry supply chain,” Denny McGuirk, president and CEO of SEMI, said in a statement. “We applaud the decontrol of semiconductor etch equipment as a rational response to current technology, trade, and commercial realities. This is a win for both equipment makers and their customers operating in the global market.”

“The Commerce Department’s decision to remove export control restrictions for etch equipment is a big victory for the U.S. semiconductor equipment sector and our customers around the world,” said Randhir Thakur, executive vice president and general manager of the Silicon Systems Group at Applied Materials. “Recognizing the availability of these tools will help fuel growth and promote the success of the global industry supply chain.”

In May, imec and Tokyo Electron presented a direct copper etch scheme for patterning copper interconnections. This would replace the usual copper damascene process, according to imec and TEL. The Belgian research organization worked with nine leading chipmakers on developing the direct copper etch technology.

Dry or wet, etching technology will be the subject of discussions at the SEMICON West 2015 conference and exhibition.

IBM present the first functional 7nm FinFET Test Wafer

An alliance led by IBM Research today announced that it has produced the semiconductor industry’s first 7nm (nanometer) node test chips with functioning transistors. The breakthrough, accomplished in partnership with GLOBALFOUNDRIES and Samsung at SUNY Polytechnic Institute’s Colleges of Nanoscale Science and Engineering (SUNY Poly CNSE), could result in the ability to place more than 20 billion tiny switches -- transistors -- on the fingernail-sized chips that power everything from smartphones to spacecraft.

With 20+ billion transistors on new chip, that's a 50% scaling improvement over today’s tech (IBM, Twitter)

To achieve the higher performance, lower power and scaling benefits promised by 7nm technology, researchers had to bypass conventional semiconductor manufacturing approaches. Among the novel processes and techniques pioneered by the IBM Research alliance were a number of industry-first innovations, most notably Silicon Germanium (SiGe) channel transistors and Extreme Ultraviolet (EUV) lithography integration at multiple levels.

Professor Michael Liehr (left) of SUNY Polytechnic Institute's Colleges of Nanoscale Science and Engineering (SUNY Poly CNSE) and Bala Haran (right) of IBM Research inspect 7-nanometer wafer of test chips developed in alliance partnership between IBM and SUNY Poly CNSE. (IBM)

Industry experts consider 7nm technology crucial to meeting the anticipated demands of futurecloud computing and Big Data systems, cognitive computing, mobile products and other emerging technologies. Part of IBM’s $3 billion, five-year investment in chip R&D (announced in 2014), this accomplishment was made possible through a unique public-private partnership with New York State and joint development alliance with GLOBALFOUNDRIES, Samsung, and equipment suppliers. The team is based at SUNY Poly’s NanoTech Complex in Albany.

TEM image of IBM's 7-nanometer node finned field effect transistors (FinFETs) packed below 30-nanometer fin pitch using self aligned patterning. (IBM Research)

“For business and society to get the most out of tomorrow’s computers and devices, scaling to 7nm and beyond is essential,” said Arvind Krishna, senior vice president and director of IBM Research. “That’s why IBM has remained committed to an aggressive basic research agenda that continually pushes the limits of semiconductor technology. Working with our partners, this milestone builds on decades of research that has set the pace for the microelectronics industry, and positions us to advance our leadership for years to come.”

According to IBM the first  7nm chips announced, today was ably possible because of the past breakthroughs listed here (IBM, Twitter)

Microprocessors utilizing 22nm and 14nm technology power today’s servers, cloud data centers and mobile devices, and 10nm technology is well on the way to becoming a mature technology. The IBM Research-led alliance achieved close to 50 percent area scaling improvements over today’s most advanced technology, introduced SiGe channel material for transistor performance enhancement at 7nm node geometries, process innovations to stack them below 30nm pitch and full integration of EUV lithography at multiple levels. These techniques and scaling could result in at least a 50 percent power/performance improvement for next generation mainframe and POWER systems that will power the Big Data, cloud and mobile era.

Congratulations to Globalfoundries taking over IBM Chip buisness. Here is a picture from the cake eaten at Globalfoudries to celebrate (Picture from a friend).

“Governor Andrew Cuomo’s trailblazing public-private partnership model is catalyzing historic innovation and advancement. Today’s announcement is just one example of our collaboration with IBM, which furthers New York State’s global leadership in developing next generation technologies,” said Dr. Michael Liehr, SUNY Poly Executive Vice President of Innovation and Technology and Vice President of Research. “Enabling the first 7nm node transistors is a significant milestone for the entire semiconductor industry as we continue to push beyond the limitations of our current capabilities.”

"Today’s announcement marks the latest achievement in our long history of collaboration to accelerate development of next-generation technology," said Gary Patton, CTO and Head of Worldwide R&D at GLOBALFOUNDRIES. "Through this joint collaborative program based at the Albany NanoTech Complex, we are able to maintain our focus on technology leadership for our clients and partners by helping to address the development challenges central to producing a smaller, faster, more cost efficient generation of semiconductors." 

The 7nm node milestone continues IBM’s legacy of historic contributions to silicon and semiconductor innovation. They include the invention or first implementation of the single cell DRAM, the Dennard Scaling Laws, chemically amplified photoresists, copper interconnect wiring, Silicon on Insulator, strained engineering, multi core microprocessors, immersion lithography, high speed SiGe, High-k gate dielectrics, embedded DRAM, 3D chip stacking and Air gap insulators.

IBM and SUNY Poly have built a highly successful, globally recognized partnership at the multi-billion dollar Albany NanoTech Complex, highlighted by the institution's Center for Semiconductor Research (CSR), a $500 million program that also includes the world's leading nanoelectronics companies. The CSR is a long-term, multi-phase, joint R&D cooperative program on future computer chip technology. It continues to provide student scholarships and fellowships at the university to help prepare the next generation of nanotechnology scientists, researchers and engineers.

For more information about SUNY Polytechnic Institute, visit www.sunycnse.com andwww.sunypoly.edu.

MIT develops Supercapacitors from Niobium Nanowire Yarns for wearable electronics

As reported by MIT News : Wearable electronic devices for health and fitness monitoring are a rapidly growing area of consumer electronics; one of their biggest limitations is the capacity of their tiny batteries to deliver enough power to transmit data. Now, researchers at MIT and in Canada have found a promising new approach to delivering the short but intense bursts of power needed by such small devices.

The key is a new approach to making supercapacitors — devices that can store and release electrical power in such bursts, which are needed for brief transmissions of data from wearable devices such as heart-rate monitors, computers, or smartphones, the researchers say. They may also be useful for other applications where high power is needed in small volumes, such as autonomous microrobots.

The new approach uses yarns, made from nanowires of the element niobium, as the electrodes in tiny supercapacitors (which are essentially pairs of electrically conducting fibers with an insulator between). The concept is described in a paper in the journal ACS Applied Materials and Interfaces by MIT professor of mechanical engineering Ian W. Hunter, doctoral student Seyed M. Mirvakili, and three others at the University of British Columbia.

Here below is the abstract for the publication or you can continue reading the story from MIT News.

High-Performance Supercapacitors from Niobium Nanowire Yarns

Seyed M. Mirvakili, Mehr Negar Mirvakili, Peter Englezos, John D. W. Madden, and Ian W. Hunter

ACS Appl. Mater. Interfaces, 2015, 7 (25), pp 13882–13888
DOI: 10.1021/acsami.5b02327

The large-ion-accessible surface area of carbon nanotubes (CNTs) and graphene sheets formed as yarns, forests, and films enables miniature high-performance supercapacitors with power densities exceeding those of electrolytics while achieving energy densities equaling those of batteries.1−7 Capacitance and energy density can be enhanced by depositing highly pseudocapacitive materials such as conductive polymers on them.3,8−15 Yarns formed from carbon nanotubes are proposed for use in wearable supercapacitors.3,16 In this work, we show that high power, energy density, and capacitance in yarn form are not unique to carbon materials, and we introduce niobium nanowires as an alternative. These yarns show higher capacitance and energy per volume and are stronger and 100 times more conductive than similarly spun carbon multiwalled nanotube (MWNT) and graphene yarns.6,17−22 The long niobium nanowires, formed by repeated extrusion and drawing,17 achieve device volumetric peak power and energy densities of 55 MW·m–3 (55 W·cm–3) and 25 MJ·m–3 (7 mWh·cm–3), 2 and 5 times higher than that for state-of-the-art CNT yarns, respectively.3 The capacitance per volume of Nb nanowire yarn is lower than the 158 MF·m–3 (158 F·cm–3) reported for carbon-based materials such as reduced graphene oxide (RGO) and CNT wet-spun yarns,5 but the peak power and energy densities are 200 and 2 times higher, respectively.5 Achieving high power in long yarns is made possible by the high conductivity of the metal, and achievement of high energy density is possible thanks to the high internal surface area. No additional metal backing is needed, unlike for CNT yarns and supercapacitors in general, saving substantial space. As the yarn is infiltrated with pseudocapacitive materials such as poly(3,4-ethylenedioxythiophene) (PEDOT), the energy density is further increased to 10 MJ·m–3 (2.8 mWh·cm–3). Similar to CNT yarns, niobium nanowire yarns are highly flexible and show potential for weaving into textiles and use in wearable devices.

Atomic layer deposition technology finds path to medical market via drug-delivery systems

I know I covered this before but it is just so cool technology. Just take a moment and think about all the possibilities and how big this market is. Here is another angle on the story - Republished form : Plastics Today

Atomic layer deposition technology finds path to medical market via drug-delivery systems

Finland-based supplier of atomic layer deposition (ALD) technology Picosun Oy (Espoo) recently announced that it has entered the medical market via drug-delivery systems developed by Nanexa AB (Uppsala, Sweden).

ALD enables the deposition of hermetic, ultra-thin layers of metals, polymers and other materials on a range of products. The technology's capability to cover very small parts with complex geometries gives it an attractive profile for medical device applications. The coating increases operational life, reliability and safety of medical equipment and enables advanced synthesis, delivery and dosing of medical substances, says the company. Several biocompatible coating materials are available, and because it is a gas-phase, low-temperature method, the ALD process can be used to coat sensitive plastic substrates in medical products. Picosun did not disclose the specific material used in the Nanexa application.

Nanexa is specialized in the development of nanotechnology-enabled drug-delivery systems that, it says, "create new possibilities for drug formulations and drug release." Its signature PharmaShell technology encapsulates solid drug particles in the nano- to micrometer range within an extremely thin shell made from a soluble, mineral compound. The thickness of the shell determines the time-release properties and allows precise therapeutic tailoring. The shell, which is created by ALD technology, completely dissolves and exits the body.

Picosun ALD process tools are used primarily in the semiconductor industry as well as in microelectromechanical and light-emitting diode production. The technology also has applications in the deposition of protective, decorative and biocompatible coatings, and is widely used in high-level research institutes across the world.

Picosun would like to see its technology make further inroads into medical applications. To this point, it is involved in the InForMed project, a European Union (EU) initiative to develop an integrated micro-fabrication pilot line for medical device production that incorporates the full innovation chain from concept to system qualification. The project, which is funded by the EU ECSEL JU public-private partnership, began in June 2015 and runs until May 2018.

PneumatiCoat completes DOE Project for a Battery Pilot Plant and recieves US Navy funding

Battery cathode materials with improved safety and performance. Picoshield® coatings provide improvements on many of the most common Li-ion cathode materials used today. As the leader in ALD battery materials PneumatiCoat (PCT) can attain cutting edge performance out of existing battery materials, both cathode and anode. 

Recently has had success in finalizing and receiving additional DOE funded projects as reported here:

PCT Presenting at DOE Annual Merit Review in Arlington, VA

June 2015 - PCT is presenting the most recent results from our DOE Phase II project. With the completion of our pilot plant, large format Picoshield® battery cells are built and producing excellent data. The results expand on the positive work conducted during the Phase I by proving out the quality, consistency, and throughput achievable using our high throughput system. The Annual Merit Review showcases DOE funded research in the fields of hydrogen, fuel cells, and vehicle technologies.

PCT Awarded NAVY SBIR Phase I for "Long Lasting, Highly Efficient, and Safe Batteries for Sensor Systems"

June 2015 - Pneumaticoat Technologies has been awarded a DOD Phase I SBIR from the Navy to develop improved batteries for sensor systems. This work will focus on improving the overall safety of the battery systems and improving the lifetime performance of critical, battery operated, sensors. Picoshield® coatings will play a crucial role in improving battery performance.

More informsation can be found here: http://www.pneumaticoat.com/news.html 

 

By incorporating well established manufacturing principles (continuous vs. batch, variable throughput vs. fixed throughput, etc.), PneumatiCoat Technologies has developed an efficient and cheap process for precise coating of powders, flats, and objects. Thanks to our innovative process design and system building know-how, Pneumaticoat Technologies is pushing the boundaries of ALD for manufacturing. With our technology, the days of ALD being too slow and too expensive are over. With high throughput manufacturing capabilities, at inexpensive price points, a great majority of the application technologies that were "put on the shelf" can now be reconsidered as viable commercial products. Combined with the exponential growth in application R&D, PneumatiCoat Technologies' systems are well-poised to help usher in a new wave of customized products to market. (http://www.pneumaticoat.com)

Integration of Sub-10 nm ALD Gate Oxide on MoS2 with Ultra Low Leakage and Enhanced Mobility

Here is a nice Open Source report (Scientific Reports 5, Article number: 11921 (2015) doi:10.1038/srep11921) on integration of Sub-10 nm Gate Oxide on MoS2 with Ultra Low Leakage and Enhanced Mobility. 

Atomic layer deposition of Al2O3 on MoS2 flakes was performed according to the paper, some of the MoS2 flakes were loaded into the Picosun R200 ALD chamber for direct Al2O3 deposition. During the deposition, TMA and H2O served as the aluminum and oxygen precursors, respectively, and different growth temperatures and pulse time were adopted to observe their impacts. For some of the flakes, the remote O2 plasma pretreatments were carried out in the same chamber before Al2O3 was deposited.

(a) Cross-sectional schematic of the top-gated devices together with the electrical connections. (b) Ids – Vtg curves with Vds ranging from 50 mV to 500 mV. The inset shows the Ids – Vds curves with the top gate voltages of 0 V and 2 V. (c) Top gate leakage current of the device. Optical image of the top gate device is attached as the inset of (c). Top gate dielectric of this device is 60 cycles Al2O3 deposited with 60 s remote oxygen plasma pretreatment. All these measurements were performed at room temperature with the back gate grounded (Scientific Reports 5, Article number: 11921 (2015) doi:10.1038/srep11921) .

Redeposition effects in plasma-assisted atomic layer deposition

Here it is - a very important study published by Oxford Instruments and TU Eindhoven on "redeposition effects" in plasma-assisted atomic layer deposition - not to be confused with "CVD effects" or "thermal decomposition of precursor effects" or other disturbing effects make the life as a ALD process guy non-conformal.

Redeposition in plasma-assisted atomic layer deposition: Silicon nitride film quality ruled by the gas residence time 

Harm C. M. Knoops, K. de Peuter and W. M. M. Kessels
Appl. Phys. Lett. 107, 014102 (2015); http://dx.doi.org/10.1063/1.4926366

The requirements on the material properties and growth control of silicon nitride (SiN x ) spacer films in transistors are becoming ever more stringent as scaling of transistor structures continues. One method to deposit high-quality films with excellent control is atomic layer deposition (ALD). However, depositing SiN x by ALD has turned out to be very challenging. In this work, it is shown that the plasma gas residence time τ is a key parameter for the deposition of SiN x by plasma-assisted ALD and that this parameter can be linked to a so-called “redeposition effect”. This previously ignored effect, which takes place during the plasma step, is the dissociation of reaction products in the plasma and the subsequent redeposition of reaction-product fragments on the surface. For SiN x ALD using SiH2(NH t Bu)2 as precursor and N2 plasma as reactant, the gas residence time τ was found to determine both SiN x film quality and the resulting growth per cycle. It is shown that redeposition can be minimized by using a short residence time resulting in high-quality films with a high wet-etch resistance (i.e., a wet-etch rate of 0.5 nm/min in buffered HF solution). Due to the fundamental nature of the redeposition effect, it is expected to play a role in many more plasma-assisted ALD processes.