Showing posts with label metrology. Show all posts
Showing posts with label metrology. Show all posts

Wednesday, April 14, 2021

Characterization of Annealing and Dopant Activation Processes Using Differential Hall Effect Metrology (DHEM) by Active Layer Parametrics (ALP) Inc.

ALP’s Differential Hall Effect Metrology (DHEM) technique is the only technique that directly measures active dopant concentration, mobility, and resistivity depth profiles through semiconductor layers at sub-nm depth resolution (

Above, cross-sectional TEM images of the P ion-implanted samples after annealing and corresponding depth profiles from DHEM.

ALP´s latest work employing this innovative technology and ALPro(TM) electrical profiling tools are summarized in a new invited paper titled “Characterization of Annealing and Dopant Activation Processes Using Differential Hall Effect Metrology (DHEM)”, which will be presented at the 239th ECS Meeting (May 30 to June 3 2021).

They showcase data developed jointly with Imec, Belgium, and Taiwan Semiconductor Research Institute (TSRI, Hsinchu) in the paper. You can read the abstract at ( If you are interested in reading the full paper, please contact Dr. Joshi below for a preprint.

Abhijeet 'AJ' Joshi, PhD
Active Layer Parametrics (ALP) Inc.

Monday, November 21, 2016

Sub 7nm Metrology is tough

Why the semiconductor industry needs breakthroughs, and why it’s getting tougher to provide them.

Sunday, July 12, 2015

Thermo Scientific present Angle resolved XPS Metrology solution for ALD High-k Dielectrics

Many of you in the ALD and High-k business have used or are using XPS to analyze high-k material like HfO2 - pure, mixed or doped with other oxides and elements like SiO2, Al2O3, La2O3, Cl, F, ...

I know for sure that XPS is use as a standard metrology method post high-k deposition in many 300 mm fabs. This is not restricted to mapping just blanket monitor wafers but also to measurement directly on product wafers. In advanced logic and DRAM memory this can be done at different positions in the integration flow depending on the technology (High-k first or last or hybrid, DRAM capacitors) - so it is an established method for high-k in production.

Now the gate stack or advanced stacks for various memory devices (e.g. DRAM, RRAM, FRAM) does not really consist of any bulk material anymore - it has come down to be a extremely advanced stack of ultra thin interfaces. Not even the substrate is bulk any more id you think about HALO doping profiles and FD-SOI technology. That it is why it is interesting to read those application paper from Thermo Scientific – Surface Analysis and Microanalysis on mapping High-k wafers using Angle Resolved XPS of 200 mm wafers. I have included some of the information below for the full paper please download it here from the Thermo Scientific application library : Characterization of high-k dielectric materials on silicon using Angle Resolved XPS

Thickness line scan across the diameter of the 200 mm wafer showing the variation of the thickness of the mixed Al2O3 and HfO2 layer and the thickness of the SiO2 interfacial layer.

XPS maps of Al 2p (upper left) and Hf 4f (lower left) from a 200 mm wafer. XPS maps of O 1s. The lower right map is oxygen in a state with a low binding energy (usually associated with hafnium). The upper right map is oxygen in a state with a high binding energy (usually associated with aluminum and silicon). 

Example of a depth profile through a sample HfO2 on SiO2 on Si. The profile was constructed from ARXPS data.

Thermo Scientific Theta Probe and Theta 300 provide essential information for the next generation of gate dielectrics:

• Layer thickness 
• Thickness of the intermediate layer
• Chemical states of the layer and the intermediate layer • Uniformity of the layers
• Distribution of the material within the layer 

ARXPS is non-destructive and avoids the use of sputtering with an ion beam. Sputtering has been shown to alter the composition of the layer and causes atomic mixing both of which can cause a misinterpretation of the data.