Chipmetrics Launches New Test Chips for Advanced Atomic Layer Processes

Finnish 3D thin film semiconductor metrology specialist launches new PillarHall LHAR5 test chip with 100 nanometer gap height, complements its metrology solution with new ASD-1 chip for Area Selective Deposition.

Joensuu, Finland – July 15th, 2024 – Chipmetrics Oy, an innovative metrology solutions provider to the semiconductor industry, announces the launch of two new test chips, the PillarHall LHAR5 and the ASD-1. The PillarHall LHAR5 silicon test chip builds on the success of its predecessor PillarHall LHAR4, with the new LHAR5 test chips being better suited for the most advanced 3D semiconductor device high aspect ratio structures with a gap height as low as 100 nm. Fitting seamlessly into Chipmetrics’ pocket wafer concept, it also allows for fast and accurate process control with full 300-millimeter compatibility.

The PillarHall LHAR5 test chip comes in two variations, with a 100-nanometer and a 500-nanometer gap height. The new 100-nanometer gap height allows engineers to research and compare possible dimensional effects in film penetration depth in line with 500-nanometer gap chips. This allows for new insights into film conformality control and a deeper understanding of 3D NAND, DRAM and other nanoelectronics containing high aspect ratio structures.

“With the launch of PillarHall LHAR5, ASD-1 and the 300-millimeter pocket wafer concept our product line is compatible with the most advanced and challenging semiconductor deposition and etch technologies like ALD, ALE and ASD. The Chipmetrics test chips with our pocket wafer concept is directly compatible with and ready to be used in all existing deposition tools,” says Mikko Utriainen, CEO of Chipmetrics.

The Chipmetrics ASD-1: Prototyping and Process Control for Area Selective Deposition workflows

Launched concurrently with the PillarHall LHAR5 is the Chipmetrics ASD-1 test chip, for prototyping and process control of Area Selective Deposition (ASD) workflows. As the name implies, ASD allows for selective growth of thin films on specific substrate areas, while avoiding it on others, with the ASD-1 test chip aiming to give customers easy access to high-quality data for process control and R&D.

The ASD-1 test chip features a high surface planarity, low line edge roughness, and small line widths which are crucial for ASD applications in advanced semiconductor manufacturing. The ASD-1 test chip features arrays of sub-100 nanometer narrow line structures with alternating materials aligned on the planar silicon substrate for accurately characterizing self-aligned area selective depositions through either Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD) and related processes. The Chipmetrics ASD-1 helps engineers to accelerate ASD process development to meet challenges in miniaturizing and scaling, as well as in reducing defects and improving yield.

Both the PillarHall LHAR5 and ASD-1 test chips are available immediately. For more information on the products, please visit Chipmetrics.com.

About Chipmetrics

Chipmetrics Oy develops and delivers metrology solutions for manufacturing processes for the semiconductor industry, focusing on innovative metrology chips and ALD measurement services. Its main product is the PillarHall® metrology chip for near-instantaneous thin film process conformality measurement. Founded in 2019, its head office is in Joensuu, Finland, with employees and sales partners in Japan, South Korea, USA, and Germany.

For more information, visit www.chipmetrics.com.

Press contact:

Jonas Klar

Chipmetrics Oy

jonas.klar@chipmetrics.com

pr@chipmetrics.com

Editor’s note on ALD:

Atomic Layer Deposition (ALD) is a precision thin-film deposition technique crucial for semiconductor manufacturing, enabling the production of uniform and conformal layers essential for microelectronic devices. Through alternating exposure to precursor gases that react with the substrate in a self-limiting manner, ALD achieves atomic-level control over film thickness and composition. This method ensures exceptional uniformity across complex geometries, vital for the miniaturized, multi-layered structures such as the future’s 3D chips in advanced semiconductor devices, keeping Moore’s Law alive.

Finland plays a key role in the ALD landscape, having pioneered the process in the 1970s. Finland’s contribution to ALD includes significant advancements in materials science, equipment design, and the exploration of new applications ranging from electronics to renewable energy sectors. The country’s strong emphasis on research and development in nanotechnology has positioned it as a hub for ALD innovation, fostering collaborations between academia, industry, and research organizations worldwide.

Characterization of Annealing and Dopant Activation Processes Using Differential Hall Effect Metrology (DHEM) by Active Layer Parametrics (ALP) Inc.

ALP’s Differential Hall Effect Metrology (DHEM) technique is the only technique that directly measures active dopant concentration, mobility, and resistivity depth profiles through semiconductor layers at sub-nm depth resolution (www.alpinc.net).

Above, cross-sectional TEM images of the P ion-implanted samples after annealing and corresponding depth profiles from DHEM.

ALP´s latest work employing this innovative technology and ALPro(TM) electrical profiling tools are summarized in a new invited paper titled “Characterization of Annealing and Dopant Activation Processes Using Differential Hall Effect Metrology (DHEM)”, which will be presented at the 239th ECS Meeting (May 30 to June 3 2021).

They showcase data developed jointly with Imec, Belgium, and Taiwan Semiconductor Research Institute (TSRI, Hsinchu) in the paper. You can read the abstract at (https://ecs.confex.com/ecs/239/meetingapp.cgi/Paper/147952). If you are interested in reading the full paper, please contact Dr. Joshi below for a preprint.

Abhijeet 'AJ' Joshi, PhD

CTO/Co-Founder

Active Layer Parametrics (ALP) Inc.

info@alpinc.net

www.alpinc.net

Sub 7nm Metrology is tough

Why the semiconductor industry needs breakthroughs, and why it’s getting tougher to provide them.

November 21st, 2016 - By: Mark LaPedus

Can We Measure Next-Gen FinFETs? https://t.co/fGCjSJvwNW#Metrology #finFET #semiconductor #5nm #7nm pic.twitter.com/N26ojJal4T

— Ed Sperling (@Chip_Insider) November 21, 2016

Thermo Scientific present Angle resolved XPS Metrology solution for ALD High-k Dielectrics

Many of you in the ALD and High-k business have used or are using XPS to analyze high-k material like HfO2 - pure, mixed or doped with other oxides and elements like SiO2, Al2O3, La2O3, Cl, F, ...

I know for sure that XPS is use as a standard metrology method post high-k deposition in many 300 mm fabs. This is not restricted to mapping just blanket monitor wafers but also to measurement directly on product wafers. In advanced logic and DRAM memory this can be done at different positions in the integration flow depending on the technology (High-k first or last or hybrid, DRAM capacitors) - so it is an established method for high-k in production.

Now the gate stack or advanced stacks for various memory devices (e.g. DRAM, RRAM, FRAM) does not really consist of any bulk material anymore - it has come down to be a extremely advanced stack of ultra thin interfaces. Not even the substrate is bulk any more id you think about HALO doping profiles and FD-SOI technology. That it is why it is interesting to read those application paper from Thermo Scientific – Surface Analysis and Microanalysis on mapping High-k wafers using Angle Resolved XPS of 200 mm wafers. I have included some of the information below for the full paper please download it here from the Thermo Scientific application library : Characterization of high-k dielectric materials on silicon using Angle Resolved XPS

Thickness line scan across the diameter of the 200 mm wafer showing the variation of the thickness of the mixed Al2O3 and HfO2 layer and the thickness of the SiO2 interfacial layer.

XPS maps of Al 2p (upper left) and Hf 4f (lower left) from a 200 mm wafer. XPS maps of O 1s. The lower right map is oxygen in a state with a low binding energy (usually associated with hafnium). The upper right map is oxygen in a state with a high binding energy (usually associated with aluminum and silicon). 

Example of a depth profile through a sample HfO2 on SiO2 on Si. The profile was constructed from ARXPS data.

Thermo Scientific Theta Probe and Theta 300 provide essential information for the next generation of gate dielectrics:

• Layer thickness 

• Thickness of the intermediate layer

• Chemical states of the layer and the intermediate layer • Uniformity of the layers

• Distribution of the material within the layer 

ARXPS is non-destructive and avoids the use of sputtering with an ion beam. Sputtering has been shown to alter the composition of the layer and causes atomic mixing both of which can cause a misinterpretation of the data.