JSR, Lam Research, and SK hynix Push the Boundaries of ASML´s EUV Semiconductor Manufacturing

JSR Corporation, including its subsidiary Inpria Corporation, and Lam Research have entered into a cross-licensing and collaboration agreement to accelerate the development of next-generation semiconductor manufacturing technologies. The partnership combines JSR’s expertise in photoresists and advanced materials—anchored by Inpria’s metal-oxide resists (MORs) for extreme ultraviolet (EUV) lithography—with Lam’s leadership in wafer fabrication equipment and process technology. By sharing intellectual property and integrating complementary capabilities, the companies aim to address scaling and patterning challenges as chipmakers pursue smaller, denser, and more energy-efficient devices for advanced logic and memory applications.

Inpria’s MORs, based on spin-on tin-oxide materials, provide high EUV photon absorption, excellent etch resistance, and reduced line edge roughness compared with conventional organic resists. These materials are fully compatible with existing lithography systems, making them attractive for high-volume production. To meet growing demand, JSR is expanding its global footprint with new R&D facilities in Japan and a production plant in Korea set to begin operations in 2026. Lam Research complements this with its Aether® dry resist technology, which replaces wet spin-coating and development with fully dry, vapor-phase processes. This innovation improves uniformity, reduces stochastic defects, and strengthens EUV absorption, enabling higher resolution and sensitivity. Aether has demonstrated direct-print 28 nm pitch patterning for logic and is already being adopted by leading memory manufacturers, offering both performance advantages and sustainability gains through reduced chemical and energy use.

These advances align with a broader industry shift toward tighter integration of materials and equipment solutions, exemplified by SK hynix’s installation of the world’s first commercial High-NA EUV lithography tool, ASML’s TWINSCAN EXE:5200B, at its M16 fab in Icheon, South Korea. Featuring a numerical aperture of 0.55—compared with 0.33 in current Low-NA EUV systems—the High-NA platform boosts resolution by 40%, enabling transistors about 1.7× smaller and wafer transistor densities nearly 2.9× higher. For SK hynix, this milestone supports the development of next-generation DRAM, reduces process complexity, lowers costs, and strengthens competitiveness in AI memory and advanced compute markets.

As one of the “big three” memory makers alongside Samsung and Micron, SK hynix has established itself as the leader in high-volume DRAM manufacturing. It was the first to mass-produce DDR5 and high-bandwidth memory (HBM3), both essential for AI and high-performance computing. Its early adoption of EUV lithography for DRAM production—and now the industry-first deployment of ASML’s High-NA EUV system—underscores its position at the forefront of DRAM scaling and density. Together, the innovations from JSR, Inpria, Lam Research, and SK hynix illustrate how collaboration across the semiconductor ecosystem is driving the breakthroughs required to sustain Moore’s Law in the era of AI and advanced computing.

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Do you want me to keep the headline-style opening as above, or make it read more like a press release introduction with a formal lead sentence?

Sources:

JSR Corporation/Inpria Corporation and Lam Research Enter Cross Licensing and Collaboration Agreement to Advance Semiconductor Manufacturing

Dry Resist Patterning Progress and Readiness Towards High NA EUV Lithography

INPRIA | A world leader world leader in metal oxide photoresist design, development and manufacturing

Inpria Co-Developing Metal Oxide Resist with SK hynix to Reduce Complexity of Patterning for Next-Generation DRAM | 2022 | News | JSR Corporation

SK hynix Introduces Industry’s First Commercial High NA EUV

Breaking the Copper Bottleneck: Lam Research’s Mo-ALD ALTUS Halo Enables Next-Generation Hybrid Metallization

Lam Research now offers molybdenum (Mo) atomic layer deposition (ALD) with its ALTUS Halo platform, introduced in 2025 as the first high-volume ALD tool designed for Mo metallization. The system enables conformal and selective, bottom-up deposition of low-resistivity, void-free Mo films, targeting advanced logic, memory, and 3D NAND applications where conventional copper and tungsten interconnects face scaling and reliability limits. This positions Lam’s Mo-ALD as a key enabler for next-generation BEOL hybrid metallization schemes.

Current density of various metal/via schemes. Red and green areas indicate higher current density.  

Hybrid metallization using Mo shows strong potential to overcome the scaling limitations of conventional copper dual damascene (Cu DD) processes in advanced semiconductor BEOL interconnects. As device dimensions shrink, Cu faces challenges such as increased resistivity, barrier thickness limitations, and stress-induced voids (SIVs), all of which degrade performance. Mo hybrid metallization, which uses bottom-up barrierless metal deposition before a conventional Cu process, significantly reduces resistance—by about 55% compared to Cu DD—and further by 15% with selective barrier deposition (SBD). This lower resistance translates into higher current densities and improved reliability. Stress distribution studies also reveal that Mo hybrid vias exhibit lower void formation risks than Cu due to smaller stress gradients at the via/barrier interfaces.

Comparison of via and line resistance for conventional Cu dual damascene and Mo hybrid metallization schemes. Mo vias reduce total resistance by ~35% without selective barrier deposition (SBD), with an additional ~20% reduction when fully replacing Cu. Applying SBD further lowers resistance, achieving up to ~55% reduction compared to the Cu baseline.

Optimization studies, performed with SEMulator3D® simulations, identified key parameters like via critical dimensions, height, and material stress properties that impact resistance, capacitance, and hydrostatic stress. Findings show that increasing Mo via height lowers resistance but raises stress, suggesting an optimal fill height around 25 nm for balancing performance and reliability. Intrinsic stress of Mo and process temperature tuning were also shown to mitigate stress-induced reliability issues, with 400°C identified as a favorable condition. Ultimately, hybrid metallization with Mo offers a scalable path forward, combining electrical and mechanical benefits, while virtual DOE and process modeling enable predictive optimization without extensive wafer-based experiments.

Sources:

Breaking the Copper Bottleneck With Molybdenum Hybrid Metallization

Lam Research Ushers in New Era of Semiconductor Metallization with ALTUS® Halo for Molybdenum Atomic Layer Deposition - Feb 19, 2025

ALD News Week 38

Solid-state batteries get a boost with new protective coating

Link: https://www.anl.gov/article/solidstate-batteries-get-a-boost-with-new-protective-coating

“A thin, glass-like layer could help protect solid-state batteries from degradation, researchers say. They use a process called atomic layer deposition (ALD) to apply a protective layer.” (ANL)

Microwave enhanced atomic layer deposition (MW-ALD): Incorporating a microwave antenna into an ALD reactor
Link: https://pubs.aip.org/avs/jva/article/43/5/052403/3361679/Microwave-enhanced-atomic-layer-deposition-MW-ALD

“Atomic layer deposition (ALD) is a technique widely used for thin film deposition with excellent uniformity and conformality. In this work, we present a modification of a conventional ALD system by integrating a microwave antenna to explore how microwave energy can enhance film growth and reduce cycle times, particularly for materials that are otherwise difficult to deposit.” (AIP Publishing)

Impacts of different thickness Al2O3 and SiO2 atomic layer deposition sidewall passivation layers on GaN-based devices
Link: https://pubs.aip.org/avs/jvb/article/43/5/052209/3361926/Impacts-of-different-thickness-Al2O3-and-SiO2-atomic-layer-deposition-sidewall
 
“The sidewall passivation layer has a critical effect on the performance and reliability of GaN-based devices. In this study, we investigate how varying the thickness of atomic layer deposition (ALD) Al₂O₃ and SiO₂ sidewall passivation layers influences device leakage, breakdown voltage, and surface recombination. The results show that thicker layers can better suppress leakage but may lead to trade-offs in other device parameters.” (AIP Publishing)

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Forge Nano to Unveil Commercial Single Module Semiconductor Wafer Fab ALD Tool at SEMICON Taiwan
Link: https://www.globenewswire.com/news-release/2025/09/04/3144564/0/en/Forge-Nano-to-Unveil-Commercial-Single-Module-Semiconductor-Wafer-Fab-ALD-Tool-at-SEMICON-Taiwan.html

DENVER, Sept. 04, 2025 (GLOBE NEWSWIRE) -- Forge Nano, Inc., a technology company pioneering domestic battery and semiconductor innovations, today announced it is unveiling a new commercial single module semiconductor wafer fab atomic layer deposition (ALD) tool – TEPHRA^{One}. The fully automated 200 mm single module platform is outfitted with features from Forge Nano’s flagship multi-process module TEPHRA in a streamlined configuration for oxide, nitride, metal and nanolaminate coatings. (GlobeNewswire)

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New Tool Announcement: Thermal/Plasma ALD System Now Available for User Access
Link: https://nanofab.ucsd.edu/new-tool-announcement_thermal-plasma-ald-system/

We are happy to announce that the new Arradiance GEMStar Thermal & Plasma ALD (Atomic Layer Deposition) System is now available for user access. This advanced system supports both thermal and plasma enhanced ALD processes and is designed to allow users to explore a wide range of thin film materials and process conditions. (nanofab.ucsd.edu)

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Press Release “ALD for Industry 2025” - Dresden
Link: https://efds.org/en/45604/

Dresden, March 12, 2025 – The 8th International Conference “ALD FOR INDUSTRY” has once again bridged the gap between basic research, industrialization and commercialization of atomic layer deposition (ALD). This event, which has been held annually in Dresden since 2017, once again welcomed over 100 participants from 14 countries and numerous exhibitors this year despite the strike at German airports. (efds.org)

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News & Announcements: Continuous, high-speed atomic layer deposition for thin-film coatings
Link: https://www.anl.gov/amd/news-announcements

“Self-exhausting” precursor pulses enable fast, precise coating applications for … (ANL)

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Global Semiconductor Sales Surge 20.6% in July, Driven by Americas and Asia Pacific

Global semiconductor sales surged in July 2025, reaching $62.1 billion — a 20.6% increase from the same month last year and 3.6% higher than June. The robust expansion was fueled by strong demand in the Americas and Asia Pacific, underscoring the industry’s momentum despite regional fluctuations. With the Americas up nearly 30% and Asia Pacific/All Other climbing over 35% year-on-year, July marked one of the strongest months of growth in recent years, highlighting continued strength in advanced computing, AI, and data-driven technologies.

• The Americas and Asia Pacific regions are the strongest contributors to both monthly and yearly growth.
• China is still growing year-to-year but slipped month-to-month, suggesting softer short-term demand.
• Japan is contracting in both comparisons, signaling structural weakness.
• Europe remains modest but positive year-to-year.

Global Overview

• Total sales: $62.07B
• Year-to-year growth: +20.6% (vs. $51.48B in July 2024)
• Month-to-month growth: +3.6% (vs. $59.91B in June 2025)
• Three-month-moving average growth: +8.9%

Regional Breakdown (Year-to-Year, July 2025 vs. July 2024)

• Asia Pacific/All Other: +35.6% (biggest growth driver)
• Americas: +29.3%
• China: +10.4%
• Europe: +5.7%
• Japan: -6.3% (only region in decline)

Month-to-Month (July vs. June 2025)

• Americas: +8.6%
• Asia Pacific/All Other: +4.9%
• Europe: 0.0%
• Japan: -0.2%
• China: -1.3%

Source:

Global Semiconductor Sales Increase 20.6% Year-to-Year in July - Semiconductor Industry Association

EU Expands Dual-Use Export Controls to Cover Atomic Layer Deposition, Etch, Epitaxy, Lithography, EUV Components and Quantum Technologies

On 8 September 2025, the European Commission adopted a Delegated Regulation updating the EU’s dual-use export control list (Annex I of Regulation (EU) 2021/821). The update aligns EU rules with commitments made in 2024 under the Wassenaar Arrangement, MTCR, Australia Group, and the Nuclear Suppliers Group, ensuring a uniform application of newly agreed controls across all Member States. The move reflects the EU’s broader strategy outlined in the 2024 White Paper on Export Controls, strengthening oversight of sensitive technologies while maintaining competitiveness and a level playing field for European industry.

The updated list introduces new controls on a range of emerging technologies. These include quantum technologies such as cryogenic components and amplifiers, advanced semiconductor manufacturing and testing equipment — notably Atomic Layer Deposition tools, epitaxial deposition systems, and EUV lithography materials — as well as high-performance computing circuits, additive manufacturing systems, peptide synthesisers, and specialized high-temperature coatings. The Delegated Regulation will enter into force following the standard two-month scrutiny period by the European Parliament and Council, reinforcing the EU’s role in safeguarding security and international stability through effective export controls.

Specifically, this update of the EU control list provides for the addition of new dual-use items, including: 

• Controls related to quantum technology (e.g. quantum computers, electronic components designed to work at cryogenic temperatures, parametric signal amplifiers, cryogenic cooling systems, cryogenic wafer probers);
• Semiconductor manufacturing and testing equipment and materials (e.g. Atomic Layer Deposition equipment, equipment and materials for epitaxial deposition, lithography equipment, Extreme Ultra-Violet pellicles, masks and reticles, Scanning Electron Microscope equipment, etching equipment);
• Advanced computing integrated circuits and electronic assemblies such as Field Programmable Logic Devices and Systems;
• Coatings for high temperature applications;
• Additive manufacturing machines and related materials (e.g. inoculants for powders);
• Peptide synthesisers, and;
• Modification of certain control parameters and update of certain technical definitions and descriptions.

By extending controls to core process equipment essential for leading-edge semiconductor production, the EU aims to close regulatory gaps and ensure uniform oversight across all Member States. For the semiconductor industry, this means that exports of critical manufacturing tools and materials outside the Union will now require authorisation, tightening compliance requirements but also ensuring fair competition and transparency within the internal market. The regulation highlights the EU’s growing focus on safeguarding supply chains for advanced chip technologies while balancing competitiveness with security concerns

For more information
Delegated Regulation
Comprehensive Change Note Summary – Update 2025: An overview of changes to the EU Dual-Use Control List across the 10 categories of Annex I

TSMC’s 2 nm Fabs Lock Out China OEMs, Securing ALD and Process Tool Demand for US, European, and Japanese Tier-1 Suppliers

TSMC’s decision to exclude Chinese equipment vendors from its 2 nm fabs in Taiwan and the US reshapes the competitive landscape in favor of Japanese, American, and European suppliers. With the 2 nm node set to become the largest in history by wafer volume and revenue potential, this policy shift effectively concentrates demand among a handful of Tier 1 players —ASMI, TEL, Applied Materials, and Lam Research—who already dominate in deposition, etch, and cleaning tools essential for nanosheet GAA and backside power delivery. No need to mention ASML.

Announced in January: TSMC is advancing with its 2 nm (N2) technology, establishing a pilot line at its Hsinchu Baoshan Fab 20 with an initial monthly output of around 3,000–3,500 wafers. By combining production from Hsinchu and Kaohsiung, the company expects to exceed 50,000 wafers per month by the end of 2025 and reach about 125,000 wafers per month by the end of 2026. Output at Hsinchu should rise to 20,000–25,000 wafers per month by late 2025 and 60,000–65,000 by early 2027, while Kaohsiung is projected to produce 25,000–30,000 wafers monthly by late 2025 and also expand to 60,000–65,000 by early 2027. Chairman C.C. Wei has highlighted that demand for 2 nm exceeds that of 3 nm, driven by its 24–35% lower power consumption, 15% performance boost at the same power, and 15% higher transistor density. Apple will be the first adopter, followed by MediaTek, Qualcomm, Intel, NVIDIA, AMD and Broadcom.

TSMC will start 2 nm mass production in Taiwan in the second half of 2025, initially with Fab 22 in Kaohsiung as the anchor site for yield learning. The first ramp is set at 40,000 wafers per month, expanding to 100,000 wafers per month in 2026 and reaching 200,000 wafers per month by 2027, making N2 the largest and most profitable node in TSMC’s history.

In the US, Arizona Fab 21 is being developed in phases. Phase 1 is already producing 4 nm chips, Phase 2 will start 3 nm by late 2025 or early 2026, and Phase 3 is planned for 2 nm and A16-class chips toward the end of the decade. This ensures that while Taiwan remains the cost-optimized base for N2 production, Arizona provides premium, subsidy-supported capacity for US customers, diversifying geographic and geopolitical risk.

Overall, Taiwan will carry the bulk of N2 output and cost efficiency, while Arizona secures local supply for strategic US clients like Apple, Nvidia, AMD, and Intel. By 2027, with 200,000 wafers per month globally, N2 alone could generate nearly $50 billion annually, cementing TSMC’s central role in powering AI and HPC expansion.

The move aligns directly with Washington’s Chip EQUIP Act, which ties subsidies to avoiding “foreign entities of concern.” By pre-emptively removing Chinese tools, TSMC safeguards its access to US incentives while giving its global customers—Apple, Nvidia, AMD, and Intel—assurance that supply chains are insulated from geopolitical risk. This codifies the leading suppliers as the “trusted” baseline for advanced-node capacity worldwide, effectively reinforcing their moat at the most profitable process node ever.

For ASMI, TEL, AMAT, and Lam, the outlook is very positive. With Chinese competitors pushed out, these companies can win more business and have stronger pricing power. At the same time, 2 nm wafer prices are climbing toward $30,000, far above older smartphone-focused nodes. TSMC is reviewing its suppliers for profit margins and China ties, but these four are essential for 2 nm production, so they are more likely to gain from rising demand and higher-value tools than lose ground. Put simply, the 2 nm era is set to drive lasting growth and profits for them as AI adoption accelerates through 2027.

Chinese semiconductor equipment OEMs that are cut out from TSMC’s 2 nm fabs under the new restrictions and supplier realignment:

• AMEC (Advanced Micro-Fabrication Equipment Inc.) – leading Chinese etch tool supplier, with relevance in dielectric etch and epitaxy
• Naura Technology Group – broad portfolio in etch, deposition, and cleaning tools
• Mattson Technology (China-owned, via E-Town Dragon Semiconductor) – focuses on dry strip, rapid thermal processing (RTP), and etch
• SMEE (Shanghai Micro Electronics Equipment) – China’s only domestic lithography tool maker (far behind in capability, but relevant in domestic fabs)
• Kingsemi – maker of ALD/CVD equipment, mainly for memory and advanced logic
• Piotech – deposition (CVD, PECVD, ALD) equipment vendor
• ACM Research (China) – cleaning and electrochemical deposition tools (though headquartered in the US, its operations are China-based and increasingly seen as China OEM)

At TSMC’s 2 nm fabs, the exclusion of Chinese equipment vendors channels ALD equipment demand entirely to US, European, and Japanese suppliers. ASM International (Europe) remains the clear leader in single-wafer ALD for high-k metal gate stacks and nanosheet spacers, with Applied Materials and Lam Research (US) competing in selective and plasma ALD for gate-all-around and backside power steps, while Tokyo Electron and Kokusai Electric (Japan) cover both single-wafer and batch ALD, particularly for spacer and liner deposition. By contrast, Chinese ALD players such as Naura, Kingsemi, and Piotech, while active in domestic logic and memory at 28–14 nm and some 7 nm non-EUV capacity, will not gain any capability at N2 and are explicitly excluded under TSMC’s supplier policy and US subsidy rules, leaving the largest and most profitable ALD opportunity in history to be divided among the established US, European, and Japanese Tier-1 suppliers.

Sources:

TSMC reportedly cuts Chinese chipmaking tools from 2nm fabs as suppliers face scrutiny due to emerging new US restrictions | Tom's Hardware

https://open.substack.com/pub/drrobertcastellano/p/tsmcs-2-nm-era-technology-leadership?r=l0uj0&utm_campaign=post&utm_medium=web&showWelcomeOnShare=false

TSMC Is Getting Ready to Launch Its First 2nm Production Line | TechPowerUp

Chipmetrics expands metrology portfolio with advanced test chips and wafer solutions for next-gen ALD semiconductor processes

Finnish metrology specialist Chipmetrics has expanded its portfolio with a new range of advanced test chips and wafer solutions aimed at accelerating prototyping and enhancing precision in next-generation semiconductor process development. The new releases include the ASD-1b area-selective deposition chip, a High Surface Area wafer, and pre-coated High Aspect Ratio test structures such as PillarHall and VHAR1. These tools are designed to simulate real-world manufacturing conditions with greater accuracy, helping engineers optimise processes more efficiently and reduce development cycles in ALD and other thin-film applications.

The ASD-1b chip provides a tricolour material layout with metal, SiO₂ and Si₃N₄ surfaces, enabling detailed assessment of selectivity and defectivity across multiple deposition techniques. Meanwhile, the new HSA wafer delivers up to 300 times greater surface area sensitivity through deep trench designs, supporting ultra-sensitive material studies. By offering pre-coated HAR structures, Chipmetrics addresses the growing industry demand for realistic conformality and uniformity testing. According to CEO Mikko Utriainen, these solutions are set to streamline benchmarking of new chemistries and processes, giving development teams faster, clearer feedback to advance semiconductor innovation.

Chipmetrics’ new metrology tools for advanced thin film process development. Left: Pre-coated high aspect ratio test structures, including PillarHall® (lateral AR > 1000) and VHAR1 (vertical AR = 200), for evaluating conformality and film penetration. Centre: The ASD-1b area selective deposition test chip with tricolour material layout for testing selectivity across Cu, SiO₂ and Si₃N₄ surfaces. Right: High Surface Area (HSA) wafer combining a 150 mm VHAR1 wafer within a 300 mm pocket wafer, providing up to 300× enhanced surface area for sensitive material studies.

Source:

Chipmetrics Expands Product Line with Advanced ALD Test Chips and Wafer Solutions - Chipmetrics

Shaping the Future of Thin Films: New Trends in Thermal ALD Chemistry

A new review published in the Journal of Vacuum Science & Technology A takes a detailed look at recent developments in thermal atomic layer deposition (ALD) chemistry, drawing on data from the comprehensive ALD database at atomiclimits.com. The analysis highlights how process innovations have accelerated since 2010, with more than half of all reported ALD processes emerging in the past 15 years. Binary oxides remain the dominant material group, but there has been a steady increase in the deposition of non-oxides and ternary compounds. More recently, classes such as elemental metals, two-dimensional transition metal dichalcogenides, and halides have gained prominence, driven largely by application demands in microelectronics, energy technologies, and catalysis. The study also notes the introduction of new elements into the ALD portfolio after 2010, including alkali metals and more exotic elements such as rhenium, osmium, gold, and antimony, each requiring unique process routes.

The review underscores the critical role of precursor chemistry in enabling these advances. While traditional precursors such as halides, alkoxides, and β-diketonates laid the foundation, newer processes have leaned heavily on amides and imides, followed by cyclopentadienyl compounds. However, the most significant trend is the growing reliance on heteroleptic precursors, which combine multiple ligand types to fine-tune key properties such as volatility, reactivity, and thermal stability. This flexibility has been instrumental in broadening the range of materials accessible via ALD and tailoring processes to meet the specific requirements of cutting-edge applications. Overall, the work reflects how ALD chemistry has evolved from relatively narrow beginnings into a dynamic and application-driven field with expanding industrial significance.

Source:

The review is based on ALD chemistries collected from the AtomicLimits ALD precursor database: Database of ALD processes

Popov, G.; Mattinen, M.; Vihervaara, A.; Leskelä, M. (2025). “Recent trends in thermal atomic layer deposition chemistry.” Journal of Vacuum Science & Technology A, 43, 030801. https://doi.org/10.1116/6.0004320

Beneq Secures Repeat Orders as ALD Gains Ground in MicroLED Display Market

Espoo, Finland, 14 July 2025 – Beneq, a global leader in Atomic Layer Deposition (ALD) technology, has announced significant momentum in the microLED display sector, marked by repeat orders from leading tech innovators. The development highlights the growing demand for advanced manufacturing tools capable of supporting the next generation of display technologies.

MicroLED is increasingly seen as a transformative display technology across consumer electronics, augmented and virtual reality (AR/VR), and the automotive sector. Offering superior brightness, contrast, energy efficiency and durability, microLED enables ultra-fine resolution, longer device lifetimes and seamless scalability.

According to Yole Group, global microLED display shipments are expected to grow at a compound annual rate of 180.6 percent from 2022, reaching 42.4 million units by 2029. However, manufacturing challenges remain, particularly as pixel sizes shrink below 10 micrometres. ALD plays a critical role in overcoming these hurdles by delivering ultra-thin, conformal coatings that ensure uniformity, stability and surface passivation—key for improving efficiency and reliability.

Beneq Transform® is an ALD cluster tool designed for technology development and manufacturing across power electronics (SiC, GaN, Si), RF, optoelectronics, microLED, MEMS, and sensors.

“Our top-tier customers rely on ALD technology to advance monolithic integration of microLEDs and driver electronics on a single chip,” said Mikko Söderlund, Head of Semiconductor ALD Sales at Beneq. “This enables a new class of compact, high-performance display products with faster data transfer and reduced power consumption.”

Beneq’s Transform® ALD cluster platform is central to its offering, providing high-throughput production capability with a modular, multi-chamber design. The platform supports a range of materials and processes, allowing customers to optimise optical and electrical properties while scaling from lab to fab.

These developments reinforce Beneq’s commitment to supporting microLED pioneers through both early-stage development and the transition to volume manufacturing, accelerating the path toward widespread adoption of advanced display technologies.

Sources: 

Beneq Advances MicroLED Leadership with Growing Demand from Industry Frontrunners | Beneq

Transform® and Transform® Lite

Atomic Scale Processing: A Key Enabler for Scalable and Coherent Quantum Technologies

Recent advances in quantum computing, including IBM’s 1000-qubit chip and imec’s 300 mm wafer transmon qubits, highlight a rapid progression towards scalable, fault-tolerant quantum systems. As quantum platforms such as superconducting and spin-based qubits evolve, the reproducibility and precision of fabrication processes have become essential. Atomic Layer Deposition (ALD) and Atomic Layer Etching (ALE) are emerging as critical tools to meet these demands. ALD’s conformal coating capabilities are particularly well-suited for developing 3D structures like through-silicon vias (TSVs), which are essential for high-density, low-loss interconnects in large-scale qubit arrays. However, transitioning ALD to 3D geometries requires careful adjustment of plasma conditions to maintain superconducting properties on vertical sidewalls. Despite these challenges, early successes with materials like TiN and NbN suggest strong potential for ALD in quantum manufacturing.

At the same time, improving surface and interface quality remains central to boosting qubit coherence times. Qubits are highly sensitive to material defects and interfacial contamination, which are known sources of decoherence. ALE’s self-limiting, smooth etching capabilities offer a superior alternative to conventional dry and wet etching by reducing surface roughness and enabling high selectivity. This process can mitigate damage and defects at key interfaces such as metal-air and substrate-air, which are critical loss points in superconducting qubits. The ability of ALE to tailor etch behaviour with high precision makes it a promising method for refining material interfaces and improving device performance. As these atomic-scale techniques continue to mature, they are poised to play a foundational role in the future scalability and reliability of quantum computing platforms.

Sources:

How atomic scale processing can help to pave the way for future quantum devices: A Workshop to bridge ALD/ALE and Quantum communities – Atomic Limits

SiCarrier Seeks $2.8 Billion to Advance Chipmaking Equipment

SiCarrier, a Chinese chip equipment manufacturer closely associated with Huawei and owned by the Shenzhen city government, is seeking $2.8 billion in funding to advance its ambitions of becoming China's leading chipmaking equipment provider. Founded in 2021, the company aims to surpass domestic rivals such as Naura and AMEC, amid U.S. export restrictions that have fueled China's drive for semiconductor self-sufficiency. The fundraising, targeting a valuation of $11 billion, is expected to conclude soon, with proceeds allocated primarily to R&D. State-owned firms and domestic investors have shown strong interest. Despite showcasing 30 products at Semicon China 2025, most of its tools remain under development and are not yet production-ready. SiCarrier has filed 92 patents, indicating plans to offer a comprehensive suite of chipmaking tools, including lithography and AI-driven inspection systems. However, its deep ties to Huawei have raised concerns among potential customers over data security and trade secret protection. Industry experts suggest full operational independence from Huawei is essential for broader market acceptance and long-term growth.

"Founded in 2021 and owned by the Shenzhen city government, SiCarrier is largely seen as a Huawei supplier. But it wants to become the leading domestic provider of chipmaking equipment in China, surpassing Naura and Advanced Micro-Fabrication Equipment China (AMEC), according to four people with knowledge of its goals."

A Reuters review of 92 patents filed by Shenzhen SiCarrier Industry Machines and its parent Shenzhen SiCarrier Technologies between October 2022 and March 2025 reveals the company’s ambitious plan to establish itself as a comprehensive supplier of semiconductor manufacturing equipment. Unlike domestic peers such as Naura and AMEC, which have taken more focused approaches, SiCarrier is pursuing an expansive product roadmap that spans the entire chip production chain—from wafer metrology and defect inspection to etching and atomic layer deposition (ALD) systems. These filings, verified through Anaqua’s AcclaimIP database, illustrate SiCarrier’s intention to compete head-on with established global players such as KLA, Lam Research, and Tokyo Electron, particularly in process-critical segments like thin-film deposition and etch uniformity control. Notably, SiCarrier is investing in AI-powered wafer defect recognition, a frontier area aimed at enhancing production yields, especially important in advanced nodes where precision is paramount. Industry observers cited by Reuters suggest metrology and inspection tools offer SiCarrier the most immediate opportunity, given the absence of a dominant Chinese competitor in that space. The patent portfolio also reveals efforts to close the technological gap in lithography by focusing on components for deep ultraviolet (DUV) systems and multi-patterning techniques. These are presented as domestic alternatives to extreme ultraviolet (EUV) lithography, which remains out of reach due to US export controls. However, experts like Dan Hutcheson of TechInsights caution that the multi-patterning approach—though pioneered by Intel and used by TSMC at 7 nm—carries known drawbacks such as increased complexity and yield challenges, stemming from its reliance on sequential deposition and several etch processes. 

Sources:

Exclusive: SiCarrier - Huawei partner in chips - seeks $2.8 billion in funds, sources say | Reuters

AlixLabs Secures Notice of Allowance for US Patent for Innovative Semiconductor Manufacturing Technology

Swedish semiconductor startup’s APS™ patent portfolio continues to grow with xth U.S. patent, marking the company’s 10th pending global patent.

Stockholm, Sweden – May 6th, 2025 – AlixLabs is excited to announce that the US Patent and Trademark Office has issued the notice of allowance for the company’s latest patent application, US20250087487A1, titled Formation of an array of nanostructures. This milestone marks the next step in AlixLabs’ commitment to advancing semiconductor manufacturing technologies.

Internally referred to as the “Tetris” patent, in honor of Alexey Pajitnov, the new patent integrates self-aligned double patterning (SADP) with atomic layer etching (ALE)-based pitch splitting (APS™) technology. This innovative approach, being industrialized by AlixLabs since its founding in 2019, combines elements of both classical and leading-edge techniques to deliver superior performance for semiconductor manufacturing.

The invention arose from AlixLabs’ efforts to develop a process for precise sidewall angle control in APS™, a key component in silicon-based processes. By leveraging plasma etch process selectivity and combining features from complex plasma processes, AlixLabs has pioneered a method that blends the traditional SADP process with the advanced APS technology.

This allows the company to utilize mature industrial technologies while benefiting from the advanced control and improved performance of cyclic processes and topographical selectivity. As a result, AlixLabs’ solution offers semiconductor manufacturers an enhanced ability to address the challenges of patterning at sub-5 nm nodes.

This breakthrough is significant for the integration of APS™ technology into existing semiconductor production workflows, preserving the use of existing Process Design Kits (PDKs) which are essential tools for chip designers. By doing so, it reduces the barrier for APS adoption in high-volume manufacturing (HVM), easing the transition to next-generation semiconductor technologies.

The patented innovation provides semiconductor manufacturers with greater flexibility, offering a new way to fine-tune the APS™ process to meet the needs to cut capital and operational expenditure (CapEx and OpEx) as well as emissions for customers at advanced technology nodes, while allowing for broader compatibility with different materials. This new method further strengthens AlixLabs’ core APS™ patent portfolio, positioning the company as a leading enabler of next-generation semiconductor manufacturing.

Moreover, this invention not only supports the development of leading-edge logic, memory, and photonics but also simplifies the semiconductor manufacturing process by reducing CapEx and OpEx for semiconductor fabs.

“We remain committed to advancing semiconductor manufacturing with innovations that significantly enhance the precision, flexibility, and efficiency of our technologies,” commented Dmitry Suyatin, co-founder and CTO of AlixLabs. “This patent represents a critical step forward in our mission to drive the next generation of semiconductor processes and further solidify our position as a leader in the field.”

AlixLabs Secures Notice of Allowance for US Patent for Innovative Semiconductor Manufacturing Technology – AlixLabs

Tokyo Electron Delivers Record FY2025 Results Amid AI Boom, Eyes Growth Through CVD Innovation and Geopolitical Resilience

Tokyo Electron (TEL) achieved a record-breaking financial year in FY2025, with strong top- and bottom-line growth driven by robust global demand for advanced semiconductor equipment. Net sales rose by 32.8% year-on-year to approximately ¥2.43 trillion (around $15.7 billion USD), marking the highest in the company's history. Operating profit surged to ¥697.3 billion (about $4.5 billion USD), supported by an improved operating margin of 28.7%. Growth was underpinned by increased investment in leading-edge logic and memory, particularly High Bandwidth Memory (HBM) and advanced DRAM nodes, where TEL maintained or expanded market share through key Process of Record (POR) wins in etch and wafer bonding technologies. Revenue contributions diversified geographically, with notable gains in South Korea and Taiwan, even as China remained a key market. TEL also demonstrated strong cash flow, increased its R&D and capital investments, and returned significant value to shareholders through dividends and buybacks. Looking ahead, TEL forecasts continued growth in FY2026, positioning itself to capitalise on accelerating AI, 2nm logic, and heterogeneous integration trends.

Tokyo Electron TEL has demonstrated strong financial performance and strategic market expansion through FY2025, according to their investor presentation dated April 30, 2025. Their net sales, gross profit, operating profit, and net income have all reached record highs, signaling both operational efficiency and favorable market conditions.

LINK: Tokyo Electron Limited 2025 Q4 - Results - Earnings Call Presentation (OTCMKTS:TOELY) | Seeking Alpha

Tokyo Electron's Q4 FY2025 earnings call highlighted strong financial performance and an optimistic forward outlook amid geopolitical uncertainties. Despite global concerns around US tariffs and export controls—particularly in China, which saw its WFE market share fall to 35%—TEL stated that it has not observed any significant changes in customer investment sentiment or competitive dynamics. The company reaffirmed its strategy of focusing on long-term innovation rather than short-term regulatory shifts, underscoring its commitment to developing higher-productivity tools to offset potential external headwinds. Looking ahead, TEL forecasts continued double-digit WFE market growth into calendar 2026, driven by AI infrastructure demand, 2nm logic, and HBM scaling. The company plans record-high investments of ¥300 billion in R&D and ¥240 billion in CapEx for FY2026, reflecting confidence in sustained momentum across DRAM, advanced logic, and packaging technologies. TEL aims to expand global market share and reach ambitious mid-term goals, including over ¥1 trillion in operating profit and 35%+ OPM, by capitalising on technology transitions such as GAA, backside PDN, and heterogeneous integration.

LINK: Tokyo Electron Limited (TOELY) Q4 2025 Earnings Call Transcript | Seeking Alpha

Revenue and Profitability Growth:

Net sales increased significantly from ¥1,399.1 billion in FY2021 to ¥2,431.5 billion in FY2025, a 74% increase over four years. The gross profit also rose steadily, reaching ¥1,146.2 billion in FY2025, up from ¥564.9 billion in FY2021. Operating profit followed suit, more than doubling from ¥320.6 billion to ¥697.3 billion. These trends underscore TEL’s ability to scale profitably, with operating margins rising from 22.9% in FY2021 to 28.7% in FY2025. Return on equity (ROE) also remained strong, peaking at 37.2% in FY2022 and settling at 30.3% in FY2025, a testament to effective capital management.

Regional Sales Composition:

The revenue breakdown by region from Q1 FY2024 to Q4 FY2025 shows growing diversification. Notably, China has remained the single largest market, although its share declined from 47.4% in Q4 FY2024 to 34.3% in Q4 FY2025, reflecting a strategic balancing across geographies. South Korea, Taiwan, and North America significantly increased their contributions, with South Korea reaching ¥147.0 billion and Taiwan ¥135.8 billion in Q4 FY2025. This reflects growing demand from advanced logic and memory fabrication customers in these regions.

In FY2025, Tokyo Electron’s semiconductor production equipment (SPE) sales reached ¥1.86 trillion, driven by a sharp rise in DRAM-related investments, particularly for high-bandwidth memory (HBM), which accounted for 31% of total sales. Non-volatile memory (NAND) remained stable at 7%, while non-memory segments, including logic and foundry, continued to dominate with 62%, reflecting robust demand from both advanced and mature nodes. The overall recovery and expansion of customer investments across segments underpinned this strong performance.

Market Segment Performance

Tokyo Electron’s global market share in CY2024 demonstrates its leadership across multiple core segments of the semiconductor production equipment market. The company holds a commanding 92% share in coater/developer systems, underlining its unparalleled position in photoresist processing for advanced lithography applications. It also leads the wafer prober segment with a 38% share and maintains robust positions in key deposition categories, including 38% in CVD and 37% in oxidation/diffusion systems. In contrast, TEL’s market share in ALD stands at 16%, notably behind ASM International, highlighting an opportunity for expansion in this strategically important technology as the industry moves towards GAA and other 3D device structures. Performance in dry etch (27%), cleaning systems (21%), and wafer bonding (32%) rounds out a broadly competitive portfolio that positions TEL to effectively support ongoing advancements in scaling, heterogeneous integration, and high-performance packaging across logic, memory, and AI-related applications.

To further expand our future profit, we made steady progress in penetrating into new technology domains. Specifically, we released multiple new outstanding products contributing to the semiconductor technology innovation. For example, penetration to untapped segments such as single-wafer plasma CVD and PVD, gas cluster beam system which improves efficiency of leading-edge lithography, and laser-lift-off system to drastically decrease environmental footprint of processing. In fiscal 2025, we conducted share repurchase of about ¥150 billion in total.

- Toshiki Kawai - Representative Director, President and CEO

 

New product 2025 Episode™ single-wafer CVD platform

Episode™ 1 is Tokyo Electron's latest single-wafer CVD platform, launched in 2024 to address the challenges of advanced device scaling in logic, DRAM, and future AI processors. It supports up to eight process modules, enabling complex, uninterrupted multi-step processing. The system integrates the OPTCURE™ module for native oxide removal and ORTAS™ for titanium CVD, allowing immediate Ti deposition to minimise contact resistance in advanced interconnects. Episode™ 1 replaces traditional PVD with CVD to achieve uniform, low-resistivity films in high aspect ratio structures such as deep contact holes. With a 45% smaller footprint than its predecessor and advanced edge computing, data analytics, and environmental tracking capabilities, the system enhances fab productivity, engineer efficiency, and readiness for new materials in next-generation device manufacturing.

The TEL Episode™ 1 system shown in the image seems to feature twin or dual single-wafer process chambers, which is typical in modular CVD tools designed for high throughput. Each visible module (with two load ports per unit) likely contains two process chambers within the same footprint to maximise wafer handling efficiency and enable parallel processing—common in tools aimed at advanced logic and memory manufacturing.

Episode™ 1 offers a reduced footprint. Compared with the Triase+™ series, twice as many smaller modules can be installed in a system. With the same number of modules installed, Episode™ 1 takes up about 45% less fab space than its predecessor

LINK: Episode™ 1 Single-Wafer Deposition System for Semiconductors: Driving the Evolution of AI Semiconductors to Transform Everyday Life | Blog | Tokyo Electron Ltd.

ASM International Strengthens ALD Market Leadership Amid Strong Q1 Results, Growing GAA Adoption, and Strategic Positioning for Advanced Node Demand

ASM International’s Q1 2025 results reaffirm its leadership in Atomic Layer Deposition (ALD), a technology central to enabling advanced semiconductor nodes such as 2nm and beyond. With ALD accounting for more than half of its equipment revenue and strong customer engagement in leading-edge logic and memory, ASM is well-positioned to capitalise on rising demand driven by GAA architectures, high-bandwidth memory, and ongoing technology node transitions.

ASM International’s Q1 2025 results reinforce its leadership in ALD, a foundational technology for enabling advanced semiconductor nodes. ALD represented more than half of ASM’s equipment revenue, with the market expected to grow at a compound annual rate of 10–14% through 2027, and ASM maintaining a leading market share above 55% in the segments they compete in:

Single-Wafer ALD Tools

ASM’s flagship ALD platforms are single-wafer systems, which provide high precision, conformality, and process flexibility. These are used primarily in leading-edge logic and memory production.

• Key Platforms:

  • XP8 and XP8 QCM: High-productivity platforms supporting multiple process chambers; widely used for high-volume manufacturing.

  • Previum and Previum Pro: Previum systems incorporate an integrated epitaxial (EPI) pre-clean step that effectively removes 15–20 monolayers of native oxide from the substrate surface. This step is crucial for ensuring high-quality EPI film growth.

  • Pulsar®: Specialised for high-k dielectrics, such as hafnium oxide (HfO₂) typically used in gate stacks.

  • Eagle® XP8: Designed for advanced metal ALD (e.g. TiN, W), often used in logic and memory applications including barrier and liner layers.

ASM International’s strategic alignment with the prevailing trends in the wafer fab equipment (WFE) market and its concentrated customer base. Logic and foundry applications are set to remain the dominant segment of WFE spending through 2026, reinforcing ASM’s focus on enabling advanced nodes such as FinFET and GAA, where Epitaxy (Epi) and atomic layer deposition (ALD) are critical. The company’s FY24 revenue profile shows that its top five customers accounted for 51% of sales, while the top ten represented 70%, indicating strong relationships with leading-edge semiconductor manufacturers. These likely include TSMC, Samsung, Intel, SK hynix, and Micron—ASM’s probable top customers given their leading-edge node adoption and high ALD utilisation. Others may include GlobalFoundries, UMC, SMIC, and select IDMs. 

The industry’s shift to gate-all-around (GAA) transistor architectures at 2 nm and beyond is driving increased demand for single-wafer ALD and silicon epitaxy (Si Epi) processes, which are essential for integrating high-k dielectrics, advanced metals, and high aspect ratio features in both logic and memory devices. ASM’s deep engagement with leading-edge customers—particularly in logic/foundry and high-bandwidth memory (HBM) DRAM—has already translated into strong revenue contributions. Additionally, early tool shipments for the 1.4nm node reflect continued confidence from top-tier clients and extend ASM’s growth visibility as chipmakers prepare for more complex architectures requiring precise material deposition.

ASMI presented a robust growth trajectory of the single-wafer Atomic Layer Deposition (ALD) market, projected to reach between US$4.2 billion and US$5.0 billion by 2027, with a compound annual growth rate (CAGR) of 10–14% from 2022.

Summary from ASM International Q1 2025 Earnings Call:

1. ALD Market Outlook:
ALD continues to be a key growth driver for ASM, with equipment sales led by ALD and expectations of a strong increase in GAA (gate-all-around) related demand throughout 2025. ALD intensity is rising as leading-edge nodes (2 nm and 1.4 nm) require more deposition steps for complex 3D structures, high-k dielectrics, and metal gate stacks. ASM confirmed ongoing R&D engagement for 1.4nm and highlighted that ALD demand will further accelerate in next-gen nodes, backside power delivery, and in advanced DRAM (e.g. HBM), which increasingly adopt logic-like ALD layers. ASM remains confident in long-term ALD market growth, forecasting double-digit increases in application layers per node.

2. Trade, Tariffs, and Geopolitical Risk:
ASM addressed potential impacts from new US tariff announcements, noting no immediate effect on equipment, but acknowledging possible indirect macroeconomic consequences. The company has prepared multiple mitigation scenarios, including flexible global manufacturing—already expanding in Korea and establishing capability in Arizona (set to scale in 2H 2026). ASM emphasised its ability to localise production quickly if needed. While there’s been no pull-forward of tool orders due to tariff concerns, the company is monitoring the situation closely and maintaining optionality in its supply chain to navigate shifting trade conditions.

ASM International NV (ASMIY) Q1 2025 Earnings Call Transcript | Seeking Alpha

"ASM International: Upgrade To Strong Buy On Better Growth Visibility And Strength"

ASM International (ASMIY) delivered a strong Q1 FY25, exceeding expectations in revenue, margins, and orders, driven by robust AI infrastructure demand, early ramp-up of 2nm nodes, and resilient performance in China. Despite macroeconomic risks and export controls, ASM saw solid contributions from mature logic foundries and high-bandwidth memory (HBM), which relies on advanced techniques like ALD and Epi. The company’s improved operational efficiency, growing AI demand, and clearer long-term growth visibility led the author to upgrade the stock to a “strong buy,” supported by a belief that ASM can reach the high end of its FY27 revenue target with continued margin expansion.

LINK: ASM International: Upgrade To Strong Buy On Better Growth Visibility And Strength (OTCMKTS:ASMIY) | Seeking Alpha

Semiconductor Equipment Stocks: Analysis of Decline and Recovery (Feb–May 2025)

Between February and May 2025, the semiconductor equipment sector experienced significant market volatility, driven by a combination of geopolitical developments, trade policy shifts, and evolving industry dynamics. Notably, U.S. tariff announcements and uncertainty in AI infrastructure investment led to sharp downturns in stock valuations across key players such as ASML, Applied Materials, KLA, Lam Research, and ASM International. Despite the initial decline, the sector showed resilience with signs of recovery emerging in late April. Here is an overview of the key events influencing these market movements, along with insights into the partial rebound observed by early May.

📉 February 24, 2025: Tariff Concerns and AI Sector Weakness

On February 24, 2025, semiconductor equipment stocks experienced a downturn due to escalating concerns over new U.S. tariffs and a slowdown in the AI sector. President Trump's administration announced a series of tariffs that heightened trade tensions, particularly affecting technology companies with significant exposure to international markets. Additionally, the AI sector faced headwinds as companies like Super Micro Computer Inc. issued profit warnings, citing delays in AI infrastructure investments. These factors collectively contributed to a decline in investor confidence, leading to a sell-off in semiconductor-related stocks.

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📉 March 25, 2025: Temporary Relief Amid Ongoing Uncertainty

On March 25, 2025, there was a brief respite in the downward trend as President Trump announced exemptions for semiconductor equipment and other electronics from the newly imposed tariffs. This announcement provided temporary relief to the market, leading to a modest rebound in semiconductor stocks. However, the relief was short-lived as uncertainties persisted regarding the broader implications of the trade policies and their potential impact on global supply chains.

Stock Market News, March 26, 2025: Nasdaq Falls; Nvidia, Tesla Drop More Than 5%

📉 April 1, 2025: Market Crash Triggered by Sweeping Tariffs

On April 1, 2025, the semiconductor sector was significantly impacted by a broader market crash initiated by the announcement of sweeping tariffs by the U.S. administration. These tariffs affected a wide range of imports, leading to fears of a global trade war and potential recession. The semiconductor industry, being highly globalized and reliant on complex international supply chains, was particularly vulnerable. The market reacted sharply, with semiconductor equipment stocks experiencing substantial declines.

Watch Tariff-Driven Turmoil Drags Stocks to Multiyear Lows | Bloomberg: The Close 04/04/2025 - Bloomberg

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📈 Partial Recovery: Resilience Amid Challenges

Despite the challenges, semiconductor equipment stocks have shown signs of recovery in the subsequent weeks. Several factors have contributed to this partial rebound:

- Strong Earnings Reports: Companies like Cadence Design Systems reported robust earnings, indicating resilience in certain segments of the semiconductor industry.

- Continued AI Demand: The ongoing demand for AI-related technologies has provided support to the semiconductor sector, with companies like ASM International projecting sales growth driven by AI chip demand.

- Tariff Exemptions: The exemption of semiconductor equipment from certain tariffs has alleviated some immediate pressures on the industry, allowing for cautious optimism among investors.

While uncertainties remain, particularly concerning global trade policies and geopolitical tensions, the semiconductor equipment sector has demonstrated a degree of resilience, adapting to the evolving landscape and capitalizing on areas of sustained demand.

The Score: Meta Platforms, McDonald’s, Kohl’s and More Stocks That Defined the Week - WSJ

Stocks to Watch: Nvidia, AMD, Abbott Laboratories, ASML

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Beneq’s Transform® ALD Tool Qualified for High-Volume GaN Power Device Production by Leading Asian Manufacturer

Beneq has announced the qualification of its Transform® ALD cluster tool for high-volume production of GaN-based power devices on 8-inch GaN-on-Si wafers by a major Tier 1 manufacturer in Asia. This achievement marks a significant step in the adoption of Beneq’s ALD technology for high-performance, scalable, and reliable GaN semiconductor applications, which are essential for power electronics and RF devices in sectors such as automotive, datacenters, and consumer electronics. The Transform system’s unique three-step process—including plasma-based surface pre-cleaning, plasma-enhanced ALD, and thermal ALD—ensures high-quality dielectric integration for wide-bandgap semiconductors like GaN and SiC.

Beneq Transform® establishes a completely new class of ALD cluster tool products in it’s versatility and adaptability to address a broad range of applications and market segments. Beneq Transform® configure with multiple ALD process modules to meet a specific wafer capacity requirement or be later upgraded in response to growing volumes or with new ALD applications. (Beneq.com)

According to Yole Intelligence, the power GaN market is set to surpass $2.2 billion by 2029, growing at a robust 41% CAGR from 2023. This tenfold expansion since 2019 is driven primarily by consumer electronics—especially fast chargers—followed by strong momentum in automotive, data center, telecom, and industrial applications. GaN's adoption is expanding into 300W mobile chargers, automotive LiDAR and onboard chargers (OBCs), high-efficiency power supplies for data centers, and future intermediate bus converters. Bidirectional GaN devices and applications in e-bikes, home appliances, and over-voltage protection (OVP) units are also contributing to market penetration.

The ecosystem is rapidly evolving, with over $4 billion invested in Power GaN since 2019 and major M&A activity including Infineon’s acquisition of GaN Systems and Renesas buying Transphorm. IDMs like STMicroelectronics, Nexperia, and Samsung are building capacity, while 8-inch GaN-on-Si is becoming standard, and early work on 12-inch is underway. Technical advances include 1200V GaN devices, bidirectional switches, and GaN-on-QST substrates. While the market is promising, failures like NexGen and BelGaN highlight the risks and capital intensity required for success​. (Yole Development)

The Beneq Transform tool's vacuum-integrated cluster design supports nitride and oxide film deposition with high throughput and competitive cost-of-ownership, making it suitable for HEMTs, integrated circuits, and vertical devices. Seventeen Transform units are now deployed globally in GaN manufacturing and R&D. The company also strengthens its GaN process innovation through its partnership with imec, where a newly installed Transform system supports ongoing research in GaN surface treatment and dielectric integration.

Key Features of the Transform GaN ALD Process

1. Three-Step ALD Process (Proprietary Architecture):

• Plasma-based surface pre-cleaning: Critical for removing contaminants and native oxides from GaN or SiC surfaces to ensure interface integrity.
• Plasma-enhanced ALD (PEALD) of interfacial layers: Enables low-temperature, conformal deposition with precise control, which is essential for GaN where thermal budgets are constrained.
• Thermal ALD of dielectric films: Offers dense and high-quality films with excellent electrical properties for gate dielectrics and passivation layers.

2. Materials Supported:

• Nitrides: AlN, SiN – important for barrier layers, passivation, or etch stops.
• Oxides: Al₂O₃, HfO₂, SiO₂ – used for gate dielectrics, field plates, and interface engineering.

Sources:

Beneq Transform® Qualified for GaN Power Device Production by Tier 1 Asian Manufacturer

Yole Group - Follow the latest trend news in the Semiconductor Industry

ASML Posts Strong Q1 2025 Results Amid AI-Driven Demand and Tariff Uncertainty

ASML kicked off 2025 with solid first-quarter performance, beating expectations on both earnings and revenue as demand for advanced lithography tools—driven by AI and next-generation semiconductor nodes—remained robust. While the company reaffirmed its growth outlook for 2025 and 2026, it also flagged increasing geopolitical uncertainty, particularly around US-China tariffs, as a risk factor for the months ahead.

ASML delivered strong Q1 2025 results, with earnings per share of $6.82 and revenue of $8.80 billion, reflecting a 56% year-over-year increase. The company met or exceeded guidance across major financial metrics, with gross margins at 54%, supported by favorable EUV system configurations and higher average selling prices. Net system sales reached €5.7 billion—€3.2 billion from EUV and €2.5 billion from non-EUV—while Installed Base Management sales added €2 billion. Bookings totaled €3.9 billion, mostly from logic customers. Despite a seasonal dip in free cash flow due to payment timing and capital investments, ASML remains financially strong with €9.1 billion in cash.

CEO Christophe Fouquet and CFO Roger Dassen emphasized the ongoing strength of AI as a demand driver, particularly in advanced logic and memory, while acknowledging growing macroeconomic and geopolitical uncertainties—especially around tariffs. They reiterated revenue expectations for 2025 between €30 billion and €35 billion, with 2026 also anticipated to be a growth year. However, they cautioned that new tariff dynamics introduce significant unknowns for both ASML and its customers, which may affect gross margins and the broader supply chain.

On the technology front, ASML made progress with both its Low NA and High NA EUV systems. The NXE:3800E tool is now shipping at full spec and is seeing strong adoption among logic and memory customers aiming for single-expose EUV. Meanwhile, the High NA NXE:5000 has demonstrated better maturity compared to the Low NA at a similar stage, with customers like Intel and Samsung reporting substantial gains in productivity and process simplification. ASML shipped its fifth NXE:5000 in Q1 and is beginning shipments of the NXE:5200, which will be critical for phase two customer evaluations. Full-scale adoption is expected from 2026–2028, contributing to ASML’s long-term revenue forecast of €44 billion to €60 billion by 2030.

ASML addressed growing concerns over US and China tariffs, highlighting the high level of uncertainty surrounding their scope and impact. The company is actively assessing both direct and indirect consequences, including tariffs on system sales, parts imports, and servicing operations. ASML emphasized that it is working closely with customers and suppliers to mitigate disruptions and ensure that tariff-related costs are fairly distributed across the value chain, rather than being absorbed solely by ASML. While management acknowledged that these discussions are still evolving and outcomes remain unclear, they cautioned that tariffs could introduce volatility in margins, supply chain planning, and customer delivery schedules. Despite this, ASML noted that the current business conversations with customers remain unchanged and the long-term strategic investment momentum—especially in logic and AI-related capacity—appears resilient.

Sources:

ASML Holding N.V. 2025 Q1 - Results - Earnings Call Presentation (NASDAQ:ASML) | Seeking Alpha

ASML Holding N.V. (ASML) Q1 2025 Earnings Call Transcript | Seeking Alpha