ASML Posts Strong Q1 2025 Results Amid AI-Driven Demand and Tariff Uncertainty

ASML kicked off 2025 with solid first-quarter performance, beating expectations on both earnings and revenue as demand for advanced lithography tools—driven by AI and next-generation semiconductor nodes—remained robust. While the company reaffirmed its growth outlook for 2025 and 2026, it also flagged increasing geopolitical uncertainty, particularly around US-China tariffs, as a risk factor for the months ahead.

ASML delivered strong Q1 2025 results, with earnings per share of $6.82 and revenue of $8.80 billion, reflecting a 56% year-over-year increase. The company met or exceeded guidance across major financial metrics, with gross margins at 54%, supported by favorable EUV system configurations and higher average selling prices. Net system sales reached €5.7 billion—€3.2 billion from EUV and €2.5 billion from non-EUV—while Installed Base Management sales added €2 billion. Bookings totaled €3.9 billion, mostly from logic customers. Despite a seasonal dip in free cash flow due to payment timing and capital investments, ASML remains financially strong with €9.1 billion in cash.

CEO Christophe Fouquet and CFO Roger Dassen emphasized the ongoing strength of AI as a demand driver, particularly in advanced logic and memory, while acknowledging growing macroeconomic and geopolitical uncertainties—especially around tariffs. They reiterated revenue expectations for 2025 between €30 billion and €35 billion, with 2026 also anticipated to be a growth year. However, they cautioned that new tariff dynamics introduce significant unknowns for both ASML and its customers, which may affect gross margins and the broader supply chain.

On the technology front, ASML made progress with both its Low NA and High NA EUV systems. The NXE:3800E tool is now shipping at full spec and is seeing strong adoption among logic and memory customers aiming for single-expose EUV. Meanwhile, the High NA NXE:5000 has demonstrated better maturity compared to the Low NA at a similar stage, with customers like Intel and Samsung reporting substantial gains in productivity and process simplification. ASML shipped its fifth NXE:5000 in Q1 and is beginning shipments of the NXE:5200, which will be critical for phase two customer evaluations. Full-scale adoption is expected from 2026–2028, contributing to ASML’s long-term revenue forecast of €44 billion to €60 billion by 2030.

ASML addressed growing concerns over US and China tariffs, highlighting the high level of uncertainty surrounding their scope and impact. The company is actively assessing both direct and indirect consequences, including tariffs on system sales, parts imports, and servicing operations. ASML emphasized that it is working closely with customers and suppliers to mitigate disruptions and ensure that tariff-related costs are fairly distributed across the value chain, rather than being absorbed solely by ASML. While management acknowledged that these discussions are still evolving and outcomes remain unclear, they cautioned that tariffs could introduce volatility in margins, supply chain planning, and customer delivery schedules. Despite this, ASML noted that the current business conversations with customers remain unchanged and the long-term strategic investment momentum—especially in logic and AI-related capacity—appears resilient.

Sources:

ASML Holding N.V. 2025 Q1 - Results - Earnings Call Presentation (NASDAQ:ASML) | Seeking Alpha

ASML Holding N.V. (ASML) Q1 2025 Earnings Call Transcript | Seeking Alpha

Applied Materials Unveils Industry-First Ruthenium-Cobalt Liner and Next-Gen Dielectrics to Enable 2nm Chip Wiring and Boost 3D Stacking for Energy-Efficient AI Computing

Applied Materials has announced new materials engineering breakthroughs aimed at improving energy efficiency in computing by enabling copper wiring to scale down to the 2nm node and beyond. Central to this innovation is the industry’s first high-volume use of ruthenium in a binary metal liner with cobalt (RuCo), which allows for thinner liners, improved copper fill, and up to 25% lower electrical resistance. This innovation, part of the new Endura™ Copper Barrier Seed IMS™ system, combines six process technologies in one high-vacuum system and is already being adopted by major logic chipmakers. These advances address the increasing challenges of interconnect resistance and mechanical weakness as chip feature sizes shrink.

Applied Materials’ new Endura™ Copper Barrier Seed IMS™ with Volta™ Ruthenium CVD combines six different technologies in one high-vacuum system, including an industry-first combination of materials that enables chipmakers to scale copper wiring to the 2nm node and beyond.

Complementing this, Applied also introduced an enhanced version of its long-standing Black Diamond™ low-k dielectric material, designed to reduce capacitance and reinforce chip strength — critical for advanced 3D stacking in logic and memory chips. These solutions help overcome scaling limitations associated with Moore’s Law and are critical for sustaining AI-driven computing advancements. As demand for high-performance, energy-efficient chips grows, Applied’s innovations are expanding its served market for interconnect technologies, which is projected to reach $7 billion per 100K wafer starts per month with the addition of backside power delivery.

With the semiconductor industry’s first use of ruthenium in high-volume production, Applied Materials' new binary metal combination of ruthenium and cobalt (RuCo) enables copper chip wiring to be scaled to the 2nm node and beyond and reduces electrical line resistance by as much as 25 percent.

Applied Materials today introduced an enhanced version of the company’s Producer™ Black Diamond™ PECVD dielectric film. This new material enables chip scaling to 2nm and below, while offering increased mechanical strength to help take 3D logic and memory stacking to new heights.

The new Producer™ Enhanced Black Diamond™ dielectric is a revolutionary product, enabling next-generation chips of the AI era. Enhanced Black Diamond™ addresses two key issues in leading-edge chips. As wires become closer together, parasitic capacitance increases. The phenomenon slows signals down, worsening performance and energy consumption. Additionally, damaging plasma manufacturing processes can cause the thinner insulating dielectric material between wires to fracture or collapse, potentially leading to chip failure (Embedded from Youtube : https://youtu.be/uJju9KNA-yE?si=ae-Eqc0Qaf5J8e0W).

Sources:

Applied Materials Unveils Chip Wiring Innovations for More Energy-Efficient Computing | Applied Materials

Photos accompanying this announcement are available at

https://www.globenewswire.com/NewsRoom/AttachmentNg/96098774-3afd-4e4a-9f5c-e0ba8d523bc2

https://www.globenewswire.com/NewsRoom/AttachmentNg/fd0d0edb-65ea-49ab-a66b-1f5bc5265b16

https://www.globenewswire.com/NewsRoom/AttachmentNg/8c6a061b-92da-4b37-a475-8f57e3884ef4

Neumonda and Ferroelectric Memory Company Collaborate in the Commercialization of Non-Volatile DRAM

Neumonda and Ferroelectric Memory (FMC) are working together to design, provide test solutions, and market FMC’s nonvolatile DRAM+. This collaboration aims nothing less than to bring semiconductor DRAM memory design and manufacturing back to Germany.

Marco Mezger, COO of Neumonda, Thomas Rueckes, CEO of FMC, and Peter Poechmueller, CEO of Neumonda (from left to right), celebrate the collaboration of the two German memory powerhouses

Two German memory innovators join forces to bring semiconductor memory back to Germany

Bad Homburg / Dresden, April 3, 2024 – Neumonda and Ferroelectric Memory (FMC) are working together in the design, provision of test solutions, and marketing of FMC’s nonvolatile DRAM+. This collaboration aims nothing less than to bring semiconductor DRAM memory design and manufacturing back to Germany.

FMC commercializes a disruptive technology that combines non-volatile properties of ferroelectric hafnium oxide (HfO2) with RAM to create a non-volatile DRAM memory for AI, medical, industrial, automotive, and consumer applications. As part of the agreement, Neumonda which holds several patents in the design and testing of DRAM memory, will support FMC with memory consulting services and with its Rhinoe, Octopus, and Raptor test platforms for FMC’s nonvolatile DRAM+ products.

“FMC was founded to exploit the disruptive invention of the ferroelectric effect of HfO2 for semiconductor memories. Applied to a DRAM, it turns the DRAM capacitor into a low power, nonvolatile storage device while maintaining the high DRAM performance to produce a disruptive nonvolatile DRAM memory ideal for AI compute,” explained Thomas Rueckes, CEO of FMC. “Since our technology is unique in the market, cost-effective testing of our memory products is of great importance for our product offerings. With Neumonda and its radically new approach to testing, we have found a partner that can help us speed up the development of our products. We also are excited to work with Neumonda as we share the common vision to bring Memory back to Europe”

Neumonda combines unmatched expertise in memory and, with its Neumonda Technology division, revolutionizes memory testing. Its testers are lightweight, low-cost, and energy-efficient and enable Neumonda to conduct manufacturer-independent tests at a level and detail that has not been possible before—all this at a fraction of the costs of traditional testers.

“As our test platforms are maturing, FMC’s products are an ideal test ground to prove the capabilities of our Rhinoe, Octopus, and Raptor testers, as well as the high-quality yield they enable,” explained Peter Poechmueller, CEO of Neumonda. “One of my personal goals behind founding Neumonda was to bring semiconductor memory back to Europe. With this collaboration, we take a big step closer to establishing a new German memory manufacturer.

About FMC

FMC was founded in 2016 as a spin-off from NaMLab GmbH, a TU Dresden company, to commercialize ferroelectric hafnium oxide technology originally invented by Qimonda, the former German DRAM manufacturer. FMC is a full stack fabless semiconductor company with operations in Dresden (Germany), Milan (Italy) and North America. FMC product offerings include high density, low power, nonvolatile DRAM and Cache chiplets for disruptive performance and power efficiency improvements in edge and cloud AI systems. Since its foundation, FMC has been working closely with Saxonian, Federal German and European funding providers and is very thankful for this continuous support. For more information visit: www.ferrolectric-memory.com

About Neumonda

NEUMONDA combines extensive memory experience with the “DNA” of former memory manufacturer Qimonda, with the aim to offer the most extensive portfolio of specialized memory solutions and competence in the market. It governs MEMPHIS Electronic, a distributor of memory ICs and modules of different suppliers; Intelligent Memory, the manufacturer of DRAM and NAND-based memory solutions; and NEUMONDA Technology which designs and holds IP for application test systems for memory applications. Combining these different areas of expertise, NEUMONDA is able to offer unique global memory competency that can help companies in any industry to meet their current and future memory requirements. www.neumonda.com

AlixLabs to Demonstrate APS™ on 300-millimeter UMC wafers at the 2025 CMC Conference

Atomic Layer Etching Pitch Splitting (APS) proven on more industry-leading wafers, doubling fin density and proving flexibility without EUV.

Austin, TX, USA/Stockholm, Sweden – April 10th, 2025 – AlixLabs AB, a Swedish semiconductor startup specializing in Atomic Layer Etching (ALE), today demonstrates the latest in its line of groundbreaking development in advanced chip fabrication unveiling additional research into its novel semiconductor manufacturing process known as APS™ (Atomic Layer Etching Pitch Splitting) capable of doubling fin density while introducing the unprecedented flexibility to vary pitch and critical dimensions within the same wafer area.

Proven on 300-millimeter wafers provided by United Microelectronics Corporation (UMC), the APS™ technology successfully halved pitch compared to current industry benchmarks. This significant advancement was achieved entirely without relying on expensive and energy-intensive Extreme Ultraviolet (EUV) lithography.

Instead, APS™ leverages advanced etching techniques that substantially enhance sustainability, drastically reducing energy consumption without compromising throughput. Previous demonstrations of the APS™ process, validated through Intel’s Test Vehicle Program[1], confirmed its potential by achieving metal pitches as small as 25 nanometers.

“Today we are sharing more proof that the APS™ process can be a game changer for leading foundries. Thanks to UMC, we have been able to verify our process on production wafers that are shipped in quantities measured in millions of wafers annually,” said Dr. Robin Athle, Principal Researcher at AlixLabs. “Our mission is to create equipment that allows companies that don’t have access to EUV tools to scale down their production to 5 nanometer and beyond. By eliminating the dependency on EUV lithography, we are offering the industry a path towards more sustainable and economically feasible high-density chip production.”

Detailed results from AlixLabs’ UMC wafer tests and further insights into APS™ technology will be presented at the 2025 CMC Conference, scheduled for April 10th in Austin, Texas. Dr. Athle’s presentation “Atomic Layer Etching Pitch Splitting (APS™): a New Alternative to Multi Patterning” will be held at 4:00 PM at the Bergstrom Ballroom in Hilton Austin Airport Hotel.

IBM and Tokyo Electron Extend Strategic Partnership to Advance Chiplet Architectures and High NA EUV for Generative AI Era

IBM and Tokyo Electron (TEL) have renewed their long-standing semiconductor research partnership with a new five-year agreement focused on advancing next-generation semiconductor nodes and chiplet architectures tailored for the demands of generative AI. Building on more than 20 years of collaboration, the companies aim to leverage their complementary strengths—IBM’s semiconductor process integration and TEL’s advanced manufacturing equipment—to develop breakthroughs in performance and energy efficiency, including new approaches to 3D chip stacking and patterning with High NA EUV lithography.

"IBM and Tokyo Electron have built a strong relationship of trust and innovation through years of joint development. We are excited to continue to build on our long-standing partnership with IBM for another five years. This renewed agreement underscores our mutual commitment to advancing semiconductor technologies, including patterning processes with High NA EUV." said Toshiki Kawai, Representative Director, President & CEO Tokyo Electron Limited. "Our collaboration at the has been instrumental in driving innovation, and we look forward to continuing this journey together."

The partnership is anchored at the Albany NanoTech Complex, a world-leading semiconductor R&D ecosystem operated by NY CREATES. This collaboration has already played a key role in positioning the site as the National Semiconductor Technology Center’s EUV Accelerator. IBM and TEL will continue joint research at Albany, accelerating U.S. leadership in chip innovation and enabling critical infrastructure for the generative AI era.

Company Summaries:

Tokyo Electron (Japan): A global leader in semiconductor production equipment, specializing in lithography, etch, and deposition systems.

IBM (U.S.): A technology and research powerhouse with deep expertise in semiconductor design, AI, and hybrid cloud infrastructure.

Sources:

Tokyo Electron & IBM Renew Collaboration for Advanced Semiconductor Technology | TechPowerUp

Semiconductor Equipment Not Listed in Tariff Exemptions and EU and Japanese Suppliers Show Market Resilience

As of April 6, 2025, semiconductor equipment is not explicitly included in the list of exempted products under the U.S. tariffs detailed in Annex II of President Donald Trump’s executive order. While semiconductors and electronic components such as integrated circuits and diodes are covered, the exemption does not extend to manufacturing equipment.

Since the April 2, 2025 tariff announcement, ASML’s stock fell about 9.5%, showing more resilience than the Philadelphia Semiconductor Index (SOX), which dropped approximately 16.7% (deepest point).

Semiconductor equipment not listed in tariff exemptions, but EU and Japanese suppliers show market resilience

Despite this, European and Japanese semiconductor equipment companies have shown relative resilience in the wake of the April 2 tariff announcement. ASML, the Netherlands-based manufacturer of advanced lithography tools, saw its stock fall by about 9.5 percent, compared to a sharper 16.7 percent drop at the lowest point for the Philadelphia Semiconductor Index (SOX). This suggests continued investor confidence in ASML’s position and the essential nature of its equipment in semiconductor manufacturing.

Other global equipment firms also experienced moderate declines. ASM International, also from the Netherlands, saw an 8.3 percent drop. Tokyo Electron, Japan’s leading chip tool supplier, declined by 8.1 percent. In contrast, US-based companies faced more significant losses: Applied Materials dropped 14.1 percent, Lam Research fell 19.9 percent, and KLA Corporation declined by 16 percent between April 2 and April 4.

The broader tariff policy applies a 10 percent baseline rate on most imports starting April 5, with higher rates—up to 50 percent—for goods from 83 countries (including EU members) beginning April 9. Annex II outlines exemptions across multiple sectors: critical minerals, pharmaceuticals, energy products, integrated circuits, and fertilizers. However, semiconductor manufacturing equipment is not among the listed exemptions, indicating it remains subject to the new tariffs unless otherwise specified in future regulatory clarifications.

Despite this, the muted market response for EU and Japanese equipment makers highlights their global significance and the likelihood that US firms will continue to source vital tools from these suppliers, tariffs notwithstanding.

Background:

Starting on April 5, a 10% baseline tariff will be applied to nearly all products from all countries, with a few notable exceptions explained later. The executive order’s Annex I lists 57 countries (83 when accounting for all European Union member states) that will face higher tariffs of up to 50%, which go into effect on April 9. The new tariffs will stack on previous product-specific tariff rates. As a reminder, a tariff is a tax paid at the border by an importer seeking to bring products into the United States from a foreign country.

The exempted items in Annex II include, but are not limited to: copper, pharmaceuticals, semiconductors, lumber articles, certain critical minerals, energy/energy products, and products facing section 232 tariffs from the current administration (steel, aluminum, automobiles and any future section 232 investigations). While some of these industries were exempted due to their important roles in the economy (energy and critical minerals), others were excluded as they are a target for future restrictions (copper, lumber, pharmaceuticals and semiconductors).

Annex II lists a range of products exempted from trade actions, categorized across several sectors. It includes critical minerals and ores, such as copper, cobalt, lithium, tungsten, manganese, rare-earth elements, and graphite.

It also covers a wide array of chemicals and industrial compounds, including hydrofluoric acid, titanium dioxide, aluminum oxide, and various oxides, chlorides, and sulfates.

A significant portion of the list includes energy products, such as crude oil, natural gas (liquefied and gaseous), coal, petroleum derivatives, lubricants, and electricity.

The Annex lists several electronic components, including integrated circuits (processors, memory, amplifiers, other ICs), semiconductor devices (diodes, transistors, thyristors, optical isolators), and parts for these devices.

In agriculture, exempted products include fertilizers containing potash and NPK compounds, peat, and veterinary vaccines.

The document also includes many pharmaceuticals and medical products, such as antibiotics, hormones, vitamins, vaccines, and active pharmaceutical ingredients (APIs), along with cell therapy products and clinical trial materials.

There are exemptions for polymers and plastics in primary forms, including polyethylene, polypropylene, PTFE, silicones, and epoxide resins.

Additionally, doped materials for electronics, such as silicon wafers (HTS 38180000), and pigments and colorants like titanium dioxide and copper phthalocyanine, are listed.

Sources:

Understanding the New Tariffs | Market Intel | American Farm Bureau Federation

Tariffs Won’t Stop Companies Buying ASML’s Machines—Heard on the Street

BALD Engineering - Semiconductor & Strategic Tech Weekly Summary

Tariffs, Trade & Supply Chain Disruptions

Despite the US exempting semiconductors from new tariffs, chip stocks plunged, dragging the Nasdaq Composite into a deeper correction—now down over 20% since December. Major players like Marvell, ON Semiconductor, Broadcom, and Microchip posted double-digit losses, while Nvidia and Micron also fell sharply, erasing much of their recent gains. The Philadelphia Semiconductor Index (SOX) dropped 7.6% in a single day, marking its lowest point since November 2023.

Adding to the pressure, China retaliated with a sweeping 34% tariff on all US imports, while concerns mount over broader supply chain disruptions.

Tariff Reality Check: The Taiwan Dependency

While most semiconductors are manufactured in Taiwan, relocating chip production to the US offers limited tariff relief. Even if chips are fabricated in the US, they often must return to Taiwan for testing and packaging, stages still dominated by Taiwanese subcontractors.

From Semiconductor supply chain by Calus Aasholm, subscribe to his blog here: https://lnkd.in/d2ZXMHjw

Claus Aasholm points out that, even if test and assembly were moved, final packaged chips are still sent back to Taiwan to be integrated into devices like phones, PCs, and servers. Moreover, the bulk of materials used across the value chain still come from outside the US.

Given these realities, and in light of unpredictable tariff policies, manufacturing outside the US currently remains more cost-effective and reliable. Notably, the Taiwan-specific tariffs could hurt US firms the most, as Taiwan leads in semiconductor design and in key product segments like PCs, servers, and smartphones.

Apple, heavily dependent on Southeast Asia for production, also declined 7.3%. Sub-equipment providers like MKS Instruments and Advanced Energy suffered proportionally steep losses before markets closed for the weekend.

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Technology Leadership & Industry Momentum - Ångström Era Has Arrived

At its Vision 2025 conference, Intel announced that its 18A (1.8nm) process node has officially entered risk production, marking a major milestone in its “five nodes in four years” roadmap set to reclaim tech leadership from TSMC. According to Intel’s Kevin O’Buckley, 18A will be the first node to feature RibbonFET gate-all-around transistors and PowerVia backside power delivery.

Intel is also progressing toward its 14A node, leveraging High-NA EUV lithography, representing a leap in scaling capability.

In parallel, Intel is bringing high-volume 3nm chip production to Europe in 2025 through Fab 34 in Leixlip, Ireland. This facility will support Xeon 6 server chips and expand Intel Foundry Services’ offerings in Europe—part of Intel’s push to localize and diversify its global footprint.

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Critical Materials, Tariffs & European Innovation

Looking ahead, the Critical Materials Council (CMC2025) summit kicks off next week in Austin, Texas, at a moment of intensified scrutiny on material dependencies. On April 2, the US imposed 10–50% tariffs on a broad array of semiconductor-enabling materials, many of which the US is a net importer of. The list includes:

1️⃣ Specialty Gases and Etchants

• Neon [Ne], Krypton [Kr], Xenon [Xe]

• Nitrogen trifluoride [NF₃], Hexafluorodisilane [Si₂F₆]

• Sulfur hexafluoride [SF₆], Carbon tetrafluoride [CF₄], Octafluorocyclobutane [C₄F₈], Trifluoromethane [CHF₃]

• Fluorinated silanes, Ultra-pure hydrogen [H₂]

2️⃣ High-Purity Metals and Elements

• Gallium [Ga], Indium [In], Germanium [Ge]

• Tantalum [Ta], Niobium [Nb], Hafnium [Hf], …

3️⃣ Rare Earth Elements (REEs)

• Yttrium [Y], Terbium [Tb], Dysprosium [Dy]

• Neodymium [Nd], Lanthanum [La], Cerium [Ce]

• Praseodymium [Pr], Samarium [Sm], Europium [Eu], Gadolinium [Gd], Scandium [Sc]

4️⃣ Semiconductor Substrates and Wafers

• Monocrystalline silicon wafers (300mm), Silicon-on-insulator wafers [SOI]

• Silicon carbide [SiC], Sapphire [Al₂O₃], Gallium nitride [GaN], Gallium arsenide [GaAs], Indium phosphide [InP]

5️⃣ Photoresists and Lithography Materials

• EUV photoresists, Chemically amplified resists (CARs)

• KrF and ArF excimer laser gas blends

6️⃣ CMP and Wet Process Materials

• Colloidal ceria, High-purity alumina slurries, High-purity silica [SiO₂]

• Advanced CMP slurries and pads, Rare-earth-based slurries

7️⃣ CVD/ALD Precursors

• Trimethylaluminum [TMA], Tetrakis(ethylmethylamino)hafnium [TEMAH], Titanium tetrachloride [TiCl₄]

• High-purity silanes [SiH₄, TEOS], Organometallic precursors for metal gates and high-k dielectrics

Gadolinium: A Strategic Blind Spot

A glaring vulnerability emerged: gadolinium, a rare earth essential for over 30 million MRI scans annually, is almost entirely sourced and refined in China. Prices have risen over 50% since 2017, and any disruption would heavily impact GE Healthcare, Bayer, Bracco, and Guerbet—all of whom rely on it for MRI contrast agents. Yet, it remains overlooked in US trade strategies.

Swedish Tech start up GREEN14 Breakthrough in Sustainable Recovery

In Switzerland last week, GREEN14 partnered with Oerlikon for a successful testing program using DC plasma equipment to validate its multi-material hydrogen plasma process. The company demonstrated the recovery of:

✅ Copper from copper sulfide

✅ Titanium from titanium dioxide

✅ Tungsten from tungsten oxide

✅ Aluminium from aluminium oxide

This progress confirms the scalability of GREEN14’s clean tech process, unlocking new sustainable pathways to critical raw materials beyond silicon. It supports Europe’s push toward resilience, emissions reduction, and strategic material independence.

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SemiWiki CEO Interview with Jonas Sundqvist of AlixLabs

In a recent interview with Daniel Nenni, Jonas Sundqvist, CEO and co-founder of AlixLabs, discussed the company’s pioneering role as the world’s only pure-play Atomic Layer Etch (ALE) equipment provider. Drawing on his academic background in ALD and CVD from Uppsala University, Sundqvist explained how AlixLabs’ APS (ALE Pitch Splitting) technology enables atomic-scale precision in semiconductor patterning. APS helps chipmakers reduce process complexity, lower costs by up to 40% per mask layer, and improve yield, particularly in advanced logic and memory manufacturing. As the industry pushes toward sub-10 nm nodes, APS offers a scalable and sustainable alternative to traditional multi-patterning and EUV lithography.

Sundqvist emphasized that AlixLabs addresses critical pain points in semiconductor production, such as increasing lithography costs, complexity, and sustainability concerns. By minimizing energy use, reducing fluorinated gas emissions, and improving process efficiency, APS supports a greener and more cost-effective manufacturing path. AlixLabs differentiates itself from giants like ASML and proponents of self-aligned multi-patterning by offering a complementary technology that simplifies patterning. The company is currently collaborating with major chipmakers and research institutes, preparing a Beta tool for pilot testing by late 2025 and targeting high-volume manufacturing between 2027 and 2029.

Sources:

CEO Interview with Jonas Sundqvist of AlixLabs - SemiWiki

EU Business Hub | Semicon Japan 2024 Business Mission - Introducing AlixLabs AB

Introducing AlixLabs AB (Sweden): one of our selected companies to participate on the EU Business Hub at Semicon Japan 2024. 

During the recent EU Business Hub at Semicon Japan 2024 business mission that took place between the 9th and 13th of December, we witnessed the spark of global collaboration in action. European and Japanese companies participating in the mission shared their impressions – and their feedback reveals exciting opportunities on the horizon. 

The EU Business Hub at Semicon Japan 2024 mission stood out for its comprehensive approach to supporting European businesses seeking to enter the Japanese market: 

Tailored B2B Matchmaking: European companies had the chance to meet with key Japanese industry players through personalized B2B meetings, fostering future partnerships.

Market Intelligence & Local Expertise: Participants received valuable market insights and coaching on business culture, provided by the programme team, helping them navigate the Japanese market with ease.

Cultural & Linguistic Support: Expert interpreters and briefings on Japanese business culture ensured that each interaction was smooth and effective.

EU-Branded Pavilion: A platform for European companies at Semicon Japan 2024, showcasing cutting-edge solutions and elevating visibility among global tech leaders.

3rd and Last Call for Papers, and List of Speakers / Symposium on ALD & ALE Applications #21, at 248th ECS Fall Meeting / Oct. 12-16, 2025 in Chicago, USA

This fall, the 248th ECS Meeting will be held on Oct. 12-16, 2025 in Chicago (IL, USA), and is expected to gather some 3,000 participants and 40 exhibitors from both academia and industry.

The conference has a strong focus on emerging technology and applications in both solid-state science & technology and electrochemistry.

• General information and the Meeting Program can be found here: Important Information and Call for Papers.
• For more information about our annual symposium G01 and the conference website: Meeting Information. 

The organizers of symposium G01 on “Atomic Layer Deposition & Etching Applications, 21” encourage you to submit your abstract(s) on topics, comprising but not limited to: 

1. Semiconductor CMOS applications: development and integration of ALD high-k oxides and metal electrodes with conventional and high-mobility channel materials; 

2. Volatile and non-volatile memory applications: extendibility, Flash, MIM, MIS, RF capacitors, etc.; 3. Interconnects and contacts: integration of ALD films with Cu and low-k materials; 

4. Fundamentals of ALD processing: reaction mechanisms, in-situ measurement, modeling, theory; 

5. New precursors, delivery systems & sustainability issues; 

6. Optical, photonic and quantum applications; applications aiming at Machine Learning, Artificial Intelligence 

7. Coating of nanoporous materials by ALD; 

8. Molecular Layer Deposition (MLD) and hybrid ALD/MLD; 

9. ALD for energy conversion applications such as fuel cells, photovoltaics, etc.; 

10. ALD for energy storage applications; 

11. Productivity enhancement, scale-up and commercialization of ALD equipment and processes for rigid and flexible substrates, including roll-to-roll and spatial processing; 

12. Area-selective ALD; 

13. Atomic Layer Etching (‘reverse ALD’) and related topics aiming at self-limited etching, such as atomic layer cleaning, etc. 

FYI: Last year at the PRiME 2024 Meeting in Honolulu, our symposium G01 on ALD & ALE Applications 20 attracted some 80 participants, attending a full 3-days schedule with 50 presentations (42 oral, of which 16 invited, plus 8 poster presentations). We expect to be at least as successful this Fall in Chicago. 

Abstract submission 

Meeting abstracts should be submitted not later than the deadline of March 28, 2025 via the ECS website: Submission Instructions

Submission Instructions Invited speakers A list of invited speakers follows below: 

Visa and travel For extensive information, see last year’s version: VISA AND TRAVEL INFORMATION

In addition, ECS’ Francesca Di Palo (francesca.dipalo@electrochem.org) can provide you with an official participation letter issued by the Electrochemical Society. For (limited) general travel grant questions, please contact travelgrant@electrochem.org. 

As in the past years, we expect also our symposium to be able provide some partial travel allowance to selected speakers. We are looking forward to meeting you all at our symposium G01 on ALD & ALE Applications 21, in Chicago | Oct. 12-16, 2025!

Bridging the Lab-to-Fab Gap: Overcoming ALD Scaling Challenges with Chipmetrics, Finland

Scaling Atomic Layer Deposition (ALD) from laboratory research to high-volume semiconductor manufacturing presents numerous challenges, particularly as the industry moves towards more complex 3D structures like 3D NAND, Through-Silicon Vias (TSVs), and nanosheet transistors. One major hurdle is the disparity between lab-scale process development and industrial fabrication, where variations in chamber design and wafer size can lead to unexpected process deviations. Additionally, throughput and cost considerations play a critical role, as slow deposition rates can hinder industrial adoption due to high operating expenses. Defect control is another key concern, as even minuscule particle contamination can significantly impact yield, yet many research facilities lack the advanced defect detection capabilities necessary for high-volume manufacturing. Furthermore, test structure availability is a limiting factor, with sub-100 nm, high-aspect-ratio structures often restricted to leading semiconductor manufacturers, creating barriers for process validation and qualification.

Chipmetrics' PillarHall® metrology chips offer an innovative solution to these challenges by providing dedicated test structures with aspect ratios up to 10,000:1, allowing for rapid and cost-effective ALD validation without the need for complex cross-sectional analysis. These metrology chips facilitate the development of high-aspect-ratio thin film depositions by enabling researchers and manufacturers to evaluate process performance in a scalable manner, ensuring compatibility with industrial requirements. Beyond technical validation, the ability to conduct precise, non-destructive measurements enhances efficiency and reduces development costs, accelerating the transition from lab to fab. As semiconductor manufacturing continues to evolve, tools like PillarHall play a crucial role in streamlining the process transfer while maintaining the precision and reliability demanded by the industry.

PillarHall LHAR4 Test Chip in animated presentation. How to use the PillarHall chip in characterizing 3D thin film process conformality. Lateral High Aspect Ratio, Ultra High Aspect Ratio, Thin Film, Conformal, Deposition, Atomic Layer Processing, Atomic Layer Deposition, Chemical Vapor Deposition, ALD, CVD, HAR, 3D, metrology, Atomic Layer Etching, ALE

In this insightful presentation given by the inventor of PillarHall test chips, Professor Riikka Puurunen from the School of Chemical Engineering, Department of Chemical and Metallurgical Engineering at Aalto University, talks about "Recent Progress in Analysis of the Conformality of Film by Atomic Layer Deposition.

Source:

Challenges of Transferring Deposition Processes to Industry Partners in the Semiconductor Industry - Chipmetrics

ALD FOR INDUSTRY 2025: Advancing Atomic Layer Deposition from Science to Industrial Applications in Dresden

The 8th International Conference "ALD for Industry" took place in Dresden from March 11 to 12, 2025, bringing together experts to discuss advancements in Atomic Layer Deposition (ALD) technology. In addition to the previously mentioned presentations, the conference featured several notable talks:

Prof. Fred Roozeboom

AlixLabs and Aether Semiconductor

Silicon Austria Labs

ASM International

The handshake

Prof. Riikka Puurunen

"Fundamentals of Atomic Layer Deposition: A Tutorial" by Prof. Riikka Puurunen

Prof. Riikka Puurunen from Aalto University, Finland, delivered a comprehensive tutorial on the fundamentals of ALD. She covered the history of ALD, its underlying surface chemistry, typical reaction mechanisms, and growth modes. Prof. Puurunen also discussed the role of diffusion in 3D structures and provided insights into surface reaction kinetics.

​In her tutorial titled "Fundamentals of Atomic Layer Deposition," Prof. Riikka Puurunen of Aalto University provided a comprehensive overview of ALD, a nanotechnology technique for precise surface modifications and thin coatings. She traced ALD's dual origins: Atomic Layer Epitaxy (ALE) developed by Tuomo Suntola in 1974, and Molecular Layering (ML) introduced by Valentin Aleskovskii and Stanislav Koltsov in the 1960s. The tutorial delved into the core principles of ALD, emphasizing its reliance on repeated, self-terminating reactions between gaseous reactants and surfaces. Prof. Puurunen categorized typical reaction mechanisms, discussed factors influencing saturation and growth modes, and highlighted "growth per cycle" (GPC) as a fundamental characteristic of ALD processes. She also explored the role of diffusion in complex 3D structures, noting how diffusion-limited growth can provide insights into surface reaction kinetics. The presentation available at Fundamentals of ALD: tutorial, at ALD for Industry, Dresden, by Puurunen 2025-03-11 | PPT

"Spatial ALD of IrO₂ and Pt Films for Green H₂ Production by PEM Electrolysis" by Dr. Paul Poodt

Dr. Paul Poodt, Chief Technology Officer at SparkNano, presented on the application of spatial ALD in fabricating iridium dioxide (IrO₂) and platinum (Pt) films. These materials are crucial for enhancing the efficiency of proton exchange membrane (PEM) electrolyzers used in green hydrogen production. Dr. Poodt highlighted how spatial ALD enables precise control over film thickness and composition, leading to improved performance and durability of electrolyzer components.

SparkNano’s CTO, Paul Poodt, presented on Spatial ALD of IrO₂ and Pt Films for Green H₂ Production by PEM Electrolysis on March 12 at 10:20 AM during the Emerging Applications session. Attendees had the opportunity to connect with him to discuss SparkNano’s spatial ALD technology.

"Advancements in ALD for Next-Generation Semiconductor Devices" by Dr. Christoph Hossbach

Dr. Christoph Hossbach from Applied Materials / Picosun Europe discussed recent progress in applying ALD techniques to next-generation semiconductor devices. His presentation covered the integration of ALD processes in manufacturing advanced transistors and memory devices, emphasizing the role of ALD in achieving atomic-scale precision and conformality required for modern microelectronics. 

"ALD Applications in Quantum Technology" by Dr. Martin Knaut

Dr. Martin Knaut of TU Dresden explored the utilization of ALD in developing components for quantum technologies. He highlighted how ALD's ability to deposit uniform and defect-free thin films is essential for fabricating qubits and other quantum devices, potentially leading to more stable and scalable quantum computing systems. 

"Emerging Applications of ALD in the Medical Field" by Dr. Mira Baraket

Dr. Mira Baraket from Atlant 3D presented on the potential of ALD in medical applications, including the development of biocompatible coatings for implants and drug delivery systems. She discussed how ALD can enhance the performance and safety of medical devices by providing precise control over surface properties.

Sources:

ALD for Industry 2025 – EFDS

AlixLabs Demonstrates 3 nanometers on Intel Silicon – Without EUV

The Swedish semiconductor company has fabricated leading-edge structures without using complex and costly lithography techniques.

The Swedish semiconductor company AlixLabs announces that it has used its technology to etch structures equivalent to commercial 3-nanometer circuits on Intel test silicon. Notably, this has been achieved without the use of extreme ultraviolet lithography (EUV) or advanced multi-patterning techniques such as SADP and SAQP (Self-Aligned Double Patterning and Self-Aligned Quad Patterning, respectively).

AlixLabs, a startup based in Lund, specializes in the development of Atomic Layer Etching (ALE), a type of plasma-based dry etching for cutting-edge structures, and ALE Pitch Splitting (APS), which enables transistor fins to be split using etching. The advantage of this approach is that it significantly reduces costs at the cutting edge, where wafer prices skyrocket with each new generation.

"We are pleased to demonstrate how APS can help the industry reduce its dependence on multi-patterning while lowering costs and environmental impact. Our technology enables the fabrication of sub-10-nanometer structures on silicon, and through Intel’s Test Vehicle Program, we have proven that sub-5-nanometer structures can be achieved using etching alone."

– Dmitry Suyatin, CTO and Co-Founder of AlixLabs

According to Dmitry Suyatin, AlixLabs’ CTO, this demonstration was made possible through Intel’s Test Vehicle Program, which provided test silicon for AlixLabs to process with its APS technology. While ALE has traditionally been limited to structures in the 10-nanometer class, AlixLabs' APS technique has significantly simplified the manufacturing of structures smaller than 5 nanometers.

Etching 3-nanometer-class structures without advanced EUV lithography, using only immersion lithography, is a significant breakthrough—provided the technology can be scaled and applied in practical manufacturing. AlixLabs has previously stated its goal of seeing its technology adopted by TSMC and Samsung for their 2-nanometer processes.

Since the industry moved past the 28-nanometer node, multi-patterning has become increasingly necessary to create smaller structures and transistors. This lithographic technique involves breaking down complex patterns into simpler ones and sequentially patterning them onto the silicon wafer for higher precision and detail. Lithography can perform this in two, three, or four steps (SADP, SAQP), though more steps are theoretically possible, they are considered too complex and costly for practical use at smaller nodes.

"APS technology demonstrates that complex multi-patterning techniques such as SADP and SAQP are not needed to manufacture circuits at 5 nanometers and below. This increases the potential to use immersion lithography for critical mask layers in 3-nanometer processes. These results were achieved with our early Alpha equipment, and Beta equipment will follow later in 2025. We thank Intel for enabling this demonstration and providing high-quality test silicon."

– Jonas Sundqvist, CEO and Co-Founder of AlixLabs

While lithographic multi-patterning is often necessary, it comes with several downsides. Each additional step requires more masks, which must be precisely aligned to form the final, complex pattern. Even a slight misalignment can lower yield and performance, but more importantly, it significantly extends production time. Avoiding multi-patterning whenever possible is therefore always preferable.

It is essential to distinguish between "nanometer-class" structures and actual physical nanometer measurements. What AlixLabs has achieved is a metal pitch (the distance between metal interconnects connecting transistor gates) of 25 nanometers through dry etching. This compares to TSMC’s most advanced 3-nanometer process, which achieves a metal pitch as low as 23 nanometers in certain high-density configurations.

AlixLabs highlights this test silicon as a major milestone towards commercialization and announces that more updates will follow later in 2025. Additional details will be presented by CTO Dmitry Suyatin at SPIE Advanced Lithography + Patterning in San Jose, California, on February 27, from 9:00–9:20 AM (local time).

Sources:

AlixLabs demonsterar 3 nanometer på Intel-kisel – utan EUV – Semi14

AlixLabs to Showcase Latest APS™ Findings at SPIE Advanced Lithography + Patterning – AlixLabs

Browse the 2025 program for SPIE Advanced Lithography + Patterning

JSR Expands Global Semiconductor Material Capabilities with New Photoresist Facilities, Advanced MOR Variants, and Strategic Acquisition of CVD/ALD Precursor Firm

JSR Corporation is expanding its global development and production of advanced photoresists by establishing a new R&D center in Japan and constructing a semiconductor photoresist plant in Korea. Since acquiring Inpria Corporation in 2021, JSR has been commercializing Metal Oxide Resist (MOR) for EUV lithography. The new R&D center in Japan’s Kanto region will enhance collaboration with global customers and partners, while the Korean plant, expected to begin operations in 2026, will handle the final production process for MOR to support local adoption. JSR aims to drive innovation in photoresists and help customers establish commercial production processes worldwide.

JSR's MOR, developed through its 2021 acquisition of Inpria Corporation, is a next-generation photoresist designed for EUV lithography. MOR is based on metal oxide nanoparticles, offering superior etch resistance and improved pattern resolution compared to traditional chemically amplified resists (CARs). This allows for finer feature definition and reduced line-edge roughness, critical for advanced semiconductor manufacturing below 10 nm. JSR has been scaling MOR for commercial adoption, with major semiconductor manufacturers evaluating its use in high-volume production. The company is expanding its R&D and manufacturing capacity, including a new R&D center in Japan and a production facility in Korea, to support global adoption of MOR.

JSR have investigated different flavors of MOR for EUV lithography, primarily focusing on variations in metal cores and process optimizations. Initially, zirconium (Zr) and hafnium (Hf) based MORs were explored, but their relatively low EUV absorption led researchers to investigate alternative metal cores such as titanium (Ti), zinc (Zn), indium (In), and tin (Sn). These new metal cores exhibited improved lithographic performance, achieving higher EUV absorption, smaller particle size, and better scum reduction. Additionally, process optimizations such as using higher dissolution rate photoacid generators (PAGs), new organic solvent developers, and lower soft bake temperatures were tested to improve scum removal and resolution. The new metal core variants demonstrated resolutions down to 13 nm with reduced defects, suggesting their potential for advanced semiconductor manufacturing.

In August 2024, JSR Corporation completed the acquisition of Yamanaka Hutech Corporation (YHC), a Kyoto-based manufacturer specializing in high-purity chemicals for semiconductor manufacturing. This strategic move allows JSR to expand its product portfolio to include Chemical Vapor Deposition (CVD) and Atomic Layer Deposition (ALD) precursors, which are essential for forming advanced and complex semiconductor device structures. YHC, established in 1960, has over 60 years of experience in advanced molecular design, synthesis technology, and quality control systems, supplying high-quality CVD/ALD precursors to leading-edge semiconductor device manufacturers. The acquisition aligns with JSR's strategy to strengthen its position as a global supplier of semiconductor materials, enhancing its capabilities in both miniaturization and device structure innovation.

Sources:

JSR Expands Global Development and Production Functions for Leading-Edge Photoresists | 2024 | News | JSR Corporation

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High-Precision ALD and Etching Techniques Enable Sub-1nm EOT in Monolayer MoS₂ Transistors

Researchers from Stanford University and Yonsei University have investigated the role of silicon seed layers in enabling high-quality atomic layer deposition (ALD) of HfO₂ on monolayer MoS₂, achieving sub-nanometer equivalent oxide thickness (EOT) and precise threshold voltage control.

Researchers developed a method to achieve sub-1 nm equivalent oxide thickness (EOT) in monolayer MoS2 transistors using atomic layer deposition (ALD) of HfO2 with a silicon seed layer, enabling improved threshold voltage control and low hysteresis. They investigated six seed layer candidates (Si, Ge, Hf, La, Gd, Al2O3) and found that only Si and Ge preserved the integrity of MoS2. The Si seed provided the best interface, allowing for the fabrication of normally-off transistors with a well-behaved threshold voltage. The resulting devices demonstrated a low EOT of approximately 0.9 nm, minimal leakage current (<0.6 μA/cm²), and a subthreshold swing of ~80 mV/dec at room temperature. This method offers a simple and accessible approach to depositing high-quality top-gate dielectrics in common nanofabrication facilities.

The manufacturing process of monolayer MoS2 transistors in the study involves several key steps, including atomic layer deposition (ALD) and etching processes:

1. MoS2 Growth and Device Preparation: Monolayer MoS2 is synthesized using chemical vapor deposition (CVD) at 750°C on a SiO2 (90 nm) / p++ Si substrate. Alignment markers are deposited, and large contact pads (SiO2/Ti/Pd) are patterned and lifted off.

2. Channel Patterning and Etching: The transistor channels are defined via electron-beam lithography and etched using xenon difluoride (XeF2) chemistry. Gold source and drain contacts are then deposited using electron-beam evaporation.

3. Seed Layer Deposition: For the top-gate structure, ultrathin Si and Ge seed layers (~1 nm) are deposited using e-beam evaporation under high vacuum (~10⁻⁷ Torr). These seed layers are exposed to air before undergoing characterization via Raman and XPS measurements.

4. Atomic Layer Deposition (ALD) of HfO₂: The Si or Ge-seeded samples are placed in the ALD chamber at 200°C for 30 minutes before initiating the deposition process. HfO₂ is grown using tetrakis(dimethylamido)hafnium (TDMAH) and H₂O as precursors at 200°C. The ultrathin Si seed oxidizes into SiOx, forming a high-quality interface for dielectric growth.

5. Top-Gate Metallization and Etching: The Pd top gate is patterned and deposited using e-beam evaporation. To expose the contact pads for probing, the top-gate oxide is selectively removed using inductively coupled plasma (ICP) etching with CF₄.

6. Annealing: The top-gated devices undergo vacuum annealing at 150°C, while back-gated devices without top gates are annealed at 250°C for two hours to remove moisture and stabilize electrical characteristics.

This process enables the formation of high-quality MoS₂ transistors with sub-1 nm equivalent oxide thickness (EOT), low leakage, and precise threshold voltage control.

Sources:

Sub-Nanometer Equivalent Oxide Thickness and Threshold Voltage Control Enabled by Silicon Seed Layer on Monolayer MoS2 Transistors | Nano Letters

nl4c01775_si_001.pdf

Accuron Acquires Trymax to Strengthen Plasma Etch Equipment Portfolio and Expand Global Reach

Accuron Technologies has acquired a controlling interest in Trymax Semiconductor Equipment, a specialist in plasma-based and UV-based process equipment for semiconductor manufacturing. This acquisition strengthens Accuron’s presence in the semiconductor equipment sector and enhances its portfolio in the Etch & Clean process segment. Trymax, headquartered in the Netherlands, will continue to be led by its existing management team, ensuring continuity and execution of its expansion strategy. With Accuron’s resources and network, Trymax aims to accelerate its growth, broaden its customer base, and enhance product development. This move marks a strategic step for both companies, leveraging synergies to drive innovation and global expansion in semiconductor manufacturing solutions.

Sources:

Trymax joins Accuron Technologies group for further growth and expansion - Trymax Semiconductor