Showing posts with label multiple patterning. Show all posts
Showing posts with label multiple patterning. Show all posts

Tuesday, August 30, 2022

Comparison confirms that SMIC reaches 7nm without access to western equipment & technologies

Similarities with TSMC 7nm have been found

After TechInsights revealed their initial findings on the SMIC MinerVa Bitcoin mining processor, their team did further analysis and comparison against TSMC 7nm. This new analysis confirms that despite current sanctions restricting access to the most advanced equipment technologies, Chinese Semiconductor Manufacturing International Corporation (SMIC) has used 7nm technology to manufacture the MinerVa Bitcoin Miner application-specific integrated circuit (ASIC).

The TechInsights analysis also uncovered many similarities between the SMIC 7nm and the TSMC 7nm, which are available in our comparison brief.




According to the SeekingAlpha assessment earlier this year (Applied Materials: SMIC Move To 7nm Node Capability Another Headwind (NASDAQ:AMAT) | Seeking Alpha) SMIC is using a large amount of multiple pattering mask layers like in the first TSMC and Samsung 7 nm nodes (N7). 

"At 7nm, normally 15 DUV systems and 5 EUV systems are demanded, depending on chip type and company. However, since SMIC is not permitted to use EUV, then they will be substituted by DUV, and 20 DUV systems will be used.

In both cases, multiple patterning is done to delineate that pattern, whether it is 28nm or 7nm. This multiple patterning process is more or less a trick to reach even the 28nm dimensions. The multiple patterning is typically a combination of deposition, etch, and lithography steps.

If we look at Chart 3 below, using immersion DUV (ArF-1) at the 20nm node there are 13 mask layers, each of which uses multiple dep-etch steps. If we move across the top of the chart, at 10nm there are 18 mask layers, an increase of 50% in the use of deposition-etch steps.

Multiple patterning at the 7nm node, as shown in the bottom left of the chart, requires 27 mask layers. However, by switching to EUV (bottom right) at 7nm, only 14 mask layers are required, similar to the 20nm node with DUV.

The terminology is as follows in switching from DUV to EUV:Double litho, double etch (LELE) process will be eliminated

While ArF-I would continue to be used for the self-aligned double patterning (SADP) and
Self-aligned quadruple patterning (SAQP) processes."
 

Table from SeekingAlpha as cited above

From an ALD point of view, the FEOL and metallization up to M2 use 19 in the case of Immersion Lithography (N7) vs 10 in the case of EUV (N7+) ALD spacer-defined multiple patterning masks (SADP or SAQP). However, the bigger difference is in etch for LELE etc., where EUV N7+ uses only 2 such masks.


Friday, February 26, 2021

Tech Insights Teardown: Samsung’s D1z DRAM with EUV Lithography

Advanced and costly schemes for ArFi immersion-based multi-pattering are definitely running out of steam for leading-edge logic and EUV is continuing the march into high volume manufacturing now also for DRAM. The other day there was an announcement that SK Hynix, the world´s number two DRAM maker has signed a 5-year agreement with ASML for EUV scanners (LINK).

As a European, I must say that I like the situation that the key to continued scaling is kept in The Netherlands (ASML) and also the important key technology providers in Germany (Zeiss SMT, Trumpf) and Belgium in the form of the worlds leading research institute for scaling CMOS - imec and the EUV Resist Manufacturing & Qualification Center NV (EUV RMQC), a Joint Venture between imec and  JSR Micro NV (LINK).

Reuters: SK Hynix signs five-year deal worth $4.3 billion with ASML to secure EUV scanners


Now DRAMs from Samsung Electronics with applied EUV lithography technology for D1z DRAM in mass production have been found in the field and analyzed by Tech Insights and reported by EETimes (LINK).

According to EETimes, Samsung Electronics announced the world’s first development of both ArF-i based D1z DRAM and separately its EUV lithography (EUVL) applied D1z DRAM last year.

Tech Insights is excited that we have finally found Samsung’s new and advanced D1z DRAM devices and confirmed details of this technology.

Here just a teaser, please check out the original EETimes article or get the full report from Tech Insights (LINK).


Samsung DRAM cell design, a comparison of BLP patterns on D1z (a) without EUVL and (b) with EUVL.


Tuesday, April 30, 2019

Improving SAQP Patterning Yield using Virtual Fabrication and Advanced Process Control

Here is a noceanimation and descrioption of the Self-Aligned Quadruple Patterning (SAQP) from Coventor.
 
[Coventor] Advanced logic scaling has created some difficult technical challenges, including a requirement for highly dense patterning. Imec recently confronted this challenge, by working toward the use of Metal 2 (M2) line patterning with a 16 nm half-pitch for their 7nm node (equivalent to a 5nm foundry node). Self-Aligned Quadruple Patterning (SAQP) was investigated as an alternative path to Extreme Ultra-Violet (EUV) lithography for this line patterning application. At the 2019 SPIE Advanced Lithography conference, Coventor personnel demonstrated how virtual process modeling (combined with advanced process control) could provide enhanced patterning yield and enable SAQP patterning at this tight pitch (See Complete White Paper).
 
Source: Coventor LINK
 

Saturday, November 10, 2018

Directed self-assembly of block copolymers for 7 nanometre FinFET technology and beyond

Globalfoundries recently announced that they have dropped all plans on putting 7 nm FinFET technology in production (LINK). Presumably this means that any advanced development for 7nm and beyond patterning has been stopped as well. In any case here is an excellent publication submitted before that announcment coming from the collaborative development from some of the most advanced semiconductor development centers in the USA - IBM Research at Albany NanoTech, TEL Technology Center, America in Albany, GlobalFoundries, and IBM Research TJ Watson in Yorktown Heights and IBM Research Almaden, San Jose.



They use different versions of directed self assembly (DSA) of block co-polymers (BCP) and spacer defined double patterning. ALD is used for spacers as well as very thin ALD SiN hardmasks. All this is all done without EUV like in the Samsung 2nd Generation 7nm FinFET or self aligned quadruple patterning (SAQP) like in the Intel 10 nm FinFET) - Impressive!

Some details are given in the Supplementary info (below).

Directed self-assembly of block copolymers for 7 nanometre FinFET technology and beyond


Nature Electronics volume 1, pages562–569 (2018)

Supplementary information : LINK (OPEN)



Monday, October 29, 2018

Coventor - N7 FinFET Self-Aligned Quadruple Patterning Modeling

Coventor just released a white paper for ther modelling on FinFET Self-Aligned Quadruple Patterning for the 7nm node (N7).

You can request the paper for download here: LINK

White Paper : N7 FinFET Self-Aligned Quadruple Patterning Modeling

In this paper, we model fin pitch walk based on a process flow simulation using the Coventor SEMulator3D virtual platform. A taper angle of the fin core is introduced into the model to provide good agreement with silicon data. The impact on various Self-Aligned Quadruple Patterning process steps is assessed. Etch sensitivity to pattern density is reproduced in the model and provides insight on the effect of fin height variability.
 
 

Friday, April 27, 2018

Intel shifts high volume 10 nm shipments to 2019 due to yield issues from multi-patterning

As reported by Reuters [LINK], Intel bet the earnings expectations for the first quarter driven by the biggest-ever quarterly jump in its data centre business and small-but-steady growth in its personal computer business.However, Intel also announced that they are pushing out volume production of their 10 nm Logic process to 2019, which was most recently announced for the 2nd half of 2018. during the 1Q 2018 earnings conference calls more details were given:

[Seeking Alpha, LINK] "We continue to make progress on our 10-nanometer process. We are shipping in low volume and yields are improving, but the rate of improvement is slower than we anticipated. As a result, volume production is moving from the second half of 2018 into 2019. We understand the yield issues and have defined improvements for them, but they will take time to implement and qualify. We have leadership products on the roadmap that continue to take advantage of 14-nanometer, with Whiskey Lake for clients and Cascade Lake for the data center coming later this year.

Moore's Law is essential to our strategy and our product leadership. It continues to create significant value for Intel and our customers. While it's taking longer and costing more to deliver and yield advanced process technologies, we are able to optimize our process and products within the node to deliver meaningful performance improvements.

For example, 14-nanometer process optimizations and architectural improvements have resulted in performance gains of more than 70% since the first 14-nanometer products were launched. We combine these advances in manufacturing technology and architecture to produce truly leadership products. And it's that product leadership that ultimately matters most to our customers and end users."

Brian M. Krzanich - Intel Corp.

Earnings call slides [Seeking Alpha, LINK]

In the Q&A Mr. Krzanich elaborated on the reason behind the 10 nm push out and he explained how it is mainly due to yield issues coming from multiple patterning (SADP and SAQP):

- Intel have 10 nm product and process leadership and are shipping 10 nm products today. 
- Those are the densest, highest performing products out there.
- Intel is slowing the ramp down to fix yield issues related to patterning.
- In multi-multi-patterning (SAQP) there are six layers of patterning to produce a feature. 
- Intel understand the yield issues, which are tied to 10 nm being the last technology tied to not using EUV and the amount of multi-patterning and the effects of that on defects.


Intel’s 10 nm Platform Process was presented in detail at the IEDM 2017 (Dec 2017) “A 10nm High Performance and Low-Power CMOS Technology Featuring 3rd Generation FinFET Transistors, Self-Aligned Quad Patterning, Contact over Active Gate and Cobalt Local Interconnects” and you may study the details in this excellent article by Dick James [Solid State Technology, LINK]

Media coverage:
 
The Register
 

Saturday, November 19, 2016

Why is EUV so difficult and why should we ALD people care about that

Inspired by a recent article by Mark LaPedus, bad weather over Germany and coming back alive after a flue I had to return to my favorite ALD topic.  As I remember it EUV was scheduled for insertion at 32 nm and has been pushed node by node ever since then. 10 years ago when I worked at the DRAM company Qimonda (RIP) I was on a small double patterning team and at that time I got my first insights into this exciting topic and I have followed it ever since. I would say that for an ALD process engineer the HKMG stack became boring once it came into production at 45 nm. 32/28 nm let´s tune the HIG source 2 degrees Zzzzzzz. Just make up you´re mind - should we go first or last? As we care.... joking aside the three big ones, Applied Materials, Lam Research and Tokyo Electron, all failed taking control of the ALD HKMG business and this was rightfully so conquered by ASMI with a good help from Finnish and Korean ALD Technology at its finest (Microchemistry and Genitech). With respect to EUV and ALD Enabled Pattering PEALD has become a key factor and may explain partially why ASM has been successful also in that field.

Ever since ALD became part of the patterning/litho community it just feels like we are taken much more serious than when we were stuck mainly playing around with funky materials from the periodic table. In short, multiple patterning and EUV is just so much cooler! 

The situation now is that Samsung may start using EUV at 7 nm and the rest may wait until 5 nm. At least that is the current situation that I have from the last month of online media reports. That Samsung may be an early adopter for EUV maybe explained by that they have to also realize DRAM scaling sub 20 nm (more details in the article linked below).

In one sense skipping EUV has been a fantastic driver for double patterning and followed by quadruple patterning technologies realized by advanced etch processes and ALD liners. The single- and multiwafer ALD & PEALD equipment market and silicon precursor revenue volume has benefited enormously from this.

Self-aligned contact and via patterning is an established method for patterning multiple contacts or vias from a single lithographic feature. It makes use of the intersection of an enlarged feature resist mask and underlying trenches which are surrounded by a pre-patterned hardmask layer. This technique is used in DRAM cells and has been extended to patterning of active areas (see "Crossed self-aligned patterning"). It is also used for advanced logic to avoid multiple exposures of pitch-splitting contacts and vias [Wikipedia]
However, one thing that is difficult to realize with multiple patterning technology is hole patterns (described in the figure above) and here I don´t think about the regular den matrix used for e.g. DRAM cell arrays but the rather randomized pattern used for contact holes and BEOL vias. So even though you´re ALD biased at some point in time it could slow down scaling for interconnects and then that would also impact the ALD business.

So that is why it should be of interest for any ALD guy to closely follow and understand the EUV situation. Please find here some insights by Mark LaPedus at Semiconductor Engineering on what the EUV problem is all about and in great technical detail as well.

One of the most complex technologies ever developed is getting closer to rollout. Here’s why it took so long, and why it still isn’t a sure thing. November 17th, 2016 - By: Mark LaPedus, Semiconductor Engineering.

Also I can highly recommend the Wikipedia page on Multiple patterning which receives regular updates. 

To inspire you even more just take time to read this excellent review by W.M.M. Kessels et al on ALD enabled pattering: "The use of atomic layer deposition in advanced nanopatterning", Nanoscale, 2014,6, 10941-10960, DOI: 10.1039/C4NR01954G. There is definitely more to come and just maybe those holes can be made by ALD as well.


Thursday, October 13, 2016

University of Minnesota has developed Atomic Layer Lithography by ALD to create long narrow nano gaps

We have entered the era of atomic level processing by the introduction of atomic layer deposition (ALD), etching (ALE), cleaning (ALC) and so on in semiconductor manufacturing for advanced CMOS and Memory devices. Especially because of the delay of EUV Lithography ALD has proven to save continued device scaling by implementation in multiple patterning techniques so that scaliong can go on.

Here is yet another interesting technique where ALD is used in a sense to create extremely narrow channels with atomic precision governed by ALD - Atomic Layer Lithography.

As reported by Nanotechweb - Gold nanogap electrodes trap tiny particles

Researchers at the University of Minnesota in Minneapolis have invented a new ultralow power technique to trap nanoparticles in the sub-10 nm gaps between two gold electrodes. The technique, which overcomes many of the problems encountered in traditional dielectrophoresis experiments, could help make portable biosensors.

(a) Fabrication scheme using atomic layer lithography. An Al2O3 layer of desired thickness (that is, gap size) is deposited using ALD on a patterned gold film. A second layer of gold is evaporated, such that the first and second metal layers are not in contact. The top gold layer is then peeled off using adhesive tape, exposing the Al2O3-filled nanogap between the two gold electrodes. (b) An array of nanogap electrodes of desirable length is patterned by photolithography and ion milling on a 1 cm long nanogap. Courtesy: Nanotechweb & Nano Lett.

Nanotechweb reports that in 2011, a student (Xiaoshu Chen) figured out how to make vertically-oriented gaps as small as 1 nm over a centimeter length scale, which accordingly is not possible by any other method.

“As a result, we were able to make long and narrow gaps using atomic layer deposition (ALD), which is a robust manufacturing technique for coating ultra-thin films to construct insulating gaps in the sidewalls of patterned metals (see figure above). Thanks to the nature of ALD, we can precisely control the width of the gap, and after depositing metals on the other side of the ALD coating, nanogaps naturally form."

“What makes this atomic layer lithography technique so unique and appealing is that we can expose the nanogaps using just Scotch tape, he tells nanotechweb.org. “This was a rather surprising discovery that Chen made. Since many labs around the world have access to ALD tools (and indeed Scotch tape!), this means that other researchers could practise our technique, easily and inexpensively.” 

Full article:  Gold nanogap electrodes trap tiny particles

Thursday, September 15, 2016

GLOBALFOUNDRIES details 7nm FinFET Technology Offering

The table below was recently published on SemiWiki and today Globalfoundries announced their 7 nm time line in a press release below. Judging by the comparison TSMC is now in lead of Moore´s Law trailed by Intel, Samsung and Globalfoundries.

"The platform is based on an industry-standard FinFET transistor architecture and optical lithography, with EUV compatibility at key levels." This means that EUV may be inserted in some BEOL metallization layers and the rest of the patterning like the complete fronte end FinFET will be made by ALD multiple patterning... oh yeah and some etch and immersion lithography in between.

CompanyCurrent20162017201820192020
Global Foundries16.6nmNANA9.5nmNANA
Intel13.4nmNA9.5nmNANA6.7nm
Samsung16.6nm12.0nmNA8.4nmNANA
TSMC18.3nm11.3nm8.2nmNA5.2nmNA


Standard Node Value by Year (edited on 9/15) according to SemiWiki (LINK)



Santa Clara, Calif., September 15, 2016 – GLOBALFOUNDRIES today announced plans to deliver a new leading-edge 7nm FinFET semiconductor technology that will offer the ultimate in performance for the next era of computing applications. This technology provides more processing power for data centers, networking, premium mobile processors, and deep learning applications.



GLOBALFOUNDRIES’ new 7nm FinFET technology is expected to deliver more than twice the logic density and a 30 percent performance boost compared to today’s 16/14nm foundry FinFET offerings. The platform is based on an industry-standard FinFET transistor architecture and optical lithography, with EUV compatibility at key levels. This approach will accelerate the production ramp through significant re-use of tools and processes from the company’s 14nm FinFET technology, which is currently in volume production at its Fab 8 campus in Saratoga County, N.Y. GLOBALFOUNDRIES plans to make an additional mutli-billion dollar investment in Fab 8 to enable development and production for 7nm FinFET.

Saturday, August 13, 2016

Tokyo Electron - A spacer-on-spacer scheme for self-aligned multiple patterning and integration

Tokyo Electron showcase "A spacer-on-spacer scheme for self-aligned multiple patterning and integration" using ALD which is claimed to be a "novel, low-cost spacer-on-spacer pitch-splitting approach is targeted at sub-32nm pitch for 7nm technology nodes and beyond"

The ALD process rauns at room-temperature depositing a silicon dioxide film that is compatible with organic materials as the first spacer.

Please read the full article in SPIE News Room here.


Illustration of the proposed spacer-on-spacer SAQP integration. Depo: Deposition. Pull: Removal (of spacer). Figure form SPIE Newsroom.

Sunday, May 15, 2016

UPDATE: Imec showcase low cost Self-aligned quadruple patterning (SAQP) for sub 10nm nodes

Imec has developed a low cost Self-aligned quadruple patterning (SAQP) that meet the basic requirements for 7 and 5 nm CMOS FinFET patterning. The technology is based on 193 immersion (193i) lithography and repeated plasma ALD and etching steps as alternative to expensive high resolution EUV lihography. You can read all details SPIE Newsroom (abstract below).

UPDATE: According to information received spacers are Plasma Enhanced ALD SiO2 and the a-Si mandrel and SiN all from ASM. The etching has been performed using Lam Research chambers.

Self-aligned quadruple patterning to meet requirements for fins with high density

Efraín Altamirano-Sánchez, Zheng Tao, Anil Gunay-Demirkol, Gian Lorusso, Toby Hopf, Jean-Luc Everaert, William Clark, Vassilios Constantoudis, Daniel Sobieski, Fung Suong Ou and David Hellin

14 May 2016, SPIE Newsroom. DOI: 10.1117/2.1201604.006378 
Transmission electron microscopy (TEM) images of the stages of SAQP show, from left to right: patterning of the first core onto a mandrel; deposition of SiO2 by ALD; etching of the first spacers; etching of the mandrel to produce the second core; further deposition of SiO2by ALD; and etching of the second spacers and silicon nitride pad (14 May 2016, SPIE Newsroom. DOI: 10.1117/2.1201604.006378 ).

Repeated plasma deposition and etching steps enable the patterning of fins with the potential to meet requirements of N7 and N5 technologies for profile, depth, uniformity, and pitch walk. Over recent decades, continuous reductions in the scale of field-effect transistors in accordance with Moore's law, which states that the number of transistors in an integrated circuit doubles every two years, have enabled continuous increases in device performance and transistor density. Currently, state-of-the-art devices are based on structural elements with dimensions of 7nm or even 5nm (N7/N5). The highest-resolution patterns required for N7/N5 devices are silicon fins with a pitch of 18–28nm and metal layers with a pitch of 24–32nm. These dimensions far exceed the resolution attainable with 193 immersion (193i) lithography. Extreme UV lithography might be an alternative process for the formation of lines and spaces, but is expensive and not entirely ready for use in production.

Thursday, April 7, 2016

Samsung Starts Mass Producing Industry’s First 10-Nanometer Class DRAM

Samsung just announced that they start Mass Producing Industry’s First 10-Nanometer Class DRAM now. According to the press release (here) the key technology developments include:
  • improvements in proprietary cell design technology
  • QPT - quadruple patterning technology lithography 
  • Ultra-thin dielectric layer deposition.
The two later ones should mean a lot of ALD business for High-k, Electrodes and dielectric spacers.

Below is a DRAM Technology Roadmap published by TechInsights last summer and here you can see that Samsung is nailing it and next we should expect announcements from SK Hynix and The Micron Camp.


Here is an earlier post form IEDM 2015 in December when Samsung revieled some details - if thoose are used here is unknown so hopefully some reverse engineering study will surface next:

Samsung to present low cost manufacturing of 20 nm DRAM and beyond at IEDM2015

Some advancement in keeping low cost manufacturing of 20 nm DRAM will be presented by Samsung at IEDM 2015. Key elements are:

  • avoiding EUV lithography
  • honeycomb structure (see figure below)
  • air-spacer technology


According to Solid State Technology an air-gap spacer arrangement achieves a 34% reduction in bitline capacitance for faster operation.

20nm DRAM: A New Beginning of Another Revolution (Invited), J. Park, Y.S. Hwang, S.-W. Kim, S.Y. Han, J.S. Park, J. Kim, J. W Seo, B.S. Kim, S.H. Shin, C.H. Cho, S.W. Nam, H.S. Hong, K.P. Lee, G.Y. Jin, and E.S. Jung, Samsung Electronics Co.


For the first time, 20nm DRAM has been developed and fabricated successfully without EUV lithography using the honeycomb structure and the air-spacer technology. These low-cost and reliable schemes are promising key technologies for 20nm technology node and beyond.



Saturday, March 12, 2016

Great summary of the patterning options at 7nm

As many of you know, the insertion of multi patterning technology is driving the single wafer and multi wafer ALD equipment market enormously. The actually the market is predicted by many (Gartner, ASMi, VLSI) to double in the coming 2-3 years and many new players are entering ALD with new powerful ALD technology Lam Research, Applied Materials and Jusung Engineering have new platforms on the market targeting the multi patterning market and Veeco is developing new low temperature Fast Spatial ALD also targeting this market. Here is a collection of recent blog posts on this topic here at BALD Engineering ALD News Blog:

ASM International's CEO Chuck Del Prado on 2015 ALD results
Applied Materials to introduce a new system for Atomic Layer Deposition - Olympia™ ALD

Lam Research gets into the booming ALD business and doubles their install base 

Jusung Engineering launches SDP R2 Revolution-Rotation ALD System at SEMICON Korea
Veeco brings low temperature nitride Spatial FAST ALD to semiconductor manufacturing

From this point of view it is good to understand what the options are at 7nm where the number of multi patterning steps may be fore than a handful. Therefore a recommend you to read this article by Mark LaPedus in Semiconductor Engineering with the latest insights from SPIE 2016.

7nm Lithography Choices

Four possible scenarios for patterning the next generation of chips

March 7th, 2016 - By: Mark LaPedus
 
1. A chipmaker doesn’t insert EUV at 7nm, but rather it uses immersion/multi-patterning exclusively.
2. A chipmaker uses immersion/multi-patterning first. Then, EUV is inserted later in the flow where it makes sense.
3. A chipmaker inserts immersion/multi-patterning and EUV simultaneously.
4. A chipmaker uses an alternative technique, such as DSA and multi-beam.

Article:  http://semiengineering.com/7nm-lithography-choices/

Sunday, March 6, 2016

ASML and IMEC EUV Progress at SPIE Advanced Lithography Conference 2016

EUV is making progress and to several reports it may be ready for 7nm. Here you can find a report in SemiWiki by Scotten Jones on "ASML and IMEC EUV Progress" from the recent SPIE conference (21-25 February 2016, San Jose, USA). According to the report, ASML has made clear progress in throughput:
  • ASML has 8 NXE 3300 systems in the field running at ~55wph. 
  • ASML has shipped NXE3350B systems with ~125wph performance. 
  • The NXE3400B will ship this year and is expected to be the production workhorse running at ~145wph.

In another paper "Comparison of EUV and 193i based patterning for advanced node integration" Imec compared EUV to current ArFi or 193ilithography for three cases showing a cost comparasion resulting in a win for EUV : LE3 > SADP > EUV.

Abstract: "In this work we compare the pattering integrity results of product like structures using EUV- and 193i-Lithography. Traditional 193i based lithography requires multiple litho-etch (LE) or pitch doubling techniques to reach sub resolution pitch. These however add additional films and steps in the pattering process, and introduces CD and overly variability. EUV offers the possibility of single print for advanced nodes with a reduced process flow. However EUV introduces pattering selectivity and uniformity challenges. The process flows, complexity and pattering results will be presented for EUV single exposure, 193i multiple Litho Etch (LE3), and 193i Spacer Assisted Double Pattering (SADP+Keep)."

According to Scotten Jones the detailed comparison was for these 3 cases:
  1. The litho-etch-litho-etch-litho-etch (LE3) process prints 42nm lines with 144nm pitch and then shrinks them with a total of 27 steps. 
  2. The SADP process creates 48nm lines on a 96nm pitch and then shrinks them with a total of 18 steps. 
  3. EUV creates 24nm lines in an 8 step process. 
"In summary EUV had the best overall performance, SADP + block was second best and LE3 the worst. The biggest issue for EUV was LER and he thinks that can be improved." concluded Scotten Jones

Too read further about SPIE I asloo recommend this piece by Ed Korczynski at Solid State Technology looking at many additional papers presented at SPIE 2016:

http://semimd.com/blog/2016/03/03/many-mixes-to-match-litho-apps/

Sunday, November 29, 2015

ALD Iridium used to fabricate Ultra-high Resolution Fresnel Zone Plates

According to US Department of Energy, Zone-plate microscopes play a crucial role in various critical science areas such as energy storage, catalysis, photovoltaics, energy conversion, and unconventional oil recovery.
  • Current microscopes are limited to resolutions of 15-20 nm in the soft X-ray range and 50-70 nm in the hard X-ray range. 
  • Pushing resolutions to the 5-10 nm range will have dramatic new impacts on science and technology.

Similar to the double pattering technique used today in the semiconductor industry, scientists at Paul Scherrer Institut in Switzerland employ ALD Iridium  in high aspect ratio structures to increase the resolution of Fresenel Zone Plates beyond the limit of e-beam lithography.


FIB cross section of a line doubled iridium zone plate (Figure from Paul Scherrer Institut)

"To further increase the resolution of Fresnel zone plates beyond the limits of electron-beam lithography, we have developed a novel technique based on the coating of a template structure with a metal layer. The electron-beam written template is coated uniformly with iridium using an atomic layer deposition (ALD) process (see figure 1). As iridium has a much higher x-ray refractive index as the template, we obtain a doubling of the effective zone density and subsequent improvement of the resolution by a factor of two compared to the template structure."

Tuesday, September 8, 2015

Semiconductor Engineering about triple and quadruple patterning after 20/16/14nm [video]

David Abercrombie, advanced physical verification methodology program manager at Mentor Graphics, talks with Semiconductor Engineering about triple and quadruple patterning after 20/16/14nm.
 

Monday, July 13, 2015

Lam Research Releases High-Productivity VECTOR(R) ALD Oxide Deposition System

Lam Research Corp a major global supplier of innovative wafer fabrication equipment and services to the semiconductor industry, today announced it has released its high-productivity VECTOR® ALD Oxide system on the Extreme platform. The new product uses atomic layer deposition (ALD) to create highly conformal dielectric films with an emphasis on advanced patterning, in particular spacer-based multiple patterning. One key challenge is managing thickness variability of the self-aligned spacers that define critical dimensions (CDs). By delivering superior CD control, VECTOR ALD Oxide has been winning volume-production decisions for multi-patterning applications. Now leveraging Lam's Extreme platform, the latest system meets productivity requirements for continued scaling, where additional steps increase process time, cost, and complexity. As a result, VECTOR ALD Oxide is gaining rapid adoption by a number of leading chipmakers for advanced multi-step patterning applications.


"Multiple patterning continues to be a key inflection for the industry, and spacer-based multi-patterning remains an enabling strategy for chipmakers for both current immersion and future EUV lithography schemes," said Sesha Varadarajan, group vice president, Deposition Product Group. "With this in mind, we are working closely with our customers to deliver cost-effective, extendible solutions required for further scaling, such as the high-productivity atomic-scale control from our VECTOR ALD Oxide product."


By repeating lithography/etch/deposition steps, multiple patterning techniques create smaller features and higher feature densities compared to the capability of current optical lithography using single patterning. To enable scaling for 14 nm and below, chipmakers are adopting self-aligned schemes, including self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP), where deposition plays a critical role in forming the pattern-defining spacers. These deposition processes are challenging since they must form high-quality conformal and very uniform films. For example, a 200-300 angstrom-thick film can have only a few angstroms thickness variation across the wafer. For next-generation 10 nm processes, the manufacturing complexity will continue to increase as additional multi-patterning process steps are added, with each step contributing to overall CD variability.


Using Lam's advanced ALD capabilities, the latest VECTOR ALD Oxide system delivers the uniformity required for CD control of the ultra-thin films critical to SADP and SAQP schemes. The quad-station modules process four wafers simultaneously and share components to improve reliability and chamber matching, contributing to industry-leading wafer-to-wafer repeatability performance. The system's compact design delivers as much as 20% higher footprint productivity compared with other solutions. Process hardware has also been optimized to enable fast gas and RF switching, increasing throughput and reducing precursor usage for improved running costs. These innovative process module features combined with the high-productivity platform deliver the performance and cost-efficiency needed for manufacturing. Consequently, VECTOR ALD Oxide is winning development and production tool of record positions at leading manufacturers for advanced multi-patterning applications. This momentum is being successfully expanded to other applications, such as high-aspect ratio liners for through-silicon vias (TSVs) and image sensors.

Tuesday, March 24, 2015

LAM Research - Multiple Patterning Makes Miniaturization Possible

Here is a great blog on Multiple Patterning by LAM Research that explains it all in a straight forward way. The main technologies are pictured below - check ot the blog for details.

https://firmenportal.iaeste.at/sites/default/files/logos/492-Lam%20Research/Lam_Research_logo_color%20june.jpg
 
"Today’s advanced chip designs have smaller and more dense features than can be created using available lithography capability. Fortunately, advanced patterning techniques have been devised to work around these limitations by using multiple patterns of larger dimensions to obtain smaller and/or more tightly packed features."

(1) Convential (Single) Patterning

 
In conventional lithography, a wafer is coated with a light-sensitive material called photoresist. Light is then streamed through a photomask (a pattern of transparent and opaque areas), exposing the photoresist in some places, but not in others. The exposed regions are then etched away, while covered areas remain protected (in the case of positive photoresist). The end result is a set of features whose size and density are determined by the original photoresist pattern.

(2) Double Patterning 

 
One of the most widely adopted double patterning schemes is double exposure/double etch, also known as litho-etch-litho-etch, or LELE.

(3) The Self-Aligned Spacer Technique - Self-Aligned Double Patterning (SADP)

 

Examples of self-aligned double patterning (SADP) applications include formation of fins in FinFET technology, lines and spaces for interconnect levels, and bitline/wordline features in memory devices

(4) Multiple Patterning - Self-Aligned Quadruple Patterning (SAQP)


Self-aligned quadruple patterning (SAQP) can achieve a half-pitch resolution of ~10 nm


Check out this awesome video to understand Atomic Layer Deposition (ALD) and Atomic Layer Etching (ALE), which are two very important processes for driving nano-patterning and scaling further down to below 10 nm.


Tuesday, July 29, 2014

VIDEO : An overview on Atomic Layer Etching (ALEt) from Stanford

VIDEO : An overview on Atomic Layer Etching (ALEt)  created for Stanford Nanomanufacturing Class July 2014. Thanks Annina at ALDPulse.com for sharing this!
 
 
Screendump - explaining self aligned double pattering (SAPD) and cration of silicon fins for leading edge FinFETs.
 



 
Video on ALEt as published on Youtube.com