Saturday, November 19, 2016

Why is EUV so difficult and why should we ALD people care about that

Inspired by a recent article by Mark LaPedus, bad weather over Germany and coming back alive after a flue I had to return to my favorite ALD topic.  As I remember it EUV was scheduled for insertion at 32 nm and has been pushed node by node ever since then. 10 years ago when I worked at the DRAM company Qimonda (RIP) I was on a small double patterning team and at that time I got my first insights into this exciting topic and I have followed it ever since. I would say that for an ALD process engineer the HKMG stack became boring once it came into production at 45 nm. 32/28 nm let´s tune the HIG source 2 degrees Zzzzzzz. Just make up you´re mind - should we go first or last? As we care.... joking aside the three big ones, Applied Materials, Lam Research and Tokyo Electron, all failed taking control of the ALD HKMG business and this was rightfully so conquered by ASMI with a good help from Finnish and Korean ALD Technology at its finest (Microchemistry and Genitech). With respect to EUV and ALD Enabled Pattering PEALD has become a key factor and may explain partially why ASM has been successful also in that field.

Ever since ALD became part of the patterning/litho community it just feels like we are taken much more serious than when we were stuck mainly playing around with funky materials from the periodic table. In short, multiple patterning and EUV is just so much cooler! 

The situation now is that Samsung may start using EUV at 7 nm and the rest may wait until 5 nm. At least that is the current situation that I have from the last month of online media reports. That Samsung may be an early adopter for EUV maybe explained by that they have to also realize DRAM scaling sub 20 nm (more details in the article linked below).

In one sense skipping EUV has been a fantastic driver for double patterning and followed by quadruple patterning technologies realized by advanced etch processes and ALD liners. The single- and multiwafer ALD & PEALD equipment market and silicon precursor revenue volume has benefited enormously from this.

Self-aligned contact and via patterning is an established method for patterning multiple contacts or vias from a single lithographic feature. It makes use of the intersection of an enlarged feature resist mask and underlying trenches which are surrounded by a pre-patterned hardmask layer. This technique is used in DRAM cells and has been extended to patterning of active areas (see "Crossed self-aligned patterning"). It is also used for advanced logic to avoid multiple exposures of pitch-splitting contacts and vias [Wikipedia]
However, one thing that is difficult to realize with multiple patterning technology is hole patterns (described in the figure above) and here I don´t think about the regular den matrix used for e.g. DRAM cell arrays but the rather randomized pattern used for contact holes and BEOL vias. So even though you´re ALD biased at some point in time it could slow down scaling for interconnects and then that would also impact the ALD business.

So that is why it should be of interest for any ALD guy to closely follow and understand the EUV situation. Please find here some insights by Mark LaPedus at Semiconductor Engineering on what the EUV problem is all about and in great technical detail as well.

One of the most complex technologies ever developed is getting closer to rollout. Here’s why it took so long, and why it still isn’t a sure thing. November 17th, 2016 - By: Mark LaPedus, Semiconductor Engineering.

Also I can highly recommend the Wikipedia page on Multiple patterning which receives regular updates. 

To inspire you even more just take time to read this excellent review by W.M.M. Kessels et al on ALD enabled pattering: "The use of atomic layer deposition in advanced nanopatterning", Nanoscale, 2014,6, 10941-10960, DOI: 10.1039/C4NR01954G. There is definitely more to come and just maybe those holes can be made by ALD as well.

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