LAM Research - Multiple Patterning Makes Miniaturization Possible

Here is a great blog on Multiple Patterning by LAM Research that explains it all in a straight forward way. The main technologies are pictured below - check ot the blog for details.

 

"Today’s advanced chip designs have smaller and more dense features than can be created using available lithography capability. Fortunately, advanced patterning techniques have been devised to work around these limitations by using multiple patterns of larger dimensions to obtain smaller and/or more tightly packed features."

(1) Convential (Single) Patterning

 

In conventional lithography, a wafer is coated with a light-sensitive material called photoresist. Light is then streamed through a photomask (a pattern of transparent and opaque areas), exposing the photoresist in some places, but not in others. The exposed regions are then etched away, while covered areas remain protected (in the case of positive photoresist). The end result is a set of features whose size and density are determined by the original photoresist pattern.

(2) Double Patterning 

 

One of the most widely adopted double patterning schemes is double exposure/double etch, also known as litho-etch-litho-etch, or LELE.

(3) The Self-Aligned Spacer Technique - Self-Aligned Double Patterning (SADP)

 

Examples of self-aligned double patterning (SADP) applications include formation of fins in FinFET technology, lines and spaces for interconnect levels, and bitline/wordline features in memory devices

(4) Multiple Patterning - Self-Aligned Quadruple Patterning (SAQP)

Self-aligned quadruple patterning (SAQP) can achieve a half-pitch resolution of ~10 nm

Check out this awesome video to understand Atomic Layer Deposition (ALD) and Atomic Layer Etching (ALE), which are two very important processes for driving nano-patterning and scaling further down to below 10 nm.