Thursday, April 7, 2016

Samsung Starts Mass Producing Industry’s First 10-Nanometer Class DRAM

Samsung just announced that they start Mass Producing Industry’s First 10-Nanometer Class DRAM now. According to the press release (here) the key technology developments include:
  • improvements in proprietary cell design technology
  • QPT - quadruple patterning technology lithography 
  • Ultra-thin dielectric layer deposition.
The two later ones should mean a lot of ALD business for High-k, Electrodes and dielectric spacers.

Below is a DRAM Technology Roadmap published by TechInsights last summer and here you can see that Samsung is nailing it and next we should expect announcements from SK Hynix and The Micron Camp.


Here is an earlier post form IEDM 2015 in December when Samsung revieled some details - if thoose are used here is unknown so hopefully some reverse engineering study will surface next:

Samsung to present low cost manufacturing of 20 nm DRAM and beyond at IEDM2015

Some advancement in keeping low cost manufacturing of 20 nm DRAM will be presented by Samsung at IEDM 2015. Key elements are:

  • avoiding EUV lithography
  • honeycomb structure (see figure below)
  • air-spacer technology


According to Solid State Technology an air-gap spacer arrangement achieves a 34% reduction in bitline capacitance for faster operation.

20nm DRAM: A New Beginning of Another Revolution (Invited), J. Park, Y.S. Hwang, S.-W. Kim, S.Y. Han, J.S. Park, J. Kim, J. W Seo, B.S. Kim, S.H. Shin, C.H. Cho, S.W. Nam, H.S. Hong, K.P. Lee, G.Y. Jin, and E.S. Jung, Samsung Electronics Co.


For the first time, 20nm DRAM has been developed and fabricated successfully without EUV lithography using the honeycomb structure and the air-spacer technology. These low-cost and reliable schemes are promising key technologies for 20nm technology node and beyond.