From now on I think that it is time to start using Ångström instead of Nanometer (nm) when talking about leading edge CMOS and Memory. At SEMI:s ISS 2018 (Industry Strategy Symposium) last week Luc van den Hove, Chief Executive Officer and President of Interuniversity MicroElectronics Center (IMEC) presented their roadmap for what future Logic nodes might look like going down to 2 nm that is 20 Ångström.
Key interconnect technologies named "scaling boosters" to reach down to 2 nm may be :
- Continued scaling of self-aligned contacts
- Cobalt "Super Via" 20 nm wide
- Burried Ruthenium Rails only 10 nm wide, which seems to be a evolution of the tungsten burried Word Lines and Bitlines introduced by Qimonda for DRAM (65nm in 2009) except offcourse these rails are burried in a dielectric which will make it stackable.
Imec Logic roadmap and technologies, Picture from Twitter (LINK)
Besides the interconnect technologies the presentation showed evolution from FinFETs to nanowire FETs and Imecs latest technology development in 300 mm wafer processing technology:
- Introduction of triple pattering (Much More ALD!)
- EUV Litography and the introduction Carbon Nano Tube CNT Pellicle for EUV mask protection
- Smoothening technology in patterning like Atomic Layer Etching for improving the local critical dimension uniformity (LCDU) down from 2.7 to 1.4 nm
In the case of memory technology Imec now focuses on 4 non-volatile types of memory cells besides DRAM and 3DNAND Flash:
- STTRAM - spin transfer torque magnetoresistive random-access memory
- RRAM - resistive random-access memory
- FeRAM - ferroelectric random-access memory (should be renamed DD-RAM for Dresden)
- SOTRAM - Spin Orbit Torque random-access memory
Luc Van den hove to Receive SEMI Sales and Marketing Excellence Award 👍 https://t.co/ZLjNa1xB21 @SEMIexpos #ISS2018 pic.twitter.com/ula0Oiucdh— imec (@imec_int) January 15, 2018