3D Ferroelectric NAND for Ultra-High Efficiency Analog Computing-in-Memory by SK hynix

3D FeNAND with Ultra-High Computing-in-Memory Efficiency: AI models containing up to trillions of parameters require substantial memory resources to handle the vast amounts of data. Energy-efficient analog computing-in-memory (CIM) devices such as 3D vertical NAND architectures are emerging as potential solutions because they offer high areal density and are non-volatile. SK hynix researchers will detail how they achieved analog computation in ultra-high-density 3D vertical ferroelectric NAND (FeNAND) devices for the first time. They used gate stack engineering techniques to improve the analog switching properties of 3D FeNAND cells, and achieved an unprecedented ≥256-conductance-weight levels/cell. The 3D FeNAND arrays improved analog CIM density by 4,000x versus 2D arrays, and demonstrated stable multiply-accumulate (MAC) operations with high accuracy (87.8%) and 1,000x higher computing efficiency (TOPS/mm²) versus 2D arrays. This work provides an efficient method to implement the processing of hyperscale AI models in analog CIM chips for edge computing applications, where speed and low power operation are the critical requirements, not extreme accuracy.

 

Above:

(1)   is a comparison of 2D and 3D arrays for analog-CIM applications.

(2)   is a TEM analysis  of the 3D FeNAND, showing (a) a top-down view of the device; (b) a cross-sectional view at low magnification; (c) a cross-sectional view at high magnification; and (d) a schematic illustration of the FeFET cells in the 3D FeNAND array.

Source: 

IEDM 2024 Paper #38.1, “Analog Computation in Ultra-High Density 3D FeNAND for TB-Level Hyperscale AI Models,” J.-G. Lee and W.-T. Koo et all, SK hynix https://www.ieee-iedm.org/press-kit

4F² DRAM developed by a Kioxia using ALD IGZO

The new 4F² DRAM developed by a Kioxia-led team combines gate-all-around (GAA) IGZO (indium-gallium-zinc oxide) vertical channel transistors (VCTs) with a unique design that places transistors above high-aspect-ratio capacitors to reduce thermal stress and suppress electrical interference like "row hammer." This structure increases memory density and efficiency, providing a high on/off current ratio essential for low-power operation. The team demonstrated a 275Mbit array with this technology, indicating its potential to enable high-density, low-power DRAM for advanced computing applications.

Kioxia is traditionally known for its expertise in NAND flash memory rather than DRAM. They are one of the leading companies in the NAND space, focusing primarily on storage solutions. However, this new venture into DRAM with innovative 4F² cell structures signals an expansion of their research and development scope, possibly to leverage their materials and process expertise in a closely related area. It suggests Kioxia may be exploring ways to diversify its technology portfolio, potentially addressing high-density memory needs beyond traditional NAND storage

ALD offers atomic-level precision and is beneficial for creating uniform, conformal layers of IGZO in complex, high-aspect-ratio surfaces demonstrated here, which is particularly advantageous in advanced semiconductor applications. ALD works by exposing the substrate to alternating pulses of indium, gallium, and zinc precursors, separated by purges to prevent unwanted reactions. This controlled process achieves a smooth and consistent IGZO layer with excellent thickness control, crucial for sensitive electronic applications like DRAM devices.

New Type of 4F² DRAM: DRAM is the workhorse memory of electronic systems, but patterning the extremely small features of conventional silicon 6F² DRAM memory cells and suppressing “row hammer” electrical interference from nearby cells are major challenges. To overcome them, the industry has been actively developing denser 4F² DRAM designs made with different materials. A Kioxia-led team will describe a new type of 4F² DRAM, comprising GAA IGZO (indium-gallium-zinc oxide) vertical channel transistors (VCTs) and a new integration scheme, where the heat-sensitive transistors are placed on the top of high aspect-ratio capacitors instead of on the bottom, to reduce the thermal impact from BEOL processing below. The vertical architecture also fully suppresses row hammer interference, because the active region isn’t shared with adjacent cells. The InGaZnO VCT achieved more than 15µA/cell ON current and 1aA/cell OFF current. The researchers demonstrated the technology by successfully building a 275Mbit array with it, demonstrating its potential for future high-density, low-power DRAM technologies.

 

Above:

(a)   is a schematic of the oxide-semiconductor channel transistor DRAM. The InGaZnO VCT was integrated on a capacitor array, a different architectural scheme from silicon-based 4F2 DRAM devices.

(b)   is a cross-sectional TEM image of the InGaZnO VCT test structure, with the key technologies needed for DRAM applications described on the right nearby. The gate oxide and InGaZnO were formed in a 26nm-diameter vertical hole.

(c)   is a cross-sectional TEM showing the InGaZnO VCTs on high-aspect-ratio capacitors.

 Source:

IEDM2024 Paper #6.1, “Oxide-Semiconductor Channel Transistor DRAM (OCTRAM) with 4F² Architecture,” S. Fujii et al, Kioxia Corp./Nanya Technology Corp. https://www.ieee-iedm.org/press-kit

Intel's Breakthrough in RibbonFET Transistor Scaling Demonstrates Silicon Viability for Future Nodes

For the latest insights from the 2024 IEEE International Electron Devices Meeting (IEDM), including groundbreaking advancements in 2nm CMOS logic, extremely scaled transistors, monolithic CFET inverters, energy-efficient 3D computing-in-memory, and novel device technologies, you can explore the full press kit here.

Extremely Scaled Transistors from Intel: Intel researchers will show that silicon can continue to support the extreme gate length scaling which future technology nodes require. They will describe how they built RibbonFET CMOS transistors (Intel’s version of nanosheets) with 6nm gate lengths at 45nm contacted poly pitch (CPP, the spacing between adjacent transistor gates), with no degradation of electron mobility (how fast electrons can move through a material). The researchers will show that electron mobility doesn’t degrade until 3nm Tsi (silicon thickness), below which electron scattering due to surface roughness becomes an issue. They will describe how they achieved good short channel control (≤100mV/V at <4nm Tsi), with extremely low threshold voltage at these gate lengths through clever workfunction engineering. The work shows that 3nm is a practical scaling limit for RibbonFETs.

The image illustrates the behavior of drain-induced barrier lowering (DIBL) vs. silicon thickness (Tsi) at LG=18nm. It shows a reduction as Tsi is scaled from 10nm to 1.5nm; however, DIBL reduction saturates at Tsi <4nm, below which very little gain is obtained. PMOS DIBL is elevated vs. NMOS DIBL at the same Tsi. Also shown are TEM micrographs of a 1NR transistor with various Tsi values down to 1.5nm.

The series of images are (a) TEM micrograph and EDX scan of a completed 6nm RibbonFET device on a 1NR vehicle, showing a disconnected subfin; (b - d) are high-resolution cross-section TEMs for Tsi=5.5nm, 3.1nm and 1.7nm respectively, at 6nm gate length on a 1NR vehicle

Sources:

IEDM 2024 Press Kit Paper #2.2, “Silicon RibbonFET CMOS at 6nm Gate Length,” A. Agrawal et al, Intel https://www.ieee-iedm.org/press-kit

TSMC 2nm Platform Technology Featuring Energy-Efficient Nanosheet Transistors and Interconnects

TSMC’s New, Industry-Leading 2nm CMOS Logic Platform: In a late-news paper, TSMC researchers will unveil the world’s most advanced logic technology. It is the company’s forthcoming 2nm CMOS (i.e., N2), platform, designed for energy-efficient computing in AI, mobile, and HPC applications. It offers a 15% speed gain (or 30% power reduction) at >1.15x chip density versus the most advanced logic technology currently in production, TSMC’s own 3nm CMOS (N3) platform, introduced in late 2022.

The new N2 platform features GAA nanosheet transistors; middle-/back-end-of-line interconnects with the densest SRAM macro ever reported (~38Mb/mm²); and a holistic, system-technology co-optimized (STCO) architecture offering great design flexibility. That architecture includes a scalable copper-based redistribution layer and a flat passivation layer (for better performance, robust CPI, and seamless 3D integration); and through-silicon vias, or TSVs (for power/signal with F2F/F2B stacking). The researchers say the N2 platform is currently in risk production and scheduled for mass production in 2H’ 25. N2P (5% speed enhanced version of N2) targets to complete qualification in 2025 and mass production in 2026.

The cross-sectional image shows that the N2 platform’s Cu redistribution layer (RDL) and passivation provide seamless integration with 3D technologies.

Graph showing that the new N2 high-density cells gain 14~15% speed@power vs. N3E FinFlex 2-1 fin cells across the Vdd range; a 35% power savings at higher voltage; and a 24% power savings at lower voltage

The graph above compares two CMOS technology nodes, TSMC's N3E and N2, specifically for Arm's A715 core. N3E FinFlex (2-1 Fin) architecture, represented by the blue dotted line, operates at higher power but achieves higher speed than previous nodes. Operating at voltages between 0.5V and 0.9V, the N3E design can achieve significant performance levels but comes with a power increase. Now, N2 NanoFlex HD (High-Density) Energy-Efficient Cells as in the The N2 node, marked by the green dotted line, introduces "NanoFlex" cells that are optimized for energy efficiency. Compared to N3E, it achieves similar speeds but with substantially lower power consumption, marking a shift toward lower power designs in advanced nodes.

Key Improvements:

• When shifting from 0.6V to 0.55V in the N3E architecture, there's a 15% reduction in speed but a 24% reduction in power.
• For N2, at 0.85V, there's a 14% reduction in speed and a 35% reduction in power compared to similar performance points in N3E.
• These efficiency improvements are essential for high-performance applications in power-sensitive environments.

In summary, TSMC's N3E focuses on performance with FinFlex technology, while N2's NanoFlex HD cells target power efficiency, marking a clear trend in CMOS architecture evolution for balancing power and speed.

For the latest insights from the 2024 IEEE International Electron Devices Meeting (IEDM), including groundbreaking advancements in 2nm CMOS logic, extremely scaled transistors, monolithic CFET inverters, energy-efficient 3D computing-in-memory, and novel device technologies, you can explore the full press kit here.

Sources: 

IEDM Press kit Paper #2.1, “2nm Platform Technology Featuring Energy-Efficient Nanosheet Transistors and Interconnects Co-Optimized with 3DIC for AI, HPC and Mobile SoC Applications,” G. Yeap et al, TSMC https://www.ieee-iedm.org/press-kit

GM Ventures Invests $10 Million in Forge Nano to Boost EV Battery Technology with Atomic Armor

GM Ventures, the venture arm of General Motors, recently invested $10 million in Forge Nano, a materials science company known for its advanced battery technology. Forge Nano specializes in Atomic Layer Deposition (ALD), particularly its "Atomic Armor" technology, which enhances battery materials by applying ultra-thin coatings. This innovation improves the performance, lifespan, and charging speed of electric vehicle (EV) batteries. 

“GM Ventures’ primary goal is to bring disruptive technology into the GM ecosystem to improve products and processes,” said Anirvan Coomer, managing director of GM Ventures. “Forge Nano’s Atomic Armor technology has game-changing potential for our battery materials at significant scale. They have already demonstrated the ability to expand cathode capabilities, which is the most expensive battery cell component. This could unlock benefits for customers and the business.”

The investment is part of GM's broader strategy to secure a robust supply chain for its EVs, and the partnership will focus on optimizing battery cathode materials to improve energy density and reduce costs. With this funding, Forge Nano aims to expand its battery coating operations and develop lithium-ion battery prototypes at its Colorado facility. This collaboration is expected to boost the range and fast-charging capabilities of GM’s future EV batteries.

About Forge Nano:

Forge Nano is a materials science company specializing in advanced surface engineering technology, particularly Atomic Layer Deposition (ALD). Its proprietary technology, "Atomic Armor," applies ultra-thin coatings at the atomic scale to improve the performance and durability of materials, particularly for energy storage applications like electric vehicle (EV) batteries. Forge Nano's coatings help enhance battery life, efficiency, and fast-charging capabilities by preventing corrosion and boosting cathode material performance.

Founded in Colorado, Forge Nano has attracted significant investment from major corporations, including General Motors, Volkswagen, LG, and others. The company's solutions extend beyond the automotive industry, targeting sectors such as electronics, aerospace, and defense. With ongoing innovation, Forge Nano aims to revolutionize how materials perform in critical technologies such as semiconductors and batteries.

Sources: 

www.forgenano.com

Forge Nano Receives $10M Investment from GM Ventures to Pursue GM Battery Material Enhancements for Future Electric Vehicles - Forge Nano

ASM launches 200 mm PE2O8 silicon carbide epitaxy system

ASM has launched the PE2O8, a silicon carbide (SiC) epitaxy system designed to enhance power device production with improved yields and reduced costs. The PE2O8 targets key applications in electric vehicles, green energy, and AI data centers, addressing the need for chips with higher power performance in smaller form factors. Its dual-chamber design enables high throughput, process uniformity, and efficient maintenance, while supporting both 6" and 8" wafer processing. With advanced thermal control and recipe transfer capabilities, the PE2O8 system offers high reliability, making it ideal for SiC epitaxy on bare wafers and during chip fabrication.

ASM's PE2O8 is a high-productivity epitaxy system designed for silicon carbide (SiC) applications, enabling the production of power devices with higher yields and lower costs. It plays a crucial role in industries like electric vehicles, green energy, and AI data centers, where chips must meet high power specifications within smaller form factors. The PE2O8 system features dual reactors for easy chamber maintenance, cross-flow hot wall reactors for precise thermal control, and inductive heating for processing 6" and 8" wafers. It ensures process uniformity and recipe transfer from earlier platforms, making it highly reliable and cost-efficient for SiC epitaxy on bare wafers and in power device fabrication.

Raleigh, NC, USA, September 30, 2024 / New system extends ASM’s portfolio of industry benchmark single wafer silicon carbide epitaxy systems, the 6” PE1O6 and 8” PE1O8 systems, with a higher throughput, lower cost of ownership, dual chamber, single wafer, 6” and 8” compatible, silicon carbide epitaxy system.

Today at the 2024 International Conference on Silicon Carbide and Related Materials, ASM International N.V. (Euronext Amsterdam: ASM) introduced the PE2O8 silicon carbide epitaxy system, a new, dual chamber, platform for silicon carbide (SiC) epitaxy (Epi). Designed to address the needs of the advanced SiC power device segment, the PE2O8 is the benchmark epitaxy system for low defectivity, high process uniformity, all with higher throughput and low cost of ownership needed to enable broader adoption of SiC devices.

As the general electrification trend drives more power device manufacturers to utilize SiC for a growing number of high-power applications (such as for electric vehicles, green power, and advanced data centers) the expanded demand and requirements for lower cost for SiC is causing a transition from 6” to 8” SiC substrates. At the same time, SiC device manufacturers are designing higher power devices that will benefit from better SiC epitaxy.

Utilizing a unique design, the dual chamber PE2O8 system deposits SiC with ultra precise control, enabling benchmark higher yield and higher throughput. The highly compact, dual chamber design enables high productivity and low total costs of operation. Additionally, the system features an easy preventive maintenance approach helping to increase uptime and reduce the occurrence of unscheduled downtime. System deliveries have been ongoing to multiple customers globally, among them leaders in SiC power device manufacturing.

“We are at a critical inflection for silicon carbide power products, as our customers transition from 6” to 8” wafers”, said Steven Reiter, Corporate Vice President, and business unit head of Plasma and Epi at ASM. “Delivering a high-quality epitaxy process on larger wafers with defectivity control is critical, and we have been the industry benchmark for process uniformity with our novel chamber design. We have now extended our system capability to improve our process control and our value for customers with lower cost of ownership.”

Since 2022, ASM, through its new SiC Epi product unit has been developing and refining its single wafer SiC epitaxy system. With the structurally higher demand for electric vehicles and improvement of the overall SiC wafer and device yield, the equipment market for SiC epitaxy has grown substantially in recent years.

About ASM International

ASM International N.V., headquartered in Almere, the Netherlands, and its subsidiaries design and manufacture equipment and process solutions to produce semiconductor devices for wafer processing, and have facilities in the United States, Europe, and Asia. ASM International's common stock trades on the Euronext Amsterdam Stock Exchange (symbol: ASM). For more information, visit ASM's website at www.asm.com.

Sources:

PE2O8 SiC epitaxy | ASM

Smoltek and SparkNano Unveil Breakthrough ALD Technology to Slash Iridium Usage in Green Hydrogen Production by 95%

Smoltek Nanotech Holding AB ("Smoltek") and Dutch ALD coating company SparkNano have collaborated to develop a breakthrough technology that drastically reduces the consumption of iridium in PEM electrolyzers by 95%. By applying SparkNano's Atomic Layer Deposition (ALD) technology to coat Smoltek's carbon nanofibers with ultra-thin layers of precious metals like iridium and platinum, the companies improve catalytic efficiency and stability while significantly lowering the cost of green hydrogen production. The collaboration was highlighted in a white paper and joint webinar on September 25, 2024, where Smoltek's Head of R&D, Fabian Wenger, discussed the potential of this technology to accelerate large-scale green hydrogen production.

Press Release: Smoltek Nanotech Holding AB (publ) ("Smoltek" or the "company") announces that the group company Smoltek Hydrogen, together with the Dutch ALD coating company SparkNano, publishes a white paper and holds a joint webinar on the synergies that the two companies' technology creates. By covering Smoltek's carbon nanofibers with an extremely thin and conformal coating of precious metals, the consumption of iridium in an electrolyzer cell can be reduced by 95 percent. Fabian Wenger, Head of R&D at Smoltek Hydrogen, will participate in a joint webinar on September 25 to discuss the collaboration, the technology and its potential for large-scale green hydrogen production.

Smoltek Hydrogen's unique innovation – a porous transport electrode designed for the anode in PEM electrolyzers – solves one of the biggest technical challenges in the green hydrogen industry: the high cost and limited availability of iridium, used as catalysts in PEM electrolysis. Together with SparkNano's advanced ALD coating technology, for platinum and iridium, a dramatic reduction of precious metals is enabled while maintaining performance and stability.

“With our carbon nanofibers and their ALD coating technology, we can together lower costs and reduce the use of rare precious metals and make green hydrogen available on a large scale”, says Fabian Wenger, Head of R&D at Smoltek Hydrogen.

Revolutionizing reduction of iridium usage

With the ALD (Atomic Layer Deposition) coating technology, platinum is spread extremely evenly over Smoltek's carbon nanofibers, which provides conformal corrosion protection and protects the carbon nanofibers, which are then coated with an ultra-thin layer of iridium.

This enables the consumption of iridium to be reduced by up to 40 times compared to conventional coating methods. The combination of Smoltek's nanofibers and SparkNano's ALD technology also enables more efficient electron transfer pathways, increasing the overall catalytic activity of the electrolyzer cell. The ALD technology also improves the stability of the catalyst, which is a big step forward for the sustainability of green hydrogen technology.

A solution for large-scale production of green hydrogen

Smoltek Hydrogen's innovative nanomaterials have been shown in long-term studies to work very well in PEM electrolyzers. Fraunhofer ISE, a leading German research institute, has already identified in October 2021 that iridium coatings below 0.4 mg/cm² are a must for large-scale production of PEM electrolyzers. This technology can thus pave the way for a faster expansion of green hydrogen production, which is crucial for the transition to fossil-free industrial processes.

“SparkNano is a Dutch company, partly owned by the French gas company Air Liquide. SparkNano's spatial ALD technology enables precise coatings of super-thin material films at higher speeds than older ALD technologies, which is a big advantage now that we start scaling up to larger volumes”, says Ellinor Ehrnberg, CEO of Smoltek Hydrogen

Presentation of the Technical note: Revolutionizing PEM electrolysis

What: SparkNano and Smoltek webinar, about 30 minutes

Where: Online, link to webinar: www.spark-nano.com/webinars

Date: 25 September 2024

Time: 08:30–09:00 (occasion 1) or 14:30–15:00 (occasion 2)

For further information:

Ellinor Ehrnberg, President Smoltek Hydrogen AB

Email: ellinor.ehrnberg@smoltek.com

Telephone: +46 317 01 03 05

Website: www.smoltek.com/investors

Smoltek develops new products with disruptive performance, based on nanotechnology, which solve advanced material engineering challenges in several industrial sectors. Today, the company operates in two business areas: semiconductors and hydrogen. Smoltek protects its unique carbon nanotechnology through an extensive patent portfolio consisting of more than 110 applied for patents, of which 91 are currently granted. The company's share is listed on the Spotlight Stock Market under the short name SMOL. Smoltek is a development company and forward-looking statements regarding time to market, production volume and price levels are to be interpreted as forecasts and not commitments.

Technological Innovations in Semiconductor Manufacturing: Insights from Tokyo Electron's 2024 Integrated Report

This summary, based on Tokyo Electron's Integrated Report 2024, provides insights into the future outlook of the Wafer Fab Equipment (WFE) market, with a particular focus on the technological advancements driving demand for advanced etch and deposition processes, including the transition to next-generation semiconductor architectures like GAAFET (Gate-All-Around Field-Effect Transistor). As the industry evolves, these technologies are becoming increasingly critical to maintaining the pace of innovation and ensuring the continued scaling of semiconductor devices.

The Wafer Fab Equipment (WFE) market is set for significant growth, driven by several key factors: the rising demand for semiconductors fueled by advanced technologies like AI, IoT, 5G, and autonomous vehicles; the ongoing transition to more advanced process nodes, which requires increasingly complex and precise equipment, particularly in etching, deposition, and lithography; substantial investments in new semiconductor fabs globally, expected to boost WFE demand as these facilities come online between 2022 and 2026; and the emergence of new semiconductor architectures like 3D NAND, DRAM, and GAAFET, which necessitate leading-edge WFE to manage the heightened complexity of these manufacturing processes.

According to Tokyo Electron (TEL), the future outlook of the Wafer Fab Equipment (WFE) market is poised for substantial growth, largely driven by the rapid technological advancements in the semiconductor industry. The escalating complexity of semiconductor devices, particularly in the areas of 3D NAND, DRAM, and advanced logic devices, is creating an increasing demand for sophisticated etch and deposition technologies, such as Atomic Layer Deposition (ALD). These technologies are critical for enabling the high precision and performance required in modern semiconductor manufacturing.

For 3D NAND, the trend towards higher layer counts—potentially reaching 500 to 1,000 layers—necessitates advanced etching processes capable of creating deep holes and trenches with high aspect ratios. This is essential for maintaining structural integrity while maximizing storage density. Similarly, ALD is becoming increasingly important in the deposition of conformal films over these intricate 3D structures, ensuring uniformity at the atomic level, which is crucial for device performance and reliability.

DRAM technology is also evolving, with the shift towards 3D DRAM structures demanding new solutions in both etching and deposition. As memory cells are stacked vertically, the need for precise etch processes to define these high aspect ratio structures becomes critical. Concurrently, ALD plays a vital role in creating ultra-thin films that can meet the stringent requirements of these new architectures, enabling the continued scaling of DRAM technology.

The transition to GAAFET (Gate-All-Around Field-Effect Transistor) structures marks a significant evolution in semiconductor technology, necessitating highly advanced etch processes. These processes must achieve extreme precision in defining the narrow, high aspect ratio features characteristic of GAAFETs, ensuring device integrity and performance as scaling continues. The integration of etch with ALD is particularly crucial, allowing for the precise control of gate structures at an atomic level, which is essential for optimizing device characteristics. Additionally, the co-optimization of etching with high-NA EUV lithography ensures that the finest features can be accurately patterned and etched, supporting the successful scaling of next-generation devices. As semiconductor architectures become more complex, the role of advanced etch technologies will be pivotal in enabling the high performance and reliability demanded by GAAFET and beyond.

Furthermore, the industry’s focus on sustainability is driving demand for WFE that not only enhances performance but also reduces environmental impact. Technologies like ALD and advanced etch processes are being developed with an eye towards lowering power consumption and minimizing CO2 emissions, aligning with broader goals of achieving net-zero emissions in semiconductor manufacturing.

Overall, the WFE market is expected to see robust growth, underpinned by the critical role of etch and deposition technologies in advancing semiconductor innovation. These technologies are not only essential for maintaining the pace of Moore’s Law but also for enabling new device architectures that will define the future of the semiconductor industry. With significant investments in R&D and a strategic focus on early-stage technology development, the WFE market is well-positioned to meet the evolving needs of semiconductor manufacturers.

Source: Integrated Report/Annual Report | Investor Relations | Tokyo Electron Ltd. (tel.com)

Material Export Restrictions Poised to Strain Semiconductors

San Diego, CA, September 12, 2024: TECHCET— the electronic materials advisory firm providing supply-chain and market trend analysis – has identified a potential strain on US semiconductor manufacturing capability as Chinese export restrictions on key materials have been announced. Most recently, China announced restrictions of antimony, a key mineral required for chips used in defense equipment. This follows a series of other export controls enacted by China in 2023, most notably on graphite, germanium, gallium, and other rare earths.

These materials have all been identified as critical inputs for chips required in the US defense and the semiconductor industry. Despite growing demand for these materials, most are still primarily produced overseas and imported into the US. For example, most of the domestic antimony demand is imported from outside global sources, with 63% coming from China. Similarly for other materials falling under these export controls, “the US relies strongly on imports, ranging from >50% for germanium and >95% for rare earth elements,” stated Michel Walden, Sr. Director at TECHCET, “while the country is completely reliant on gallium imports.” The US is dependent on China for the majority of these imports.

TECHCET is actively monitoring the impacts of these export controls and other geopolitical factors on the global semiconductor supply chain. As of now, the effects have yet to be fully comprehended, but they are obviously of significant concern. Additionally, wafer starts for semiconductor device production are expected to continue rising at a compound annual growth rate (CAGR) of 5% from 2023 – 2028, requiring increased material production. Without a reliable supply of these and other vital materials, the industry will see shortages and likely experience logistic complications.

TECHCET specializes in market research information for the semiconductor materials supply chain. For more information, contact us or visit https://techcet.com/

Want to receive more market updates? Sign up for our mailing list here: https://techcet.com/mailing-list/

ABOUT TECHCET: TECHCET CA LLC is an advisory services firm expert in market and supply-chain analysis of electronic materials for the semiconductor, display, solar/PV, and LED industries. TECHCET offers consulting, subscription service, and reports, including the Critical Materials Council (CMC) of semiconductor fabricators and Data Subscription Service (DSS). For additional information, please email us here, call +1-480-332-8336, or go to www.techcet.com.

AlixLabs Qualifies APS™ for Use In 300-millimeter Silicon Wafer Designs

Swedish semiconductor startup clears technical hurdle for leading-edge process use on 300 mm wafer design*.

Scanning electron microscopy (SEM) images of amorphous silicon lines before (top) and after the APSTM process: nominal 40 nm line width and 40 nm half-pitch converted to lines with width below 15 nm and a half-pitch of 20 nm. Bild: Alixlabs

Stockholm, Sweden – September 12th, 2024 – AlixLabs AB, a Swedish semiconductor startup specializing in Atomic Layer Etching (ALE), announces that it has qualified its APS™ (ALE Pitch Splitting) process on a 300-millimeter silicon wafer design, marking one of its final steps towards commercial adoption. APS™ provides atomic-scale precision and pattern fidelity with critical dimensions below 15 nanometers for both single crystalline and amorphous silicon.

AlixLabs APS™ is designed to reduce the cost of leading-edge manufacturing, sub-7-nanometer, where feature sizes of less than 20 nanometers are required. An estimated cost saving of up to 40 percent per mask layer can be achieved with APS™ rather than relying on EUV lithography, and complex self-aligned multi patterning schemes.

AlixLabs' patented and wordmarked APS™ IP – short for Atomic Layer Etch (ALE) Pitch Splitting, here demonstrated in a simple animation.

“Proving that APS™ works on lithography designs on 300-millimeter wafers, is what we’ve all worked on since we founded AlixLabs in 2019,” says CEO and co-founder Dr. Jonas Sundqvist. “Not only do we aim to provide chip manufacturers wafer processing equipment that can create 20-nanometer half-pitch lines and critical dimension below 15 nanometers on silicon, we aim to do that at a lower cost and a more sustainable way than other technologies”

“We are also able to provide record breaking 3-nanometer critical dimension features on gallium phosphide (GaP) wafers today showing that APS™ can scale far into the future beyond what is needed today,” adds CTO and co-founder Dmitry Suyatin.

APS™ is positioned as an alternative to self-aligned double and quadruple patterning (SADP and SAQP). It allows for splitting dense line structures that can act as a foundation for transfer-etch into various materials such as dielectrics, metals, metal nitrides, and high-k dielectrics. The structures created with APS™ can also be used as-is for critical device features such as the fins in FinFET-type transistors due to extremely low surface damage.

AlixLabs’ goal is to supply leading semiconductor manufacturers, in both logic and memory segments. By enabling them to simplify and speed up their chip production at least fourfold for each critical mask layer by replacing four plasma wafer processing chambers in the SADP process flow with one APS™ chamber and eightfold correspondingly in SAQP. Finally, AlixLabs contributes overall to more sustainable semiconductor manufacturing.

*EBL patterned 300 mm wafers were provided by Fraunhofer IPMS Center Nanoelectronic Technologies (CNT) and financed by Ascent+ European Union's Horizon 2020 research and innovation program under GA No 871130.

Sources:

www.alixlabs.com

New Export Controls on ALD, ALE and ASD Technologies Effective September 2024 to Safeguard National Security

The US Bureau of Industry and Security (BIS) is introducing* stringent export controls targeting advanced technologies essential to national security, particularly within the semiconductor, quantum computing, and additive manufacturing sectors. These controls include new and revised Export Control Classification Numbers (ECCNs) and specific restrictions on critical equipment and materials, such as those involved in Gate-All-Around Field-Effect Transistor (GAAFET) technology, Atomic Layer Etching (ALE), and Atomic Layer Deposition (ALD). The controls aim to safeguard U.S. technological leadership while harmonizing with international export control standards. Specific restrictions apply to high-precision wafer processing equipment and isotopically enriched materials used in quantum computing, reflecting the critical importance of these technologies. These measures ensure that while international collaboration continues, sensitive technologies remain protected under national security protocols.

BIS has introduced new export controls focused on advanced technologies, particularly in the semiconductor, quantum computing, and additive manufacturing sectors. These controls include new Export Control Classification Numbers (ECCNs), revisions to existing ones, and the addition of new license exceptions for countries with similar technical controls. This rule aims to protect national security and advance foreign policy objectives by aligning U.S. export controls with those of international partners. The controls cover a wide range of items, including quantum computing technologies and semiconductor manufacturing equipment, reflecting the critical importance of these technologies to national security. The rule is effective immediately, though there are delayed compliance dates for certain items, allowing businesses time to adjust to the new requirements.

BIS has also established a framework to differentiate between items controlled multilaterally and those controlled through Implemented Export Controls (IEC), which are harmonized with international partners. The new regulations include provisions for annual reporting, particularly concerning the deemed export of quantum technology and software, highlighting the global nature of innovation in these fields. The rule is designed to support U.S. technology leadership while ensuring that export controls do not impede international collaboration, particularly in areas like quantum computing, where global expertise is crucial. Comments on the rule and its potential impact on supply chains and compliance programs are invited, with a focus on refining the scope and clarity of the new ECCNs and license exceptions.

BIS specifies that the restrictions on GAAFET (Gate-All-Around Field-Effect Transistor) technology primarily focus on the "technology" required for the "development" or "production" of GAAFET structures. This includes process recipes and other detailed specifications necessary for fabricating these advanced semiconductor devices. These restrictions are captured under ECCN 3E905, which applies to the "technology" for GAAFETs but does not extend to vertical GAAFET architectures used in 3D NAND. The export, reexport, or transfer of this technology to certain countries requires a license due to its national security and regional stability implications. However, the rules include specific exceptions for existing collaborations and provisions for continued access under certain conditions.

The specific wafer processing technologies restricted for export include:

Dry Etching Equipment:

Equipment designed for isotropic dry etching, as well as anisotropic etching of dielectric materials. These include technologies that enable the fabrication of high aspect ratio features, with aspect ratios greater than 30:1 and a lateral dimension on the top surface of less than 100 nn.  

The specific restrictions on Atomic Layer Etching (ALE) equipment are detailed under the export control regulations. The BIS has imposed controls on equipment designed or modified for anisotropic dry etching, which includes certain types of ALE equipment. These tools, particularly those using RF pulse-excited plasma, pulsed duty cycle excited plasma, and other advanced techniques, are now restricted due to their critical role in the precise fabrication of high-performance semiconductor devices. The restrictions apply to ALE equipment that is capable of producing high aspect ratio features, which are essential for advanced semiconductor manufacturing, making these tools subject to national security and regional stability controls .

Deposition Technologies:

Equipment designed for the selective bottom-up chemical vapor deposition (CVD) of tungsten fill metal, and other deposition processes such as those for tungsten nitride, tungsten, and cobalt layers. This also includes atomic layer deposition (ALD) equipment designed for area selective deposition of barriers or liners.

The restrictions on Atomic Layer Deposition (ALD) equipment are focused on several key types of equipment essential for advanced semiconductor manufacturing. Specifically, ALD equipment designed for area-selective deposition of barriers or liners using organometallic compounds is controlled. This includes equipment capable of area-selective deposition (ASD) that enables fill metal contact to an underlying electrical conductor without a barrier layer at the fill metal via interface to the conductor. Additionally, ALD equipment designed for depositing tungsten (W) to fill interconnects or channels less than 40 nm wide is also restricted. These restrictions are imposed due to the critical role these technologies play in the precision required for the fabrication of next-generation semiconductor devices.

These technologies are controlled under ECCNs (Export Control Classification Numbers) such as 3B001 and related classifications, and are subject to national security (NS) and regional stability (RS) controls.

The specific materials, chemicals, or precursors that are being restricted under the new export controls include:

These restrictions reflect the importance of controlling advanced materials that play a crucial role in emerging technologies, particularly those with significant national security implications, i.e., quantum technologies.

Epitaxial Materials: This includes materials with at least one epitaxially grown layer of silicon or germanium containing a specified percentage of isotopically enriched silicon or germanium. These materials are controlled due to their critical role in developing spin-based quantum computers.

Fluorides, Hydrides, Chlorides: Specific chemicals of silicon or germanium that contain a certain isotopic composition are also restricted. These chemicals are essential in semiconductor manufacturing processes, particularly in the development of quantum technologies.

Silicon, Silicon Oxides, Germanium, or Germanium Oxides: These materials, when isotopically enriched, are restricted due to their applications in quantum computing and other advanced technologies. The control extends to various forms such as substrates, lumps, ingots, boules, and preforms . 

* The new export controls introduced by the Bureau of Industry and Security (BIS) are effective as of September 6, 2024. However, there are delayed compliance dates for certain items, allowing businesses until November 5, 2024, to comply with the new requirements, particularly for specific quantum technologies and related equipment. This delayed compliance is intended to give affected parties time to adjust to the new regulations.

Source:

2024-19633.pdf (SECURED) (govinfo.gov)

Rising Prices of Critical Metals Highlight Their Importance in Semiconductor Manufacturing Amid Global Supply Challenges

Germanium, gallium, and antimony are crucial to the semiconductor industry due to their unique electrical properties that make them essential for producing advanced electronic components. Germanium is used as a semiconductor material, particularly in high-speed electronics and fiber optics, due to its excellent ability to efficiently transmit electrical signals. Gallium, often used in the form of gallium arsenide, is vital for producing high-performance chips, LEDs, and solar cells because it can operate at higher frequencies and temperatures than silicon. Antimony is used in creating semiconducting alloys and compounds that improve the efficiency and performance of devices like diodes and infrared detectors. These materials are key to advancing the capabilities of modern electronics, making them indispensable in the production of next-generation technologies.

The prices of rare earth metals, essential for semiconductor manufacturing, have more than doubled in the past year following China's retaliation against U.S. semiconductor restrictions. Notably, China's export restrictions on metals like germanium and gallium have caused significant price hikes, with germanium seeing a 115% increase to $2,600 per kilogram, up from $1,200 in the first quarter of 2023. Gallium prices have also surged by 75%, rising from around $300 per kilogram at the beginning of 2024 to approximately $530 today. These price increases reflect China's strategic control over these critical materials in response to global trade tensions.

                            Germanium price (LINK)

The situation is expected to worsen, with no signs of price relief on the horizon. Starting October 1, 2024, all rare earth metals in China will be effectively under state control, and the export of gallium and germanium has required a license since August 2023. China's tightening grip on these minerals is seen as a powerful tool to counter U.S. efforts to impede its advancement in semiconductor production. Currently, China dominates the global supply of these materials, producing 94% of the world's gallium and 73% of germanium in 2023, and its export volumes have reportedly dropped by up to 50% since the restrictions were imposed.

China's export restrictions on critical metals may impact US and European industries by causing supply shortages and driving up costs in the semiconductor and electronics sectors. These disruptions can slow production and raise consumer prices. Additionally, the restrictions may force companies to seek alternative, potentially more expensive, sources, straining global supply chains and weakening the competitive position of US and European industries.

Sources:

Halvledarmetaller skenar i pris – Semi14

China Warns Japan Over Semiconductor Export Curbs as US Pressure and Economic Tensions Mount

China has issued strong warnings to Japan against imposing new restrictions on the sale and servicing of chipmaking equipment to Chinese firms, in response to pressure from the United States. The US is seeking to align Japan with its own restrictive measures aimed at curbing China’s semiconductor advancements. Japan is concerned about potential retaliation from China, particularly the possibility that China might cut off access to critical minerals essential for its automotive industry, which could severely impact companies like Toyota. This echoes past instances where China restricted exports of rare earths to Japan during diplomatic tensions.

The US is also considering more stringent restrictions on chipmaking tools and high-bandwidth memory chips, crucial for AI development, as part of its broader strategy to limit China's technological progress. However, the US has so far refrained from using the foreign direct product rule (FDPR) against Japan, a powerful measure that could control sales of products worldwide if they use any American technology. While diplomatic efforts continue, the situation is complicated by upcoming political changes in Japan and the US, with Japan seeking to ensure its supply chain security while managing pressure from both China and the US.

China's heavy reliance on Japan for crucial semiconductor materials and equipment, such as high-end photoresists and wafer processing tools, significantly complicates its stance in the ongoing tech war with the US and Japan. Four Japanese companies—JSR, Tokyo Ohka Kogyo, Shin-Etsu Chemical, and Fujifilm Electronic Materials—dominate the global market for advanced photoresists, holding about 70% of the market share, making China highly dependent on them despite efforts to develop its own production capabilities. Additionally, Japan's Tokyo Electron, Screen Holdings, Nikon, Kokusai, and Lasertec are key suppliers of semiconductor wafer processing equipment to China. Japanese chemical companies, such as ADEKA Corporation, JSR Corporation, and Mitsui Chemicals, are key suppliers of CVD and ALD precursors. These companies produce a range of specialized chemicals used in semiconductor manufacturing, including organometallic precursors, silanes, and other complex compounds essential for deposition processes.

Japan's exports rose 5.4% year-on-year in June, cooling from 13.5% growth in May and underscoring concerns that a slowdown in China may hamper Japan's trade-reliant economy. The trade balance came to a surplus of 224.04 billion yen.

In June 2024, Japan's export growth slowed to 5.4% year-on-year, down from 13.5% in May, raising concerns that a slowdown in China could negatively impact Japan's trade-dependent economy. Despite a weak yen boosting the value of exports, the actual volume of exports declined by 6.2%, highlighting the challenges Japan faces with sluggish external demand. Exports to China, which grew by 7.2%, were primarily driven by chip-making equipment, but this growth was significantly lower than the 17.8% increase seen in May. The trade balance swung to a surplus of 224 billion yen, as imports grew less than expected, marking Japan's first trade surplus in three months. However, analysts express concern over the lack of a strong export growth engine among Japan's trading partners, including the United States, Europe, and China.

This dependency on Japanese technology and materials puts China in a vulnerable position as Japan faces increasing pressure from the US to align with stricter export controls, further raising the stakes in the ongoing geopolitical and economic tensions.

Sources

China Warns Japan of Retaliation for Possible New Chip Curbs - Bloomberg

Japan export growth cools amid worries about China slowdown | Reuters

Breakthrough by Japanese Researchers - Block Copolymer Enables Ultra-Fine Semiconductor Patterns with 7.6 nm Half-Pitch

Scientists at Tokyo Institute of Technology and Tokyo Ohka Kogyo have developed a novel block copolymer (BCP) that could significantly advance semiconductor manufacturing by enabling finer circuit patterns through directed self-assembly (DSA). This new BCP, derived from a chemically tailored version of polystyrene-block-poly(methyl methacrylate) (PS-b-PMMA), self-assembles into lamellar structures with a half-pitch size of just 7.6 nanometers. This surpasses the capabilities of conventional BCPs, which struggle to achieve sub-10 nm features, and represents one of the smallest reported half-pitch sizes in the world for thin-film lamellar structures.

a Schematic of the DSA process using a PS-b-PGFM on a chemically patterned Si substrate. AFM phase images of a b PS-b-PGFM19-23 film on an NL35-modified DSA substrate (Ls = 90 nm) after annealing at 240 °C for 5 min, c PS-b-PGFM19-10 film on an NL38-modified DSA substrate (Ls = 84 nm) after annealing at 230 °C for 5 min, and d PS-b-PGFM18-11 film on an NL38-modified DSA substrate (Ls = 90 nm) after annealing at 230 °C for 5 min. All thin films are 19-nm thick and were etched using O2 plasma for 10 s prior to AFM.

The research, published in *Nature Communications*, highlights the potential of this new BCP to push the boundaries of miniaturization in electronics, which is crucial for the continued advancement of semiconductor technology. The tailored copolymer, PS-b-PGFM, exhibits reliable and reproducible self-assembly into extremely small nanometric patterns, making it a promising template for lithographic processes. As the demand for smaller feature sizes in semiconductor devices grows, this breakthrough could pave the way for next-generation Logic and Memory components that all need to continuously scale to smaller critical dimensions.

Sources:

Advances in Semiconductor Patterning: New Block Copolymer Achieves 7.6nm Line Width - Semiconductor Digest (semiconductor-digest.com)

Chemically tailored block copolymers for highly reliable sub-10-nm patterns by directed self-assembly | Nature Communications

Impact of Deposition Mechanisms on Feature Sizes in Area-Selective Atomic Layer Deposition of TiO2 and HfO2

A study from Georgia Techinvestigates the mechanisms behind area-selective atomic layer deposition (AS-ALD) of titanium dioxide (TiO2) and hafnium dioxide (HfO2) on poly(methyl methacrylate) (PMMA) and silicon (Si) substrates, emphasizing their effects on feature sizes and film thickness. The researchers found that TiO2 exhibits highly selective deposition on Si compared to PMMA, though the PMMA sidewalls inhibit deposition, resulting in smaller feature dimensions than the original patterns. In contrast, HfO2, while less selective, combines selective deposition with a lift-off mechanism, allowing for smaller feature sizes but limiting the possible thickness before full coverage occurs.

The study highlights that TiO2's truly area-selective deposition mechanism causes significant sidewall inhibition, restricting the achievable feature size to larger dimensions. However, HfO2's combination of selective deposition and lift-off results in less sidewall inhibition, enabling the formation of much smaller features. The research further suggests that the choice of deposition material and the mechanism it employs critically influences the minimum feature sizes that can be achieved in semiconductor fabrication, with practical implications for future device miniaturization.

Summary of the mechanisms for AS-ALD of TiO2 and HfO2 using a PMMA area-selective mask, along with the corresponding benefits and limitations of each material. J. Phys. Chem. C 2024, XXXX, XXX, XXX-XXX

The findings underscore that the AS-ALD mechanism—whether a pure area-selective process or a combination with lift-off—directly affects the precision and scalability of nanofabrication. TiO2's area-selective mechanism is more effective for creating precise patterns but is limited by sidewall effects, while HfO2 offers greater flexibility in feature size at the cost of potential thickness limitations due to less selective deposition behavior. Potentially the research provides valuable insights for optimizing deposition techniques in advanced semiconductor manufacturing.

Source

Mechanisms of Area-Selective Atomic Layer Deposition and Their Impact on Feature Sizes | The Journal of Physical Chemistry C (acs.org)

Innovations in Atomic and Molecular Layer Deposition of Rare Earth-Based Functional Thin Films: Expanding Horizons in Electronics and Optoelectronics

In a recent article, researches from Germany (Bochum University) and Finland (Aalto University) explore the evolution and advancements in the atomic layer deposition (ALD) and molecular layer deposition (MLD) techniques for rare earth-based thin films, emphasizing their role in diverse applications ranging from microelectronics to optoelectronics and medical diagnostics. Initially focused on developing rare earth oxides as high-k dielectric materials in semiconductor devices, research has expanded to include complex ternary and quaternary perovskite oxides with unique magnetic and catalytic properties. The recent surge in ALD/MLD techniques has enabled the creation of rare earth-organic hybrid materials with intriguing luminescence properties, promising new avenues for applications in lighting, imaging, and solar cells.

Survey over the different rare earth precursor classes commonly employed for the ALD and ALD/MLD of rare earth containing thin films. Color bars indicate successful ALD employment of the compound class for the respective element. R represents an element of the extended rare earth elements, while R’ and R’’ refer to specific substituents. These are: H = Hydrogen, Me = Methyl, Et = Ethyl, iPr = Isopropyl, nBu = Butyl, tBu = Tert-butyl.

The review also highlights the challenges associated with precursor development and the need for further research to optimize the chemical reactivity and long-term stability of these materials. The potential for these novel materials to revolutionize industries is significant, particularly in the creation of flexible devices and advanced optoelectronic applications. However, according to the article, achieving widespread industrial adoption will require continued collaboration between academia and industry to refine processes, enhance material performance, and ensure scalability.

Annually published ALD and ALD/MLD articles involving rare earth elements from 1992 to 2023. The publications were searched from Scopus and Web of Science, using search terms that included “atomic layer deposition” and “rare earth”, or “atomic layer deposition” and “lanthanide”. The data thus acquired were further manually refined to check for numbers as accurate as possible. Data were accessed lastly on 10-02-2024.

Source: Atomic and Molecular Layer Deposition of Functional Thin Films Based on Rare Earth Elements - Ghazy - Advanced Materials Interfaces - Wiley Online Library

Optimizing Atomic Layer Deposition Processes with Nanowire-Assisted TEM Analysis - Reducing Process Development CycleTimes by 80%

Researchers from  Empa, the Swiss Federal Laboratories for Materials Science and Technology located in Switzerland, have developed a novel method to optimize Atomic Layer Deposition (ALD) processes using high-aspect ratio nanowires coupled with Transmission Electron Microscopy (TEM). By directly depositing materials onto nanowires placed on TEM grids, the team was able to conduct immediate post-deposition analysis, significantly speeding up the optimization of process parameters such as layer thickness, chemical composition, and conformality. This approach allows for rapid feedback and adjustment, reducing the time required to fine-tune ALD processes by a factor of five. 

The study focused on optimizing the deposition of aluminum oxide using a standard trimethylaluminum (TMA) and water process. By varying cycle numbers, temperature, and pulse/purge times, the researchers identified optimal conditions for the ALD process, achieving a uniform and stoichiometric aluminum oxide layer. This method also revealed early-stage non-uniform growth in the initial cycles, providing new insights into ALD mechanisms. The researchers propose that this technique could extend beyond ALD to other deposition processes, offering a powerful tool for the rapid development and refinement of thin-film deposition technologies.

Source: Optimizing Atomic Layer Deposition Processes with Nanowire‐Assisted TEM Analysis - Schweizer - 2024 - Advanced Materials Interfaces - Wiley Online Library

The 2024 1st Asian-Pacific Atomic Layer Deposition (AP-ALD) Conference Shanghai, China, from October 17 to 20, 2024

Following the successes of the previous four international Conferences on ALD Applications and ten China ALD Conferences since 2010. the 2024 1st Asian-Pacific Atomic Layer Deposition (AP-ALD) Conference will be a four-day meeting, dedicated to the fundamentals and applications of Atomic Layer Deposition (ALD) technology in various fields. It will be held in Shanghai, China, from October 17 to 20, 2024. This conference will feature plenary sessions, oral sessions, poster sessions and industrial exhibitions.

The ALD technique has been widely used and explored in numerous fields such as microelectronics, photoelectronics, optical coating, functional nanomaterials, MEMS/NEMS, energy storage, biotechnology, catalysis technology and etc. This is attributed to some unique advantages of ALD, including precise control of nano-scale thickness, superior uniformity across a large area, excellent conformity, relatively low deposition temperature and stoichiometric composition. Especially in the field of microelectronics, ALD has been involved deeply into advanced integrated circuits to prepare high-k/metal gate, spacer, and ultrathin diffusion barriers for Cu interconnects etc. Furthermore, ALD is also receiving great attention for its potential application in photovoltaics, flexible electronics, organic electronics, flat-panel display and other emerging areas.

Invited speakers: Invited Speakers – AP-ALD

Conference Web: AP-ALD – ALD2024