Samsung Electronics Is Pushing Hard to Bring Monolithic 3D DRAM to HVM by 2025

Samsung Electronics has been enjoying its DRAM market leader position for about 30 years now. To retain the position further, it has intensified its R&D of monolithic 3D DRAMs to bring them to HVM by 2025.

DRAM’s performance boost based on scaling the cell size or pitch is approaching a physical limit for cramming more cells in a limited space. Additionally, the ultra-high aspect ratio capacitors may collapse leading to compromised device reliability. Therefore, switching from current 2D DRAMs to next-generation monolithic 3D DRAMs seems inevitable.

Samsung has reportedly intensified its R&D on stacking DRAM cells on top of each other in a monolithic fashion, unlike in the case of high-bandwidth memory (HBM), wherein multiple dies are stacked atop each other.

Besides High-k/Metal Gate transistor technology, Samsung is also considering adopting FinFET or gate-all-around (GAA) technology for the DRAM cell transistor to attain better electrostatic control of the charge flow within the channel with the gate electrode.

Micron Technology and SK Hynix are also reportedly developing monolithic 3D DRAMs. Micron recently filed a patent for a monolithic 3D DRAM that is different from that of Samsung. Micron’s approach is to change the shapes of the transistor and capacitor without laying down a cell. Major equipment manufacturers such as Applied Materials and Lam Research are also developing solutions for the monolithic 3D DRAMs.

By Abhishek Kumar Thakur & Jonas Sundqvist

Source: Samsung Electronics Gearing up to Develop World’s First 3D DRAM - Businesskorea

Applied Materials MEMORY MASTER CLASS 2021 - slide deck

I missed this opportunity, however, I am grateful for Lita Shon-Roy just sending me the link to the slide deck - Tack så mycket. 

Slide deck for the Memory Class LINK

Next class up is Logic June 16, 2021 followed by more interesting topics in 2nd half 2021:

• Specialty semiconductors
• Heterogeneous design and advanced packaging
• Inspection and process control

Teaser slide (Credit Dr. Sony Varghese, Director of Strategic Marketing at at Applied Materials)

You are welcome to contact us at TECHCET (jsundqvist@techcet.com) to dig further into the future surge of materials to realize the data-driven economy:

• ALD/CVD precursors
• Metals/PVD Targets
• Photoresist
• Wet chemicals
• CMP pads & slurries
• Bulk, Rare and Speciality gases
• Wafers

Applied Materials Introduces Materials Engineering Solutions for DRAM Scaling

• New Draco™ hard mask material co-optimized with Sym3® Y etcher to accelerate DRAM capacitor scaling
• DRAM makers adopting Black Diamond®, the low-k dielectric material pioneered by Applied Materials to overcome interconnect scaling challenges in logic
• High-k metal gate transistors now being introduced in advanced DRAM designs to boost performance and reduce power while shrinking the periphery logic to improve area and cost

SANTA CLARA, Calif., May 05, 2021 (GLOBE NEWSWIRE) -- Applied Materials, Inc. today announced materials engineering solutions that give its memory customers three new ways to further scale DRAM and accelerate improvements in chip performance, power, area, cost and time to market (PPACt).

The Draco hard mask resolves this issue with a new material whose selectivity is more than 30 percent higher than conventional DRAM capacitor hard masks. It enables the deposition of a 30 percent thinner hard mask, thus decreasing the capacitor’s aspect ratio and easing the difficulty of the etch process.

The digital transformation of the global economy is generating record demand for DRAM. The Internet of Things is creating hundreds of billions of new computing devices at the edge which are driving an exponential increase in data transmitted to the cloud for processing. The industry urgently needs breakthroughs that can allow DRAM to scale to reduce area and cost while also operating at higher speeds and using less power.

Applied Materials is working with DRAM customers to commercialize three materials engineering solutions that create new ways to shrink as well as improve performance and power. The solutions target three areas of DRAM chips: storage capacitors, interconnect wiring and logic transistors. They are now ramping into high volume and are expected to significantly increase Applied’s DRAM revenue over the next several years.

Introducing Draco™ Hard Mask for Capacitor Scaling

Since over 55 percent of a DRAM chip’s die area is occupied by the memory arrays, increasing the density of these cells is the biggest lever for reducing cost per bit. Data is stored as charges in cylindrical, vertically arranged capacitors that need as much surface area as possible to hold adequate numbers of electrons. As DRAM makers narrow the capacitors, they also elongate them to maximize surface area. A new technology challenge to DRAM scaling has emerged: the etching of the deep capacitor holes threatens to exceed the limits of the “hard mask” material that acts as a stencil to determine where each cylinder is placed. If the hard mask is etched through, the pattern is ruined. Taller hard masks are not viable because as the combined depth of the hard masks and capacitor holes exceeds certain limits, etch byproducts remain and cause bending, twisting and uneven depths.

Applied Producer® XP Precision® Draco™ CVD

The solution is Draco™, a new hard mask material that has been co-optimized to work with Applied’s Sym3® Y etch system in a process monitored by Applied’s PROVision® eBeam metrology and inspection system that can take nearly half a million measurements per hour. The Draco hard mask increases etch selectivity by more than 30 percent which enables a shorter mask. Draco hard mask and Sym3 Y co-optimization includes advanced RF pulsing which synchronizes etching with byproduct removal to enable patterning holes that are perfectly cylindrical, straight and uniform. The PROVision eBeam system gives customers massive, immediate actionable data on hard mask critical dimension uniformity which is the key to capacitor uniformity. Applied’s solution provides customers with a 50-percent improvement in local critical dimension uniformity and reduces bridge defects by 100X, thus increasing yields.

Implementation of Draco for DRAM capacitors. (Applied Materials Master Memory Class May the 5th 2021 LINK)

“The best way to quickly solve materials engineering challenges with our customers is to co-optimize adjacent steps and use massive measurements and AI to optimize process variables,” said Dr. Raman Achutharaman, group vice president, Semiconductor Products Group at Applied Materials.

Bringing Black Diamond® Low-k Dielectric to the DRAM Market

A second key lever of DRAM scaling is reducing the die area needed by the interconnect wiring that routes signals to and from the memory arrays. Each of the metal lines is surrounded by an insulating dielectric material to prevent interference between data signals. For the past 25 years, DRAM makers have used one of two silicon oxides – silane and tetraethoxysilane (TEOS) – as the dielectric material. Continual thinning of the dielectric layers has reduced DRAM die sizes but created a new technology challenge: the dielectrics are now too thin to prevent capacitive coupling in the metal lines whereby signals interfere with one another causing higher power consumption, slower performance, increased heat and reliability risks.

The solution is Black Diamond®, a low-k dielectric material first used in advanced logic. With DRAM designs now experiencing similar scaling challenges, Applied is adapting Black Diamond to the DRAM market and making it available on the highly productive Producer® GT platform. Black Diamond for DRAM enables smaller, more compact interconnect wires that can move signals through the chips at multi-gigahertz speeds without interference and at lower power consumption.

High-k Metal Gate Transistors Bring PPAC Improvements to DRAM

A third key lever of DRAM scaling is improving the performance, power, area and cost of the transistors used in the periphery logic of the chip to help drive the input-output (I/O) operations needed in high-performance DRAM like those based on the new DDR5 specification.

Until today, DRAM used transistors based on polysilicon-oxide which were phased out in foundry-logic by the 28-nanometer node because extreme thinning of the gate dielectric allowed electrons to leak, thereby wasting power and limiting performance. Logic makers adopted high-k metal gate (HKMG) transistors, replacing the polysilicon with a metal gate and the dielectric with hafnium oxide, a material that improves gate capacitance, leakage and performance. Now memory makers are designing HKMG transistors into advanced DRAM designs to improve performance, power, area and cost. In DRAM as in logic, HKMG will increasingly replace polysilicon transistors over time.

This technology inflection in DRAM creates growth opportunities for Applied Materials. The more complex and delicate HKMG materials stack is challenging to manufacture, and in-vacuum processing of adjacent steps using Applied’s Endura® Avenir™ RFPVD system has become the industry’s preferred solution. HKMG transistors also benefit from Applied’s epitaxial deposition technologies such as Centura® RP Epi along with film treatments including RadOx™ RTP, Radiance® RTP and DPN which are used to fine-tune the transistor characteristics for optimum performance.

“Draco hard mask and Black Diamond low-k dielectric are being adopted by leading DRAM customers, and the first HKMG DRAMs are now being introduced,” added Dr. Achutharaman. “Applied Materials projects billions of dollars in revenue growth as these DRAM inflections play out over the next several years.”

Additional information about the growth outlook for these technologies is being provided at Applied’s 2021 Memory Master Class being held later today. For more information, please visit the investor page of our website at https://ir.appliedmaterials.com.

Samsung confirms first HKMG for DDR5 DRAM

ASM International recently acknowledged that ALD High-k/Metal Gate (HKMG) is finally in high volume production for DRAM (LINK). Now Samsung confirms that. This is a small victory for all people working on this process for such a long time. My first tool ownership when I moved to Germany and started at Infineon was an ASM Polygon 200 mm cluster with a Pulsar 2000 chamber running HfO2, TiN, TiHfN, TiAlN, Al2O3, and my not fully understood HfN ALD process and a Poly chamber that I never really cared too much about. Press release below - and now do the maths - how big this business is once rolled out for all DRAM technologies to come - yeah $$$, many tulips indeed.

Samsung Develops Industry’s First HKMG-Based DDR5 Memory; Ideal for Bandwidth-Intensive Advanced Computing Applications

512GB capacity DDR5 module made possible by an 8-layer TSV structure

HKMG material reduces power by 13 percent while doubling the speed of DDR4

Samsung Electronics, the world leader in advanced memory technology, today announced that it has expanded its DDR5 DRAM memory portfolio with the industry’s first 512GB DDR5 module based on High-K Metal Gate (HKMG) process technology. Delivering more than twice the performance of DDR4 at up to 7,200 megabits per second (Mbps), the new DDR5 will be capable of orchestrating the most extreme compute-hungry, high-bandwidth workloads in supercomputing, artificial intelligence (AI) and machine learning (ML), as well as data analytics applications.

“Samsung is the only semiconductor company with logic and memory capabilities and the expertise to incorporate HKMG cutting-edge logic technology into memory product development,” said Young-Soo Sohn, Vice President of the DRAM Memory Planning/Enabling Group at Samsung Electronics. “By bringing this type of process innovation to DRAM manufacturing, we are able to offer our customers high-performance, yet energy-efficient memory solutions to power the computers needed for medical research, financial markets, autonomous driving, smart cities and beyond.”

“As the amount of data to be moved, stored and processed increases exponentially, the transition to DDR5 comes at a critical inflection point for cloud datacenters, networks and edge deployments,” said Carolyn Duran, Vice President and GM of Memory and IO Technology at Intel. “Intel’s engineering teams closely partner with memory leaders like Samsung to deliver fast, power-efficient DDR5 memory that is performance-optimized and compatible with our upcoming Intel Xeon Scalable processors, code-named Sapphire Rapids.”

Samsung’s DDR5 will utilize highly advanced HKMG technology that has been traditionally used in logic semiconductors. With continued scaling down of DRAM structures, the insulation layer has thinned, leading to a higher leakage current. By replacing the insulator with HKMG material, Samsung’s DDR5 will be able to reduce the leakage and reach new heights in performance. This new memory will also use approximately 13% less power, making it especially suitable for datacenters where energy efficiency is becoming increasingly critical.

The HKMG process was adopted in Samsung’s GDDR6 memory in 2018 for the first time in the industry. By expanding its use in DDR5, Samsung is further solidifying its leadership in next-generation DRAM technology.

Leveraging through-silicon via (TSV) technology, Samsung’s DDR5 stacks eight layers of 16Gb DRAM chips to offer the largest capacity of 512GB. TSV was first utilized in DRAM in 2014 when Samsung introduced server modules with capacities up to 256GB.

Samsung is currently sampling different variations of its DDR5 memory product family to customers for verification and, ultimately, certification with their leading-edge products to accelerate AI/ML, exascale computing, analytics, networking, and other data-intensive workloads

Tech Insights Teardown: Samsung’s D1z DRAM with EUV Lithography

Advanced and costly schemes for ArFi immersion-based multi-pattering are definitely running out of steam for leading-edge logic and EUV is continuing the march into high volume manufacturing now also for DRAM. The other day there was an announcement that SK Hynix, the world´s number two DRAM maker has signed a 5-year agreement with ASML for EUV scanners (LINK).

As a European, I must say that I like the situation that the key to continued scaling is kept in The Netherlands (ASML) and also the important key technology providers in Germany (Zeiss SMT, Trumpf) and Belgium in the form of the worlds leading research institute for scaling CMOS - imec and the EUV Resist Manufacturing & Qualification Center NV (EUV RMQC), a Joint Venture between imec and  JSR Micro NV (LINK).

Reuters: SK Hynix signs five-year deal worth $4.3 billion with ASML to secure EUV scanners

Now DRAMs from Samsung Electronics with applied EUV lithography technology for D1z DRAM in mass production have been found in the field and analyzed by Tech Insights and reported by EETimes (LINK).

According to EETimes, Samsung Electronics announced the world’s first development of both ArF-i based D1z DRAM and separately its EUV lithography (EUVL) applied D1z DRAM last year.

Tech Insights is excited that we have finally found Samsung’s new and advanced D1z DRAM devices and confirmed details of this technology.

Here just a teaser, please check out the original EETimes article or get the full report from Tech Insights (LINK).

Samsung DRAM cell design, a comparison of BLP patterns on D1z (a) without EUVL and (b) with EUVL.

Capacitorless DRAM using oxide semiconductors could be built in 3D layers above a processor’s silicon

One of the biggest problems in computing today is the “memory wall”—the difference between processing time and the time it takes to shuttle data over to the processor from separate DRAM memory chips. The increasingly popularity of AI applications has only made that problem more pronounced, because the huge networks that find faces, understand speech, and recommend consumer goods rarely fit in a processor’s on-board memory.

In December at IEEE International Electron Device Meeting (IEDM), separate research groups in the United States and in Belgium think a new kind of DRAM might be the solution. The new DRAM, made from oxide semiconductors and built in the layers above the processor, holds bits hundreds or thousands of times longer than commercial DRAM and could provide huge area and energy savings when running large neural nets, they say.

Continue reading: New Type of DRAM Could Accelerate AI (IEEE Spectrum)

The transistors in the capacitorless DRAM developed by U.S.-based researchers includes a tungsten-doped indium oxide [orange] semiconductor, palladium top and bottom gates [yellow], nickel source and drain electrodes [green] and hafnium oxide dielectrics [blue]. Image: University of Notre Dame

Micron Delivers Industry’s First 1α DRAM Technology

Micron recently announced that they are shipping memory chips built using the world’s most advanced DRAM process technology, which offers major improvements in bit density, power and performance. This is an astonishing feat of nanofabrication. 

Micron announcement: Micron Delivers Industry’s First 1α DRAM Technology

Micron’s 1α DRAM node will facilitate more power-efficient, reliable memory solutions and provide faster LPDDR5 operating speeds for mobile platforms that require best-in-class LPDRAM performance. Micron’s innovation brings the industry’s lowest-power mobile DRAM, with a 15% improvement in power savings,1 allowing 5G mobile users to perform more tasks on their smartphones without sacrificing battery life.

To find out more watch Thy Tran, vice president of DRAM Process Integration at Micron previously with Qimonda explain how to realize this amazing technology.

According to more details given in a Blog by Thy Tran, Micron uses Quadruple Patterning or Quad Patterning to realize the most critical lithography layers, which employ multiple ALD process steps and has become one of the biggest ALD market segment over recent years. See the video below by Lam Research for some more insights!

Quad patterning process flow (Image: Lam Research)

Imec demonstrate BEOL compatible architecture that paves the way to high-density 3D-DRAM memories

LEUVEN (Belgium), 15 December 2020 — This week, at the 2020 International Electron Devices Meeting, imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, presents a novel dynamic random-access memory (DRAM) cell architecture that implements two indium-gallium-zinc-oxide thin-film transistors (IGZO-TFTs) and no storage capacitor. DRAM cells in this 2T0C (2 transistor 0 capacitor) configuration show a retention time longer than 400s for different cell dimensions – significantly reducing the memory’s refresh rate and power consumption. The ability to process IGZO-TFTs in the back-end-of-line (BEOL) reduces the cell’s footprint and opens the possibility of stacking individual cells. These breakthrough results pave the way towards low-power and high-density monolithic 3D-DRAM memories.

(image: Imec)

Scaling traditional 1T1C (one transistor one capacitor) DRAM memories beyond 32Gb die density faces two major challenges. First, difficulties in Si-based array transistor scaling make it challenging to maintain the required off-current and world line resistance with decreasing cell size. Second, 3D integration and scalability – the ultimate path towards high-density DRAM – is limited by the need for a storage capacitor. Imec presents a novel DRAM architecture that responds to both challenges, thereby offering a scaling path towards low-power high-density 3D-DRAM memories.

The new architecture implements two IGZO-TFTs – which are well known for their very low off-current – and no storage capacitor. In this 2T0C configuration, the parasitic capacitance of the read transistor serves as the storage element. Resulting DRAM cells exhibit a retention time >400s thanks to an extremely low (extracted) off-current of 3x10-19A/µm. These breakthrough results were obtained for optimized scaled IGZO transistors (with 45nm gate length) processed on 300mm wafers. Optimization was directed towards suppressing the impact of oxygen and hydrogen defects on both on-current and threshold voltage – one of the main challenges for developing IGZO-TFTs.

Gouri Sankar Kar, Program Director at imec: “Besides the long retention time, IGZO-TFT-based DRAM cells present a second major advantage over current DRAM technologies. Unlike Si, IGZO-TFT transistors can be fabricated at relatively low temperatures and are thus compatible with BEOL processing. This allows us to move the periphery of the DRAM memory cell under the memory array, which significantly reduces the footprint of the memory die. In addition, the BEOL processing opens routes towards stacking individual DRAM cells, hence enabling 3D-DRAM architectures. Our breakthrough solution will help tearing down the so-called memory wall, allowing DRAM memories to continue playing a crucial role in demanding applications such as cloud computing and artificial intelligence.”

TechInsights Webinar: ALD/ALE Process in Commercially Available Memory Devices

2018 saw memory product manufacturers Samsung, Hynix, Toshiba and Micron introducing 64- or 72- stacked layer 3D-NAND devices, and move into 1x generation DRAM devices.

This presentation will examine some of the different structures we have seen through the evolution of these technologies, in particular the latest 3D-NAND and DRAM parts. We will also look at several historical applications of ALD/ALE technology that have been observed through reverse engineering. We will highlight the importance of ALD/ALE process in advanced logic devices. In many cases, the technology could not have advanced without the implementation of ALD technology.

Information and registration: LINK

Hafnium, Zirconium: Australian Strategic Materials a step closer to completing commercial pilot plan

Recent semiconductor materials related trade issues between Japan and South Korea have led South Korea to secure alternative sourcing of photoresists and metals for their semiconductor industry. This includes essential minerals for hafnium and zirconium ALD precursors that are used in the manufacturing of DRAM and Foundry logic at SK Hynix and Samsung fabs.

Besides the tension with Japan, China's dominance in the supply of zirconium chemicals and materials has highlighted the additional risk in the critical materials supply change for its important semiconductor and high tech industries.

One such action has been setting up a pilot plant in South Korea for hafnium and zirconium metal in joint development with Australias Alkane and its subsidiary Australian Strategic Materials (ASM). The joint undertaking has now moved to the next phase for a commercial operation of a pilot plant as reported by Alkaine below.

Australian Strategic Materials a step closer to completing commercial pilot plan

Australian Strategic Materials (ASM), a wholly owned subsidiary of Alkane Resources is getting closer to completing the construction of a commercial pilot plant facility in South Korea that will enable critical metal oxides, including zirconium and hafnium, to be converted into metals in clean, carbon-free way.

As the Covid-19 pandemic continues to highlight weaknesses in critical minerals supply chains globally, ASM has confirmed in Alkane Resources' quarterly recently it has received interest in both potential future supply and partnership from a number of parties in South Korea and elsewhere. ...

Read more.

Read more about previous blog about the Alkane Dubbo project in New South Wales, Austrailia:

The Dubbo Project - The High-k mine in Dubbo, NSW Australia

Hafnium product breakthrough consolidates Dubbo Project business case

China’s water crisis stems the flow of zirconium and rare earths for global industries

Alkane Resources reports that zirconium oxychloride (ZOC) prices are up 40% since January 2017

Choppy Waters for Shipping $50B of Semiconductor Materials in 2020

Risky Sailing on the Global Supply-Chain Seas

San Diego, CA, Apr 17, 2020:TECHCET announces that:

 

• 2020 global material revenues in semiconductor manufacturing forecasted to decline by 3.0% year-over-year (YoY) despite growth in 1Q2020,
• Impact of COVID-19 pandemic on the global economy is creating choppy waters for shipping and supplying critical materials, as highlighted in recent Critical Materials Council (CMC) monthly meetings, and
• With a return of global economic growth by 2021, compound annual growth rate (CAGR) through 2025 is forecast at 3.5% as shown in the Figure (below).
 

 

“From our market research, materials suppliers are increasing production and sales to ensure safety-stock throughout the supply-chain in case there are further disruptions due to COVID-19 cases,” remarked Lita Shon-Roy, TECHCET President and CEO. “Even without further disruptions, we can already see leading economic indicators such as unemployment levels, metal prices and container shipping indices point toward a significant decline in global GDP.” This is supported by the International Monetary Fund’s (IMF’s) current outlook on 2020.

Currently, almost all chip fabs appear to be running at normal levels, with a few exceptions. During this difficult period, YMTC in Wuhan, China reportedly has maintained R&D and grown production of 3D-NAND chips. However, chip fabs in Malaysia report that the government required companies to request permission to continue operating at 50% staffing levels. One company in France had to temporarily reduce production due to their labor union insisting on temporary workforce reductions.

Significant value-added engineered materials including specialty gases, deposition precursors, wet chemicals, chemical-mechanical planarization (CMP) slurries & pads, silicon wafers, PVD/sputtering targets, and photoresists & ancillary materials for lithography are reporting healthy orders and in some cases will see better than expected revenues for 1Q2020 and April 2020. However, more than 60% of all materials are expected to be negatively impacted before year-end.

Overall demand for commodity materials, such as silane and phosphoric acid, is expected to decline YoY in 2020 by an average of 3% due to softening of the global economy. Average selling prices (ASP) for electronic-grade commodities may drop due to cost reductions in feed-stocks; for example, the global helium (He) gas market which had been forecasted to be in shortage with high ASPs throughout 2020 has already improved due to COVID-19 slowing down helium demand.

DRAM, 3D-NAND, and MPU chips for server / cloud-computing applications are now in high demand for virtual meetings and remote work. It is yet unclear how much of an increase in materials shipments will be needed to support this segment, however from TECHCET’s modeling of prior cycles it will likely be >7%. Despite such an increase in the materials used to make leading-edge ICs to build out data centers, shipments in support of legacy node IC fabrication are expected to decline this year.

Consequently, cloud-computing growth may not compensate for overall reduced semiconductor materials demands caused by economic downturns this year. By 2021 the global economy and all chip fabs should return to healthier growth, with materials markets for all IC devices expected to increase at a CAGR of +3.5% through 2025.

Critical Materials Reports™ and Market Briefings: TECHCET Shop
CMC Events: Click here to view all Events

Micron claim DRAM Technology Leadership As Samsung And SK Hynix Push Out EUV

• ASML reported that four EUV lithography systems will be pushed out from shipping in 4Q 2019.
• My analysis suggests Samsung Electronics and SK Hynix are two of the companies pushing our EUV for their memory business.
• Micron's 1z nm DRAM already is technologically advanced, and are two quarters ahead of Samsung and one year ahead of SK Hynix.

Full article: Micron: DRAM Technology Leadership As Samsung And SK Hynix Push Out EUV, Seeking Alpha (LINK)

A DRAM roadmap by the Information Network showing Micron’s transition to 1z nm and gain of leadership over rivals Samsung and SK Hynix.

Micron has started volume production of 10 nm-class DRAM (1z nm)

Micron announced on Thursday that it had started volume production of memory chips using its 3rd Generation 10 nm-class fabrication technology (also known as 1Z nm). The first DRAMs to be made using Micron’s 1Z nm process are 16 Gb monolithic DDR4 and LPDDR4X devices. 

The company claims that its 16 Gb DDR4 device consumes 40% less power than two 8 Gb DDR4 DRAMs (presumably at the same clocks). Meanwhile, Micron’s 16 Gb LPDDR4X ICs will bring an up to 10% power saving. One of the first products to use the company’s 16 Gb DDR4 devices will be high-capacity (e.g., 32 GB and higher) memory modules for desktops, notebooks, and workstations.

Source: Anandtech LINK

----------

By Abhishekkumar Thakur

Applied Materials to buy Japan's Kokusai to boost memory chip business and ALD

Here are more details and analyst responses on the Applied Materials Kokusai purchase and my own thoughts at the end:

(Reuters, LINK) - U.S. chip gear maker Applied Materials Inc (AMAT.O) on Monday agreed to buy Japanese peer Kokusai Electric for $2.2 billion from KKR & Co Inc (KKR.N), as it bets on rising demand for memory chips used in data centers, 5G phones, and AI-powered devices.  

In summary:

• Kokusai is a small acquisition for Applied materials as compared to the previously failed mega-merger with Tokyo Electron, meaning that the road to approval should be easy. However, China’s willingness from a political standpoint is always a risk, Evercore analysts said. 
• Apart from China, the acquisition will need approvals from Israel, Ireland, Japan, Korea and Taiwan, Applied Materials Chief Financial Officer Dan Durn said on a call with analysts.
• Kokusai, which counts Samsung, SK Hynix, Toshiba and Micron among its top customers, reported revenue of $1.24 billion as of March 2018. 
• Kokusai’s batch wafer processing tools are less technology intensive than Applied Materials’ single wafer tools, the recent focus on ultra-thin films has driven renewed interest in this group, DA Davidson analysts said.

So this whole purchase is really about Applied Materials getting a state of the art ALD technology for the memory business (DRAM and 3DNAND). The last readout is a bit crazy, the analyst refers to ALD as an "Ultra Thin Films". Anybody who has followed the ALD business the previous 15-20 years know that Applied Materials has repeatedly failed to take a big market share in ALD and that a Japanese Large Batch ALD reactor is one of the most advanced and reliable ALD tools out there - simply because nobody would like to trash a full load of +100 product wafers. The top three domination has been by:

• ASM International
• Tokyo Electron
• Kokusai

The top 3 has been followed by Lam Research, Jusung Engineering, Wonik IPS and Applied Materials was always somewhere in this bunch. Even the inrodcution of the new Spatial ALD Olympia platform didn´t change things. It seems that Tokyo Electron took a large part of the spatial ALD market with their NT333 tool and ASM was able to defend their single wafer approach by making the XP platform super productive by adding more chamber slots (up to 16 for the latest ASM XP8 QCM).  

When it comes to IP in Spatial ALD, Tokyo Electron is No.1 followed by Applied Materials (see below).

IP Applications for spatial ALD

Magically, Kokusai settled the IP issues with ASM just before the Applied announcement (LINK). Historically, Kokusai has been masters in avoiding to call ALD ALD because of the IP situation. However, now there is a different situation and Kokusai also have single wafer ALD out there, and Applied is dominating the BEOL films deposition business so we can assume that Applied will enter top three and have a go at No 1. Exciting!

TechInsights’ Logic, NAND, DRAM and Emerging Memory Process Roadmaps are here

TechInsights’ Logic Process Roadmap offers an assessment and the anticipatory timing of new innovations from key players within the Logic space including: TSMC, Global Foundries, Intel & others. Download the roadmap here http://bit.ly/2FipHHA 

TechInsights’ technology roadmaps show you the innovations we are monitoring

For over 30 years, TechInsights has been reverse engineering semiconductors and advanced technology products, developing the world’s largest library of technical analysis. We have built this library through two approaches: by conducting analysis in response to client requests, and by proactively analyzing disruptive or innovative technologies as they are released.

We constantly monitor the consumer electronics market to determine which manufacturers are planning to release new solutions, and when. We maintain and regularly update technology roadmaps in several different areas: Logic, NAND Flash Memory, DRAM, Emerging Memory, and Internet of Things Connectivity Systems on Chips, and more.

Updates to the roadmaps shown below are released throughout the year; check this page for updates. 

4th CMC Conference Enabled Critical Information and Connections

Fab materials event in Albany, New York area April 25-26 featured GlobalFoundries keynote and Intel and TI presentations. Plan now for the 2020 April 23-24 event in Hillsboro, Oregon. 

(SAN DIEGO (PRWEB) May 07, 2019) Over 150 leading executives and managers within the semiconductor manufacturing ecosystem gathered on April 25th and 26th in the Albany area of New York state for an important event on fabrication (fab) materials. The fourth-annual Critical Materials Council (CMC) Conference, produced by TECHCET, included topical presentations, a fab tour, exhibits by specialty materials suppliers, and networking roundtable discussions to learn about best-practices in a pre-competitive environment. Folks who missed attending the event this year can register to access the posted presentations for a nominal fee at https://cmcfabs.org/cmc-conference-2019/.

The event opened again, as in each of the prior three years, on an extremely strong business and technology keynote address by an executive from one of the CMC Fab member companies. The 2019 CMC Conference keynote was given by Dr. John Pellerin, Deputy CTO and VP of Worldwide R&D, GlobalFoundries. Pellerin talked about how demand for new high-volume manufacturing (HVM) semiconductor devices over the next few years will drive needs for increased numbers of new specialty materials as well as volumes of existing materials in his presentation on "Materials Challenges & Opportunities in Differentiated Technologies."

In the first session of the event covering global supply-chain issues of economics and regulations, G. Dan Hutcheson, CEO of VLSI Research, presented on "Slowdown: When did it start? What drove it? And When will the recovery come?" Hutcheson showed data from leading economic indicators that the recent decline in global semiconductor fab industry revenues due to memory chip prices may have already turned around.

TECHCET Sr. Analysts Dr. Jonas Sundqvist and Terry Francis presented updated information on demand drivers and forecasts for ALD/CVD precursors and Rare Earths, respectively. Sundqvist--also leader of the Thin Film Technologies Group at Fraunhofer IKTS--focused on how new 3D memory and logic chips demand more deposition precursors such that chemical volume growth will outpace that of silicon wafers, shown in the Figure. Francis showed how "Rare Earth" elements are not so rare at the elemental level, but complex dynamics between mining and refining and capitalism have led to a situation where mainland China currently controls most of the market for elements such as lanthanum (used in advanced ICs to create CMOS logic gates). Deep dives into all such materials matters are found in the TECHCET Critical Materials Reports (CMR), and you can find all of them online at https://techcet.com/shop/. 

Global semiconductor silicon quarterly wafer shipments 2015-2019 in millions of square inches (MSI). (Source: TECHCET)

The 2020 spring CMC Conference is scheduled for April 24-25 in Hillsboro, Oregon. The CMC Fab members and Associate members will again gather for two days of private face-to-face meetings before attending the public CMC Conference.

In addition to the annual spring CMC Conference in the US, there is also an annual fall CMC Seminar in Asia. The 2019 CMC Seminar will be held on October 17 in Taoyuan, Taiwan. For more information on CMC events see https://techcet.com/cmc-events/.

About CMC:
The Critical Materials Council (CMC) of Semiconductor Fabricators (CMCFabs.org) is a membership-based organization that works to anticipate and solve critical materials issues in a pre-competitive environment. The CMC is a business unit of TECHCET, and includes materials supplier Associate Members.

About TECHCET:
TECHCET CA LLC is an advisory services firm focused on process materials supply-chains, electronic materials business, and materials market analysis for the semiconductor, display, solar/PV, and LED industries. Since 2000, the company has been responsible for producing the SEMATECH Critical Material Reports™, covering silicon wafers, semiconductor gases, wet chemicals, CMP consumables, Photoresists, and ALD/CVD Precursors. For additional information about reports, market briefings, CMC membership, or custom consulting please contact info(at)cmcfabs(dot)org, +1-480-332-8336, or go to http://www.techcet.com or http://www.cmcfabs.org.

Imec to present scaled Superduper High-k Ruthenium/Strontium titanate capacitor at IEDM

Here is another interesting IEDM 2018 paper from Imec. It is a classical paper obn DRAM capacitor scaling featuring the almost impossible Superduper High-k Ruthenium/Strontium titanate capacitor! It is an ALD integration, the patterning the capacitor everything - no need to involve anyone else - it is up to the Litho and ALD people to get the job done.

Paper #2.7, "High-Performance (EOT<0.4nm, Jg~10-7 A/cm2) ALD-Deposited Ru/SrTiO3 Stack for Next-Generation DRAM Pillar Capacitor," M. Popovici et al, Imec)

I have not seen the abstract but it has been reviewed by CDRInfo (see paragraph below) and I am sure there will be more details available soon (LINK):

"Scaling DRAM Technology To 16nm And Beyond: DRAM memory technology is used in virtually all electronic systems because of its speed and density. DRAM memory comprises arrays of capacitor-transistor pairs which store data as electrical charge in the capacitor; the presence of charge indicates "1" and its absence "0." Manipulation of these digits is the basis of computer programming. It’s difficult to scale DRAM to the 16nm generation and beyond because of space limitations which make it hard to pack enough capacitance within the pitch. Imec researchers used an atomic layer deposition (ALD) process to pattern and build a novel 11nm pillar-shaped capacitor using new dielectric materials (SrTiO3, or STO). By tailoring the material properties of the capacitor and the SrRuO3 (SRO) epitaxial template on which it was grown, the researchers achieved a very high dielectric constant (k~118) and low electrical leakage (10-7 A/cm2 at ±1V). This means that pillar-shaped capacitors can be used instead of existing cup-shaped capacitors, without paying too great a penalty in terms of reduced data-storage capability. These results make the STO capacitors suitable for continued scaling for 16nm and smaller DRAMs."

 

 

Construction work at Imec, Leuven, June 2013. The tower looks a bit like a DRAM Capacitor but somehow I do not think that the architect know that and I bet they were working on Ru/STO ALD well before that!

RASIRC® BRUTE® peroxide and hydrazine technology for leading edge memory and high performance logic

Hydrogen peroxide (H₂O₂) gas is an oxidant that improves passivation and nucleation density at semiconductor interfaces, potentially leading to reduced interfacial defect density. A new technology capable of generating and delivering stable anhydrous H₂O₂ gas has been developed by RASIRC. The method utilizes a substantially anhydrous H₂O₂ solution, a carrier gas and membrane pervaporator in order to deliver anhydrous H₂O₂. A broad range of high-k materials and interfaces that can be improved as well as enhanced transistor performance were shown at ALD2016 Ireland. 

H₂O₂ allows for unique process windows in ALD due to its oxidative potential, which lies between more commonly used water and ozone, and greater acidity relative to water [1]

RASIRC BRUTE H₂O₂ Apparatus (H₂O₂ + solvent) surrounds the Nafion membrane tubes. H₂O₂ passes through the membrane walls and is picked up by the carrier gas.

Growth of many different films has been showcased with BRUTE Peroxide and the related RASIRC product BRUTE Hydrazine. In presentations and posters at ALD2016 Ireland the RASIRC line of BRUTE Hydrazine and BRUTE Peroxide showed impressively many useful results by many different precursors. In total, four separate posters and presentations covered growth passivation of SiO_x on SiGe, SiN_x on SiGe, SiON on SiGe as well as  growing HfO₂, ZrO₂, TiO₂, Al₂O₃ and  TaO_x with the BRUTE line of new reactive chemistries.

Transistor channel passivation, Dan Alvarez presented results of growing SiN_x and SiO_xN_x  on SiGe using BRUTE Hydrazine and BRUTE Peroxide [2]. These films were then further processed with HfO₂ dielectric layer to grow MOSCAPs. These MOSCAPS had better performance than those processed with HF last and water vapor, where improved defect density and lower leakage characteristics were reported. In addition, the presentation by Dan Alvarez discussed how anhydrous hydrazine can be used to create a thin layer of silicon nitride that can act as a diffusion barrier or channel passivation layer prior to dielectric deposition in FinFets or MOSFETs. The study focused on <400 °C silicon nitride ALD process and showed how further oxidation using anhydrous peroxide provides good nucleation for High-k deposition.

A low Temperature Passivation on SiGe(110) via plasma free process by subsequent doses of anhydrous hydrazine and hexachlorodisilane can further increase the amount of SiNx on the surface. A final treatment with HOOH can prepare the surface for high-k deposition.

BRUTE Peroxide was reported to reduce HfO₂ gate oxide EOT by reduction in the interface layer

Steve Consiglio from Tokyo Electron, presented data comparing growth of HfO₂ and interface layer thickness control [3]. Utilizing 300 mm Si wafers with pre-formed chemical oxide, he evaluated an all in-situ method of chemical oxide removal (COR; Si-H termination) followed by H₂O₂(g) dosing prior to ALD growth of HfO₂ using TEMAHf and H₂O. The study reported faster growth rate with H₂O₂ than for O₃. Most interestingly, the interface results were very exciting with interface layer regrowth in the 2-4 Ångstrom range, which corresponds to ½ to 1 monolayer of SiOx interface for improved EOT and this was definitely much thinner than the results reported using O₃.

Aluminum oxide, Al₂O₃ ALD has been presented previously [4]. This time RASIRC had a poster on improved nucleation by using H₂O₂ as an oxidant in ALD of Al₂O₃ [5]. The poster explained the need for a novel oxidant that improves passivation and nucleation density at semiconductor interfaces. The study was performed on SiGe(110) surfaces and  provides a direct comparison of equal amounts of water, 30% H₂O₂/H₂O, and anhydrous H₂O₂. A five-fold increase was found in nucleation density for H₂O₂ versus water, and a three-fold increase for H₂O₂ versus 30% H₂O₂/H₂O. An additional comparison was made of H₂O₂ to H₂O by deposition of Al₂O₃ on an Si-H surface. This comparison found denser nucleation and faster initiation for H₂O₂ treated surfaces.

In a direct comparison of TMA based ALD with water vs peroxide the coverages of O and Al are higher with peroxide and growth starts earlier.

Zirconium oxide, ZrO₂  was presented in study by Intermolecular and RASIRC at ALD2016 Poster session [6]. By utilizing the Intermolecular Combinatorial ALD platform equipped with a RASIRC BRUTE H₂O₂ apparatus the study compared the performance of H₂O₂ against O₃ in a zirconium oxide ALD using ZyALD Air Liquide industry standard Zr-precursor. By MIMCAP integration the differences in ZrO_x unit film properties and electrical performance was shown. Similar unit film behavior (GPC, linearity, growth saturation, film crystallinity etc.) was observed between O₃ and H₂O₂.

Oxidant dosing (left) show that 4% O₃ yields saturated response, whereas H₂O₂ and 20% O₃ display softer saturation. ZyALD dose (middle) for each oxidant system shows definite completion for 20% O₃. All three investigated conditions show linear growth without growth inhibition (right).       

The MIMCAP study (above) concluded that ZrO2 produced with H₂O₂ matched the best performance of 4% O₃. Therefore it is possible to avoid issues observed with high (20%) O₃ concentration as showcased in the figure below. More importantly, H₂O₂ has the capability to produce thin node dielectric, which is needed for highly scaled DRAM nodes.

Optical (left) and SEM (middle) images of MIMCAPs, post-annealing, with defects observed with 20% O₃ and thin 5 nm ZrO_x. As comparison blanket TiN film enhanced resistivity was observed (right) using 4 resp. 20% O3 concentrations, whereas H₂O₂ lays in-between. Results suggest that elevated TiN bottom electrode oxidation takes place with 20% O₃ that leads to degassing during annealing.  However, the defect can be avoided with minimal reduction in growth rate, by using H₂O₂ as the oxidant.

Hafnium oxide, HfO₂ by TDMAHf along TEMAHf was the first Hf-precursors in use at the introduction of High-k in the DRAM industry more than 10 years ago at the 90nm node. HfO₂ ALD has also been investigated by Intermolecular using the H₂O₂/TDMAHf ALD process and in this study the MIMCAPs showed to match the best O₃ performance like in the case of ZrO₂ given in more detail above. In addition, Tokyo Electron presented work for HfO2 as summarized above.  

Titanium oxide, TiO₂ low temperature (100 °C) TiO_x ALD using H₂O₂ and TiMCTA (methylcyclopentadienyl tris(dimethylamino)titanium) as the metal precursor has successfully been grown as also reported by Intermolecular at ALD2016 Poster session [6].  

   

To summarize, RASIRC and their collaborations throughout the semiconductor insdustry and with leading research facilities have shown that many different films can be grown with BRUTE Peroxide and BRUTE Hydrazine and most importantly that BRUTE Peroxide can reduce EOT by reduction in the interface layer, yielding higher performing memory and logic devices.

References

[1] D. R. Lide, CRC Handbook of Chemistry and Physics (CRC Press, Boca Raton, 1996).

[2] Hydrogen peroxide gas for improved nucleation and initiation in ALD, Daniel Alvarez, Adam Hinckley, Pablo Macheno, Christopher Ramos, Jeffrey Spiegelman,

Anthony Muscat, Presentation at ALD 2016 Ireland.

[3] Anhydrous H₂O₂ for ALD HfO₂ growth and interfacial layer thickness control, Steven Consiglio, Robert Clark, Takahiro Hakamata, Kandabara Tapily, Cory Wajda, Gert Leusink, Presentation at ALD2016 Ireland.

[4] Comparison of Water Vapor to Ozone for Growth ALD Films, J. Spiegelman, J. Sundqvist, EU PVSEC Proceedings 2011, page 1694 – 1698.

[5] Hydrogen peroxide gas for improved nucleation and initiation in ALD, Daniel Alvarez, Adam Hinckley, Pablo Macheno, Christopher Ramos, Jeffrey Spiegelman, Anthony Muscat, Poster ALD2016 Ireland.

[6] Comparison of hydrogen peroxide and ozone for use in zirconium oxide atomic layer deposition, Gregory  Nowling,  Stephen Weeks, Daniel Alvarez, Mark Leo, Jeff Spiegelman, Karl Littau, Poster ALD2016 Ireland.