Imec Boosts Performance of III/V Devices using Novel ASMi ALD HKMG Stack

Imec presented a high performing gate-all-around InGaAs Nanowire FETs (Lg=50nm) at IEDM 2015. Imec succeeded in increasing the performance by gate stack engineering using a novel gate stack ALD inter-layer (IL) material developed by ASM, and high pressure annealing. The novel IL/HfO2 was benchmarked to the typically used Al₂O₃/HfO₂ stack.

TEM of complete gate-all-around InGaAs Nanowire FET and HRTEM of the gatestack. The insert shows a close up of the Interface Layer HKMG developed and presumably deposited by ASM on any of the ASM ALD chambers available at imec - I am assuming that the high-k was deposited in a Pulsar 3000 and the TiN cap in a ASM A412 Large Batch ALD Furnace and I have absolutely no clue what the ALD inter layer may be - obviously it has less electrons than HfO2.

According to Aaron Thean, vice president and director of imec’s advanced logic R&D program.Imec’s R&D enables Moore’s law beyond the 5nm technology node through 3 approaches:

• by are tackling the technology challenges to extend silicon CMOS devices towards smaller nodes. 
• by research into disruptive heterogeneous solutions for beyond-silicon CMOS devices to increase performance and introduce new functionalities. 
• by researching emerging beyond-CMOS devices and systems such as spintronics to investigate further functional scaling beyond device-density-driven scaling

The CTO of ASM Inernational had this to say about the GAA Gate Stack collaboration with imec:
“ASM and imec have a long history of R&D collaboration using many of ASM’s products and advanced deposition and thermal processes. As a leader in ALD, we are glad to see this breakthrough new ALD material now demonstrated in imec’s high mobility devices and presented at IEDM 2015.”

Full press release from imec : http://www2.imec.be/be_en/press/imec-news/iedm2015-iiiv-tunnelfet-gaa-nanowire.html