Saturday, December 5, 2015

Samsung is using an ALD Al2O3 gate dielectric for 3D V-NAND

Samsung seems to be using an ALD Al2O3 gate dielectric with a TiN/W Metal Gate according to Dick James at Chipworks who recently reported on the matter in front of IEDM 2015 (http://electroiq.com/chipworks_real_chips_blog/2015/12/02/a-look-ahead-at-iedm-2015/).

"Samsung started shipping their V-NAND last year, but that uses charge-trap storage, in which the electrons that make up the memory bits sit on a silicon nitride layer; the Intel/Micron device uses the conventional floating-gate method used in planar flash, where the electrons are stored on a polysilicon floating gate. It’ll be interesting to see the difference!"

Plan-view TEM images of Samsung V-NAND flash array (Chipworks) 

Looking at the rest of the stack one want to believe that also the TiN, SiO2 and SiN is deposited by ALD. However, knowing that those materials can successfully be deposited in a LPCVD or pulsed LPCVD process it can just as well be done in Large Batch furnaces from any of the companies ASM, Kokusai or Tokyo Electron. Those furnaces are for sure also capable of running the processes in a pure ALD mode though.

Below is a principal cross section of the first couple of cells in the Samsungs 3D NAND  from
Samsung SSD 850 Pro (128GB, 256GB & 1TB) Review: Enter the 3D Era by Kristian Vättö"


"NAND scaling in vertical dimension does not have the same limitations as scaling in the X and Y axes do. Because the cost of a semiconductor is still mostly determined by the die area and not by the height, there is no need to cram cells very close to each other. As a result, there is very little interference between the cells even in the vertical direction. Also, the usage of high-k dielectrics means that the control gate does not have to wrap around the charge trap. The result is that there is a hefty barrier of silicon dioxide (which is an insulator) between each cell, which is far more insulating than the rather thin ONO layer in 2D NAND."