Thursday, December 10, 2015

Stanford skyscraper chip design boosts electronic performance by factor of a thousand

Americans love building Skyscrapers and now they will get going building Skyscraper chips. They also like using units for temperature that nobody can relate to - it must be the first time I hear somebody using Fahrenheit referring to thermal budget in CMOS processing. 

"Fabricating a silicon chip requires temperatures close to 1,800 degrees Fahrenheit, making it extremely challenging to build a silicon chip atop another without damaging the first layer. The current approach to what are called 3-D, or stacked, chips is to construct two silicon chips separately, then stack them and connect them with a few thousand wires." 

A multi-campus team led by Stanford engineers Subhasish Mitra and H.-S. Philip Wong has developed a revolutionary high-rise architecture for computing. (Stanford University)

Anyhow, that´s a side step we all use Kelvin in any situation right. So the key to success in this future business will be to reduce the thermal budget for the front end CMOS processing or rather build a back end transistor preferably using less than 734 Fahrenhet or as in the Stanford approach thin and stack the chips and make interconnect using CNTs.

The Stanford Team  have already demonstrated a working prototype of a high-rise chip, which was preented at IEDM 2014 - a four-layered chip made up of two layers of RRAM memory sandwiched between two layers of CNTs.

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