Tuesday, December 29, 2015

CEA-Leti showcases 300mm quantum computing on silicon-on-insulator platform

Thanks Rob for Sharing this one in the FEP Group on LinkedIn as Semiconductor Today reported yesterday : Researchers in France believe they have made preliminary steps towards establishing a silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) platform for quantum information processing. Quantum information processing promises a revolution in cryptography and database searching. In particular, the superposition of quantum amplitudes enables a radical form of parallel processing for which a large number of potential super-efficient algorithms have been developed (and implemented on a relatively small scale in various model/prototype systems).

CEA-Leti and CEA-Inac have adapted a quantum dot technology originally developed for very-large-scale integration (VLSI) CMOS circuits. The dots are located beneath the gate electrode of field-effect transistors [Romain Lavieville et al, Nano Letters, vol15, p2958, 2015]. The dots can be populated with a small number of charge carriers (electrons or holes, depending on nFET or pFET structure), when the operating temperature is 0.1K.
What makes this extraordinary interesting is that the work is not done on some 10x10mm test coupon cluster tool but in a state of the art 300mm fab using standard leading edge CMOS equipment and some advanced lithography and patterning to produce those Si-nanowire - it is all production technology just around the corner.

Check out the beautiful ALD HKMG stack below - The HfSiON gate dielectric could actually be MOCVD since they do not explicitly state ALD in the paper. MOCVD High-k is used in production in the IBM common platform which next door neighbor in Grenoble to CEA/Leti, STMicro is member of together with Samsung, Globalfoundries and Panasonic.

TEM image showing the cross section of the 3.4 nm diameter CVD grown silicon nanowire (3.4 nm), the 7 nm thick SiO2 gate oxide, the 1.9 nm HfSiON, and the 5 nm ALD TiN/polysilicon gate [Figure from graphical abstract, Romain Lavieville et al, Nano Letters, vol15, p2958, 2015].