Tuesday, December 1, 2015

TSMC to present 16nm FinFET embedded HfO2 ReRAM at IEDM2015

According to Semconductor Engeneering, TSMC is to present a NVM 16nm FinFET embedded ReRAM at IEDM2015 using basically a standard ALD HfO2 High-k / Mettal Gate Stack. Assumingly, TSMC just run also here the standard ASM Pulsar HfCl4/H2O thermal ALD process like for the gate dielectric. The novel device integration is denoted FIND RRAM. Interesting here is a comparison with NVM 28nm Ferroelectric FeFET using also HfO2 in development by Globalfoundries, NaMLab, Fraunhofer and FMC, which is normally done using the ASM Pulsar process but has also been proven using other ALD Chambers and  precursors.Especially in the case of a 3D FRAM integration where typically HfCl4 is difficult. However, as far as I know these guys have yet not published a FinFET FeFET version, which should be pretty straightforward unless the rather thick HfO2 (6-10 nm) that is needed to get a ferroelectric phase of HfO2 proves difficult to integrate and especially pattern (dry etch or CMP).

ReRAM Gains Even More Steam. The prospect of using the latest in finFET processing to enable embedded non-volatile memory (NVM) will be described by a team from TSMC and Tsing Hua University in Taiwan at the IEDM meeting on Dec. 8 in Washington, D.C.

Fin in structured memory cell, from IEDM paper abstract. The fin consists of a multilayer sandwich of TiN/ HfO2/SiO2 with the finFET metal gate and epi SiP as the two electrodes.  

Here is some previous published material from EETimes Europe on this technology and the abstract below form the IEDM Memory RRAM session.

1Kbit FINFET Dielectric (FIND) RRAM in Pure 16nm FinFET CMOS Logic Process, H.-W. Pan, K.-P. Huang, S.-Y. Chen, P.-C. Peng, Z.-S. Yang, K.-H. Chen*, Y.-H. Kuo*, C.-P. Lin*, B.-Z. Tien*, T.-S. Chang*, C.-H. Kuo*, Y.-D. Chih*, Y.-C. King, and C.J. Lin, National Tsing Hua University, *Taiwan Semiconductor Manufacturing Company
A fully CMOS process compatible FinFET Dielectric RRAM (FIND RRAM) is firstly proposed and demonstrated by 1kbit RRAM macro on 16nm standard FinFET CMOS logic platform. The new 16nm low voltage FIND RRAM consists of one FinFET transistor for select gate and an HfO2-based resistive film for a storage node of the cell. The FIND RRAM largely improves the set and reset characteristics by the locally enhanced field at fin corners and results in a low set voltage and reset current in array operation. Besides, by adopting the 16nm FinFET CMOS logic process, the FIND RRAM is shrink to an aggressive cell size of 0.07632um2 without additional mask or process step. The low voltage operation, excellent reliability, and very stable LRS/HRS window are all realized in the new fabricated 1kbit macro. They all support the new FIND RRAM technology is a promising embedded NVM in the coming FinFET era.

As comparison, a TEM of FeFET processed in 28 nm high-k metal gate CMOS Technology (left) and 2D TCAD-model for device simulation (right). (Picture from NaMLab)

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