Atomic Layer Etching as a Scaling Enabler: From Isotropic Chemistry to Selective, Directional, and Geometry-Driven Patterning

Continued scaling in semiconductor manufacturing increasingly relies on atomic-scale control of etching for complex 3D material stacks, making patterning precision a growing industrial bottleneck. Atomic layer etching (ALE) has emerged as a key enabler, with plasma-driven anisotropy and surface-chemistry control allowing improved selectivity and profile fidelity for advanced logic and memory integration. Current approaches emphasize decoupling surface modification from material removal to enable low-temperature, highly controlled processes.

From an industry perspective, the focus is shifting toward systematic ALE process development frameworks that combine thermodynamic screening, tailored half-cycle chemistries, and experimental verification of etch rates and selectivity. These strategies are increasingly relevant as device architectures push beyond conventional materials and dimensions. At the same time, ALE is gaining attention for its potential to reduce process complexity, energy use, and chemical consumption, positioning it as both a scaling and sustainability enabler for future semiconductor manufacturing.

In a recent paper by Smith et al (reference below), Thermal ALE is described as a purely chemical, vapor- or gas-phase process in which both the surface modification and removal steps are self-limiting and thermally activated. Volatile products are typically formed through ligand-exchange reactions that generate metalorganics. Because no ions are involved, this mode of ALE is intrinsically isotropic, leading to uniform material removal in all directions. This makes thermal ALE attractive for conformal trimming, lateral recessing, and highly selective etches, but fundamentally limits its ability to produce vertical, profile-controlled features.

(a) Periodic table of the elements showing which metals, metal oxides, and metal nitrides have had ALE processes developed for them. In developing a new ALE process, determining the nature of the volatile etch product is critical, with some metals proving more favorable to etching via the formation of volatile metalorganics and others via volatile metal halides. Data compiled from the ALE Database [reference]. (b) An outline of the pathways by which reported ALE processes can proceed. Metals, metal oxides, and metal nitrides can be halogenated, with the modified layer removed by subsequent Ar⁺ sputtering or ligand exchange. Metals can be oxidized or nitrided, and the metal oxide or nitride subsequently etched. (c) Gibbs free energy minimization and volatility diagram analysis can be used to theoretically screen possible etch processes. (d) Various surfaces of Ni modified with (1) surface O, (2) mixed surface and subsurface O, and (3) subsurface O. The Gibbs free energy of reaction showed the importance of having an oxidized sublayer to achieve favorable thermodynamic etching. Adapted from ref [reference]. (e) Analysis of Gibbs free energy of reaction: nitridation of nickel could form metastable Ni3N, which can be etched through favorable reactions with formic acid, forming dimers of nickel formates. by Smith et al (reference below)

In contrast, plasma ALE introduces ions as an active control parameter, most commonly during the removal step. A plasma first forms a chemically modified surface layer, such as a halogenated or oxidized film, which is then selectively removed by directional ion bombardment within a narrow ALE energy window. The momentum of the ions provides anisotropy, enabling vertical etching with atomic-scale precision while suppressing continuous sputtering. This directionality comes at the cost of tighter process windows and increased sensitivity to ion-induced damage.

A hybrid plasma–thermal ALE approach is presented as a way to decouple anisotropy from volatilization chemistry. In this scheme, plasma exposure is used to directionally modify the surface or precisely control the thickness of the modified layer, while removal proceeds via isotropic, thermally driven ligand-exchange reactions. This allows anisotropy to be engineered through selective surface modification rather than sputtering alone. Overall, the key conclusion is that isotropic versus directional behavior in ALE is determined by how and where ions are used, not simply by whether the process is labeled thermal or plasma.

Comment on Geometry

From an industrial standpoint, atomic layer etching is emerging as a core patterning technology as device scaling shifts toward complex 3D architectures and heterogeneous material stacks where conventional plasma etching reaches its limits. Smith et al. highlight that future adoption will be driven by selective ALE, enabled by surface-chemistry engineering, controlled anisotropy, and precise balance between etching and deposition rather than brute-force sputtering. In this landscape, AlixLabs’ use of geometrical selectivity extends the ALE paradigm by exploiting feature pitch and local geometry as an additional selectivity axis, enabling pattern multiplication and critical dimension scaling without added lithography complexity. The convergence of chemical, directional, and geometrical selectivity positions ALE not as a niche technique, but as a scalable, cost- and sustainability-aligned solution for next-generation semiconductor manufacturing.

The relevance of these advances is underscored by their recent and upcoming exposure at major industry forums. Results demonstrating sub-10 nm, high-aspect-ratio patterning with APS™ were presented at the 248th Electrochemical Society (ECS) Meeting in October 2025, marking an important milestone in validating the technology on bulk silicon using mature lithography. This momentum continues at SPIE Advanced Lithography + Patterning 2026, where AlixLabs will present new APS™ results spanning nanoimprint lithography and simplified self-aligned quadruple patterning, including joint work with UMC. Together, these events signal APS™ and geometrically selective ALE moving from concept and lab validation toward broader industrial evaluation and integration.

AlixLabs announced that Dr. Dmitry Suyatin, CIPO and Co-Founder, presented new APS™ (Atomic Layer Etching Pitch Splitting) results at the 248th ECS Meeting in Chicago (October 12–16, 2025), demonstrating high-aspect-ratio, narrow-fin patterning on bulk silicon with critical dimensions below 10 nm using standard 193-nm immersion lithography. The results reinforce APS™ as a viable path to advanced logic patterning without next-generation scanners, enabling reduced process complexity and cost. Supported by recent patent milestones and progress toward a beta tool planned for operation in fall 2026, APS™ is positioned to move from lab-scale validation toward production-grade refinement, aligning with AlixLabs’ goal of making advanced semiconductor manufacturing more accessible and sustainable.

AlixLabs announced its participation at SPIE Advanced Lithography + Patterning in San Jose, where two abstracts by Reza Jafari Jam et al and Robin Athlé et al have been accepted for oral presentation, including one in collaboration with United Microelectronics Corporation (UMC). The presentations will showcase recent progress in APS™ (Atomic Layer Etching Pitch Splitting), demonstrating sub-13 nm half-pitch patterning on silicon and a simplified alternative to self-aligned quadruple patterning that delivers a 4× density increase using a streamlined three-step process. Together, the talks highlight APS™ as a precise, cost-effective, and more sustainable approach to advanced nano-patterning that reduces complexity compared with conventional multi-patterning schemes.

Reference:

AlixLabs – News

Adapted from Smith, T. G. and Chang, J. P., Atomic Layer Etching in Patterning Materials: Anisotropy, Selectivity, Specificity and Sustainability, Plasma Chemistry and Plasma Processing, 46:9 (2026), © The Author(s) 2026. Published by Springer Nature and licensed under CC BY 4.0.

Smith, T. G., Chang, J. P., Atomic Layer Etching in Patterning Materials: Anisotropy, Selectivity, Specificity and Sustainability, Plasma Chemistry and Plasma Processing, 2026, 46:9.

Atomic Layer Etching in Patterning Materials: Anisotropy, Selectivity, Specificity and Sustainability | Plasma Chemistry and Plasma Processing

AlixLabs presents HAR narrow-fin patterning at ECS 248

AlixLabs is pleased to announce that Dr. Dmitry Suyatin, CIPO and Co-Founder, has presented the company’s latest advances in APS™ (Atomic Layer Etching Pitch Splitting) at the 248th Electrochemical Society (ECS) Meeting held in Chicago, October 12–16, 2025.

During the session, Dr. Suyatin highlighted new experimental results demonstrating high-aspect-ratio (HAR), narrow-fin patterning on bulk silicon achieved using conventional immersion lithography at a 193-nanometer wavelength. These results further confirm the viability of APS™ as an innovative method for extending fine-pitch patterning capabilities using existing lithography infrastructure.

By enabling advanced logic patterning without the need for next-generation scanners, APS™ offers a significant opportunity to reduce process complexity and cost, paving the way for broader access to advanced semiconductor manufacturing technologies.

“These new APS™ results – demonstrating high-aspect-ratio narrow-fin (CD < 10 nm) patterning on bulk silicon – go hand in hand with our recent patent successes,” said Dmitry Suyatin, CIPO and Co-Founder of AlixLabs. “Together, they validate APS™ as both a technically sound and strategically protected innovation in semiconductor manufacturing. As we prepare to install our beta tool that will become operational in fall 2026, we’re excited to take APS™ from lab-scale to production-grade refinement. Each step brings us closer to making advanced logic manufacturing simpler, more accessible, and more cost-efficient for the global industry.”

The advances presented at ECS reflect AlixLabs’ long-term mission to lower the threshold to advanced logic production, supporting a more sustainable, affordable, and globally accessible semiconductor ecosystem.

This research has been led by Dr. Dmitry Suyatin and Dr. Intu Sharma, whose work continues to push the boundaries of patterning innovation.

Source: AlixLabs presents HAR narrow-fin patterning at ECS 248 – AlixLabs

ASML Posts Strong Q1 2025 Results Amid AI-Driven Demand and Tariff Uncertainty

ASML kicked off 2025 with solid first-quarter performance, beating expectations on both earnings and revenue as demand for advanced lithography tools—driven by AI and next-generation semiconductor nodes—remained robust. While the company reaffirmed its growth outlook for 2025 and 2026, it also flagged increasing geopolitical uncertainty, particularly around US-China tariffs, as a risk factor for the months ahead.

ASML delivered strong Q1 2025 results, with earnings per share of $6.82 and revenue of $8.80 billion, reflecting a 56% year-over-year increase. The company met or exceeded guidance across major financial metrics, with gross margins at 54%, supported by favorable EUV system configurations and higher average selling prices. Net system sales reached €5.7 billion—€3.2 billion from EUV and €2.5 billion from non-EUV—while Installed Base Management sales added €2 billion. Bookings totaled €3.9 billion, mostly from logic customers. Despite a seasonal dip in free cash flow due to payment timing and capital investments, ASML remains financially strong with €9.1 billion in cash.

CEO Christophe Fouquet and CFO Roger Dassen emphasized the ongoing strength of AI as a demand driver, particularly in advanced logic and memory, while acknowledging growing macroeconomic and geopolitical uncertainties—especially around tariffs. They reiterated revenue expectations for 2025 between €30 billion and €35 billion, with 2026 also anticipated to be a growth year. However, they cautioned that new tariff dynamics introduce significant unknowns for both ASML and its customers, which may affect gross margins and the broader supply chain.

On the technology front, ASML made progress with both its Low NA and High NA EUV systems. The NXE:3800E tool is now shipping at full spec and is seeing strong adoption among logic and memory customers aiming for single-expose EUV. Meanwhile, the High NA NXE:5000 has demonstrated better maturity compared to the Low NA at a similar stage, with customers like Intel and Samsung reporting substantial gains in productivity and process simplification. ASML shipped its fifth NXE:5000 in Q1 and is beginning shipments of the NXE:5200, which will be critical for phase two customer evaluations. Full-scale adoption is expected from 2026–2028, contributing to ASML’s long-term revenue forecast of €44 billion to €60 billion by 2030.

ASML addressed growing concerns over US and China tariffs, highlighting the high level of uncertainty surrounding their scope and impact. The company is actively assessing both direct and indirect consequences, including tariffs on system sales, parts imports, and servicing operations. ASML emphasized that it is working closely with customers and suppliers to mitigate disruptions and ensure that tariff-related costs are fairly distributed across the value chain, rather than being absorbed solely by ASML. While management acknowledged that these discussions are still evolving and outcomes remain unclear, they cautioned that tariffs could introduce volatility in margins, supply chain planning, and customer delivery schedules. Despite this, ASML noted that the current business conversations with customers remain unchanged and the long-term strategic investment momentum—especially in logic and AI-related capacity—appears resilient.

Sources:

ASML Holding N.V. 2025 Q1 - Results - Earnings Call Presentation (NASDAQ:ASML) | Seeking Alpha

ASML Holding N.V. (ASML) Q1 2025 Earnings Call Transcript | Seeking Alpha

AlixLabs to Demonstrate APS™ on 300-millimeter UMC wafers at the 2025 CMC Conference

Atomic Layer Etching Pitch Splitting (APS) proven on more industry-leading wafers, doubling fin density and proving flexibility without EUV.

Austin, TX, USA/Stockholm, Sweden – April 10th, 2025 – AlixLabs AB, a Swedish semiconductor startup specializing in Atomic Layer Etching (ALE), today demonstrates the latest in its line of groundbreaking development in advanced chip fabrication unveiling additional research into its novel semiconductor manufacturing process known as APS™ (Atomic Layer Etching Pitch Splitting) capable of doubling fin density while introducing the unprecedented flexibility to vary pitch and critical dimensions within the same wafer area.

Proven on 300-millimeter wafers provided by United Microelectronics Corporation (UMC), the APS™ technology successfully halved pitch compared to current industry benchmarks. This significant advancement was achieved entirely without relying on expensive and energy-intensive Extreme Ultraviolet (EUV) lithography.

Instead, APS™ leverages advanced etching techniques that substantially enhance sustainability, drastically reducing energy consumption without compromising throughput. Previous demonstrations of the APS™ process, validated through Intel’s Test Vehicle Program[1], confirmed its potential by achieving metal pitches as small as 25 nanometers.

“Today we are sharing more proof that the APS™ process can be a game changer for leading foundries. Thanks to UMC, we have been able to verify our process on production wafers that are shipped in quantities measured in millions of wafers annually,” said Dr. Robin Athle, Principal Researcher at AlixLabs. “Our mission is to create equipment that allows companies that don’t have access to EUV tools to scale down their production to 5 nanometer and beyond. By eliminating the dependency on EUV lithography, we are offering the industry a path towards more sustainable and economically feasible high-density chip production.”

Detailed results from AlixLabs’ UMC wafer tests and further insights into APS™ technology will be presented at the 2025 CMC Conference, scheduled for April 10th in Austin, Texas. Dr. Athle’s presentation “Atomic Layer Etching Pitch Splitting (APS™): a New Alternative to Multi Patterning” will be held at 4:00 PM at the Bergstrom Ballroom in Hilton Austin Airport Hotel.

JSR Expands Global Semiconductor Material Capabilities with New Photoresist Facilities, Advanced MOR Variants, and Strategic Acquisition of CVD/ALD Precursor Firm

JSR Corporation is expanding its global development and production of advanced photoresists by establishing a new R&D center in Japan and constructing a semiconductor photoresist plant in Korea. Since acquiring Inpria Corporation in 2021, JSR has been commercializing Metal Oxide Resist (MOR) for EUV lithography. The new R&D center in Japan’s Kanto region will enhance collaboration with global customers and partners, while the Korean plant, expected to begin operations in 2026, will handle the final production process for MOR to support local adoption. JSR aims to drive innovation in photoresists and help customers establish commercial production processes worldwide.

JSR's MOR, developed through its 2021 acquisition of Inpria Corporation, is a next-generation photoresist designed for EUV lithography. MOR is based on metal oxide nanoparticles, offering superior etch resistance and improved pattern resolution compared to traditional chemically amplified resists (CARs). This allows for finer feature definition and reduced line-edge roughness, critical for advanced semiconductor manufacturing below 10 nm. JSR has been scaling MOR for commercial adoption, with major semiconductor manufacturers evaluating its use in high-volume production. The company is expanding its R&D and manufacturing capacity, including a new R&D center in Japan and a production facility in Korea, to support global adoption of MOR.

JSR have investigated different flavors of MOR for EUV lithography, primarily focusing on variations in metal cores and process optimizations. Initially, zirconium (Zr) and hafnium (Hf) based MORs were explored, but their relatively low EUV absorption led researchers to investigate alternative metal cores such as titanium (Ti), zinc (Zn), indium (In), and tin (Sn). These new metal cores exhibited improved lithographic performance, achieving higher EUV absorption, smaller particle size, and better scum reduction. Additionally, process optimizations such as using higher dissolution rate photoacid generators (PAGs), new organic solvent developers, and lower soft bake temperatures were tested to improve scum removal and resolution. The new metal core variants demonstrated resolutions down to 13 nm with reduced defects, suggesting their potential for advanced semiconductor manufacturing.

In August 2024, JSR Corporation completed the acquisition of Yamanaka Hutech Corporation (YHC), a Kyoto-based manufacturer specializing in high-purity chemicals for semiconductor manufacturing. This strategic move allows JSR to expand its product portfolio to include Chemical Vapor Deposition (CVD) and Atomic Layer Deposition (ALD) precursors, which are essential for forming advanced and complex semiconductor device structures. YHC, established in 1960, has over 60 years of experience in advanced molecular design, synthesis technology, and quality control systems, supplying high-quality CVD/ALD precursors to leading-edge semiconductor device manufacturers. The acquisition aligns with JSR's strategy to strengthen its position as a global supplier of semiconductor materials, enhancing its capabilities in both miniaturization and device structure innovation.

Sources:

JSR Expands Global Development and Production Functions for Leading-Edge Photoresists | 2024 | News | JSR Corporation

tec125-4.pdf

Integrating Metal-Oxide EUV Resists with Directed Self-Assembly for High-Resolution Chemical Patterning

Extreme ultraviolet (EUV) lithography struggles with resist materials that can deliver both high resolution and acceptable throughput, often resulting in rough patterns and printing defects that degrade semiconductor performance. To overcome this, researchers are exploring directed self-assembly (DSA) of block copolymers (BCPs), which can naturally rectify pattern defects when aligned to EUV-defined chemical guides. However, metal-oxide EUV resists (MORs), which provide high resolution, face challenges in converting their patterns into effective chemical guides for DSA integration.

This study presents a novel method using hydrogen silsesquioxane (HSQ), a negative tone resist, to create chemical patterns for integrating MORs with DSA. The process involves forming a sacrificial chromium pattern from HSQ, which is later replaced with a polyethylene oxide brush layer and a nonpolar polystyrene brush. These steps allow the successful assembly of polystyrene-block-poly(methyl methacrylate) BCPs, achieving 24 nm full-pitch resolution. This approach shows potential for producing sub-10 nm patterns by combining high-χ BCPs with MOR-based EUV lithography, advancing next-generation semiconductor fabrication.

DSA of BCPs is a promising nanofabrication technique that utilizes the phase separation properties of BCPs to create highly ordered nanoscale patterns with feature sizes below 10 nm. In DSA, BCPs self-organize into distinct microdomains, forming well-defined structures that can be guided using chemoepitaxy or graphoepitaxy. Chemoepitaxy involves chemically patterned surfaces that influence the alignment and orientation of BCP domains, while graphoepitaxy uses topographical features to achieve similar control. High-χ (chi) BCPs are often used to achieve finer pattern resolutions, and material optimizations such as selecting appropriate substrates and brush layers are crucial to improving pattern quality and reducing defects. DSA has been explored for various semiconductor applications, including the creation of dense line-space arrays, hole shrink patterns, and advanced memory devices, offering significant potential to enhance pattern fidelity, reduce defectivity, and lower manufacturing costs.

Sources:

High-resolution chemical patterns from negative tone resists for the integration of extreme ultraviolet patterns of metal-oxide resists with directed self-assembly of block copolymers | Journal of Vacuum Science & Technology B | AIP Publishing

https://www.spiedigitallibrary.org/conference-proceedings-of-spie/12956/3010817/Material-and-process-optimization-for-EUV-pattern-rectification-by-DSA/10.1117/12.3010817.full

https://journals.spiedigitallibrary.org/conference-proceedings-of-spie/12497/124970K/EUV-lithography-line-space-pattern-rectification-using-block-copolymer-directed/10.1117/12.2657990.full
https://www.mdpi.com/2073-4360/12/10/2432

https://www.spiedigitallibrary.org/conference-proceedings-of-spie/PC12054/PC1205402/Exploring-the-synergy-between-EUV-lithography-and-directed-self-assembly/10.1117/12.2622565.full
https://journals.aps.org/prb/abstract/10.1103/PhysRevB.101.085407

ASML's 2024 Investor Day Highlights EUV-Driven Revenue Projections of €44-60 Billion by 2030 Amid AI, DRAM Scaling, and Advanced Semiconductor Growth

At its 2024 Investor Day, ASML projected annual revenue of €44 billion to €60 billion with gross margins of 56% to 60% by 2030, driven by double-digit growth in EUV lithography spending for Logic and DRAM, AI-driven semiconductor demand, and scalable EUV technology enabling cost-effective solutions for advanced nodes.

(Full video available here: Investor Day 2024)

DRAM scaling is undergoing a transformation fueled by the adoption of EUV lithography and the architectural shift to 3D DRAM, spearheaded by industry leaders Samsung, SK Hynix, and Micron. EUV lithography extends traditional DRAM scaling, enabling smaller cell sizes and higher densities. Micron plans to integrate EUV into DRAM production by 2025, marking a significant step toward cost-effective scaling. Samsung and SK Hynix are pioneering 3D DRAM architectures, which stack memory cells vertically to enhance density, performance, and energy efficiency. Samsung aims to commercialize 3D DRAM by 2030, while SK Hynix is targeting 2027-2028 for the introduction of vertical channel transistors (VCTs) with compact 4F² cell designs. These advancements represent a leap forward, with EUV lithography ensuring 2D scaling and 3D DRAM addressing physical and economic scaling limitations, paving the way for higher capacities and improved performance.

The progress and benefits of High-NA EUV lithography, with over 10,000 wafers exposed, including 1,300 DRAM and foundry customer wafers, and a target of 2,000 wafers by the end of 2024. Leading semiconductor companies like Micron, Intel, Samsung, SK Hynix, TSMC, and IBM are leveraging High-NA systems to enhance precision and scaling. Mark Philips from Intel highlights the readiness of High-NA EUV with robust tool availability and ecosystem support, enabling advancements like RibbonFETs, PowerVia, and "6x12" masks, which offer 23-50% productivity improvements over previous platforms. These developments underscore the role of High-NA EUV in enabling cost-effective scaling for DRAM and logic manufacturing.

ASML is pivotal in advancing EUV lithography for DRAM manufacturing. By 2024, memory manufacturers such as Samsung and SK Hynix had begun integrating EUV into production to enhance patterning precision and enable further scaling. ASML’s High-NA EUV systems, like the TWINSCAN EXE:5000, are expected to be production-ready by 2025, meeting stringent requirements for higher density and performance in memory technologies. Collaborations like the High-NA EUV Lithography Lab with imec have successfully demonstrated patterning for DRAM and logic structures, showcasing readiness for high-volume manufacturing by 2025-2026.

EUV lithography spending for DRAM is projected to grow at a CAGR of 15-25% through 2030. This growth is driven by the adoption of EUV for enhancing patterning precision and enabling further scaling in DRAM manufacturing. Key advancements include the integration of High-NA EUV systems, like ASML’s TWINSCAN EXE:5000, which is expected to be production-ready by 2025. These technologies support the development of 2D scaling and the transition to 3D DRAM architectures, addressing the physical and economic scaling challenges. Industry leaders Samsung, SK Hynix, and Micron are at the forefront of these efforts, incorporating EUV to achieve smaller cell sizes, higher densities, and improved energy efficiency.

Obviously, advanced logic drives EUV adoption. Spending in this sector is expected to grow at a CAGR of 10-20% through 2030, with High-NA systems playing a critical role in scaling logic nodes. Meanwhile, NAND benefits from advanced lithography solutions addressing the complexity of 3D NAND structures. Though it relies heavily on deposition and etch technologies, advanced DUV and EUV systems provide critical support for these applications.

The global semiconductor market is expected to grow significantly, driven by factors such as AI, high-performance computing, and 5G, which are fueling demand for advanced chips. Semiconductor sales are projected to reach $1 trillion by 2030, supported by the rapid adoption of AI technologies, growing automotive semiconductor needs for electric and autonomous vehicles, and the expansion of 5G networks and connected devices. Additionally, exponential growth in data generation is driving demand for robust data storage solutions, while continuous innovations in manufacturing, such as EUV lithography, enable smaller and more efficient chips. 

The global semiconductor market is expected to grow significantly, driven by AI, high-performance computing, and 5G. Sales are projected to reach $1 trillion by 2030, with wafer demand growing by 780,000 wafer starts per month annually. Strategic considerations, including geopolitical factors, are adding 5-8% extra wafer capacity by 2030. China’s role in the semiconductor industry remains vital, as the country invests heavily in advanced technologies to strengthen its manufacturing capabilities. However, due to export restrictions, China does not have access to ASML's EUV lithography tools. Instead, Chinese manufacturers focus on DUV technology and other innovative approaches to enhance their capabilities in advanced logic and DRAM production. Despite these limitations, China’s expanding wafer capacity contributes significantly to global growth projections, ensuring its relevance in the industry. The region’s efforts to integrate cutting-edge technologies, supported by partnerships with global leaders, highlight its ambitions to remain competitive and innovative in the semiconductor market.

ASML’s holistic lithography approach integrates computational models, metrology, and scanner optimization to maximize accuracy and yield. Innovations target reducing Edge Placement Errors (EPE) and enhancing defect inspections for 2D and 3D structures. The holistic lithography market is expected to grow at a CAGR exceeding 15% through 2030. Holistic lithography also plays a critical role in supporting front-end 3D integration by ensuring overlay control throughout pre-bonding, bonding, and post-bonding processes. Pre-bonding achieves <5 nm overlay error using scanner and offline metrology for correction and control, while bonding addresses large wafer deformation with extensive metrology (50-100 nm overlay error with over 5000 measurements per wafer). Post-bonding refines overlay error to <5 nm with over 2000 measurements per wafer, leveraging scanner actuators and lithography adjustments to bring errors within specifications.

ASML’s holistic lithography approach integrates computational models, metrology, and scanner optimization to maximize accuracy and yield. Innovations target reducing Edge Placement Errors (EPE) and enhancing defect inspections for 2D and 3D structures. The holistic lithography market is expected to grow at a CAGR exceeding 15% through 2030.

In conclusion, ASML’s strategy leverages its installed base, drives EUV and DUV advancements, and capitalizes on AI-driven demand. With projected annual revenue of €44-60 billion by 2030 and gross margins between 56% and 60%, ASML remains at the forefront of semiconductor innovation, enabling transformative progress in DRAM, logic, and NAND technologies.

Sources:

Investor Day 2024

South Korea's Exports Surge in August Driven by Semiconductors; SK Hynix Leads 1c DRAM Production, Samsung Confirms Investment for 2025 Launch; Both Giants to Adopt Next-Gen Photoresist Technologies

In the first 10 days of August 2024, South Korea's exports increased by 16.7% year-on-year, reaching $15.5 billion, driven primarily by a significant 42.1% surge in semiconductor exports. Other sectors like petroleum products and automobiles also saw growth, with automobile exports rising sharply by 63.9%. However, machinery product exports declined by 10.6%. Imports grew by 13.4% to $18.4 billion, resulting in a trade deficit of $2.9 billion. Notably, exports to major trading partners China and the United States increased by 10.7% and 27.7%, respectively. This continues a trend of export growth, marking the tenth consecutive month of gains as of July.

SK hynix has announced it will begin mass production of its 6th generation (1c) 10nm class DRAM in the third quarter of 2024, ahead of Samsung Electronics, which plans to start production by the end of the year. SK hynix has already established an internal road map to achieve customer certification and start production, potentially positioning itself to capture significant demand from major tech companies like Amazon and Microsoft once Intel certifies its DRAM for server use. The 6th generation DRAM, utilizing advanced Extreme Ultraviolet (EUV) lithography, promises higher chip yields and improved power efficiency compared to previous generations.

Samsung has confirmed its investment in the Pyeongtaek P4 plant for the production of 6th-generation 1c DRAM, with plans to begin mass production in June 2025. This next-generation DRAM, which uses 10nm-class technology, is still not commercialized globally, but Samsung and SK hynix are preparing for its mass production. Despite initial delays due to a downturn in the semiconductor market, Samsung is now expanding its P4 facility, initially installing NAND flash equipment and confirming plans for 1c DRAM production. The company also anticipates launching HBM4 using 1c DRAM by the second half of 2025, aligning with forecasts of significant growth in the memory industry's revenues.

Both Samsung and K Hynix plans to adopt Inpria's metal oxide resist (MOR) technology in the production of 1c DRAM, utilizing MOR to draw the finest lines on one of the five to six  EUV layers in the 1c DRAM. This adoption aims to enhance performance and reduce costs in future DRAMs. MOR is seen as a next-generation alternative to the chemically amplified resist (CAR) currently used in advanced chip lithography, addressing CAR's limitations in resolution, etching resistance, and line edge roughness. 

In 2021, JSR Corporation announced its acquisition of Inpria Corporation, the leading innovator in metal oxide photoresist technology for EUV lithography, solidifying its focus on advancing semiconductor materials.

Samsung is considering multiple suppliers for its EUV MOR photoresist needs beyond Inpria, including companies like Dupont, Dongjin Semichem, and Samsung SDI. These alternatives are currently being tested as the company explores the best options for its 1c DRAM production. 

Lam Research refers to its inorganic photoresist technology as "dry resist," which reportedly is expected to be supplied for Gen 7 10nm (1d) DRAM production, anticipated to launch next year. This dry resist is deposited by ALD and represents a further evolution in PR technology, potentially offering enhanced performance for the next generation of DRAM manufacturing.

Exports increase 16.7 percent in first 10 days of August - The Korea Times

SK hynix Leads with ‘6th Generation 10 nm’ DRAM Production Ahead of Samsung - Businesskorea

[News] Samsung Reportedly Confirms Investment in Pyeongtaek P4 Plant for 6th-Generation 1c DRAM | TrendForce Insights

SK Hynix to adopt Inpria MOR in 1c DRAM - THE ELEC, Korea Electronics Industry Media (thelec.net)

Samsung said to consider Inpria's metal oxide resist for 1c DRAM process (digitimes.com)

Samsung considering applying metal oxide resist in next DRAM - THE ELEC, Korea Electronics Industry Media (thelec.net)

Lithography Materials Headed for Upwards Growth

PFAS elimination efforts expected to drive migration to photoresist alternatives

San Diego, CA, August 8, 2024: TECHCET— the electronic materials advisory firm providing business and technology information —is forecasting semiconductor photoresist revenues to increase by nearly 11% in 2024. Overall semiconductor market recovery is expected in 2024, particularly in the second half, which should drive increased demand for all resists. In parallel, photoresist ancillaries are expected to increase by around 10%, and extensions by around 9%. More details on photoresist volume and revenue forecast by material can be found in TECHCET's new Lithography Materials Critical Materials Report™.

Recent pushes in the EU and US to eliminate PFAS-related chemicals are expected to gradually impact future photoresist material compounds. Photoresists that use photoacid generating (PAG) compounds have been qualified and used for many years, making it challenging to switch away to alternatives. While numerous companies and universities are working to develop non-PFAS-related PAGs, current performance is not yet meeting all process requirements. Consequently, defining suitable non-PFAS PAG alternatives and transitioning effectively is expected to take 5-10 years.

To read the full article, go to: https://lnkd.in/gKadBq7Z

The newly released TECHCET Critical Materials Reports™ on Lithography Materials contains details on market and technology trends and supplier profiles. For the full table of contents or to request a sample report, visit https://lnkd.in/esXU6SW

Want to receive more market updates? Sign up for our mailing list here: https://lnkd.in/ggMAbXS

ASML's New Chapter: Navigating Tech Innovation and Geopolitical Shifts Under Christophe Fouquet's Leadership

In an era of significant technological and geopolitical changes, ASML, the number one player in the semiconductor industry, stands at a crossroads. The forthcoming retirement of Martin van den Brink and Peter Wennink, who have jointly steered ASML for over a decade, signals the end of a dynamic period. Van den Brink's leadership in technology development propelled ASML to unparalleled heights in the lithography sector, while Wennink’s diplomatic and financial acumen solidified its market dominance. ASML's impact extends beyond technology; it has become a geopolitical force, enhancing the Netherlands and Europe's strategic significance in global politics.

The appointment of Christophe Fouquet as the incoming CEO heralds a new era. Fouquet faces the challenge of maintaining ASML's technological edge while adapting to a market nearing the limits of Moore's Law. 

As ASML approaches its 40th anniversary in April 2024, it confronts a changing landscape. The company has weathered various phases – from early struggles to market leadership, marked by innovations like the PAS 5500 and immersion lithography. Under Van den Brink, ASML prioritized technological advancement, often at the expense of other factors like reliability.

The appointment of Christophe Fouquet as the incoming CEO heralds a new era. Fouquet faces the challenge of maintaining ASML's technological edge while adapting to a market nearing the limits of Moore's Law. The shift in focus from chip performance to system-level advancements requires a nuanced approach. Additionally, as technology matures, reliability and predictability become crucial for maintaining ASML's competitive edge.

The transition from a "firefighter" engineering culture to one emphasizing process and reliability won't be easy. Fouquet must balance innovation with operational efficiency, ensuring ASML remains responsive to market and geopolitical dynamics. This requires a departure from the legacy of Van den Brink, focusing instead on a holistic, structured approach to development and engineering.

Fouquet's tenure will be pivotal in shaping ASML's future. His leadership must navigate the complexities of a highly competitive industry, geopolitical pressures, and the evolving technological landscape. The challenge lies in fostering a culture that values reliability and process without stifling the innovative spirit that has been ASML's hallmark. As the company moves into its fifth decade, its ability to adapt and evolve under Fouquet's guidance will determine its continued success in a rapidly changing world.

Advancing the Microchip Revolution: EUV Lithography's Challenges and Future Outlook

Extreme Ultraviolet (EUV) lithography represents a significant advancement in semiconductor manufacturing, enabling the production of more compact and efficient integrated circuits, particularly for 7 nm Logic process nodes and below and leading edge DRAM. This technology, developed and marketed primarily by ASML Holding, uses a highly specialized process involving laser-pulsed tin droplet plasma to etch patterns onto substrates at the 13.5 nm wavelength scale. The progression from early prototypes to more efficient models has been remarkable, with modern EUV systems capable of handling 200 wafers per hour, a substantial improvement from initial prototypes.

Looking into the future, EUV lithography is expected to play a critical role in advancing semiconductor technology, especially as the demand for smaller and more powerful chips increases. However, several technological challenges need addressing continiously to fully harness EUV's potential:

1. Optical Component Durability: The EUV process requires highly specialized and sensitive optical components, including mirrors and photomasks. These components are prone to degradation from exposure to high-energy photons and contaminants. Improving their durability and developing efficient cleaning and maintenance processes are crucial.

2. Throughput Efficiency: While significant improvements have been made, further enhancing the throughput of EUV systems is vital. This includes reducing setup times, increasing the speed of the lithography process, and minimizing downtime due to maintenance or component replacement.

3. Pattern Fidelity and Defect Reduction: As circuit patterns become increasingly smaller, maintaining pattern fidelity and reducing defects is challenging. This involves improving the resolution of EUV systems, enhancing photoresist materials to better respond to EUV exposure, and developing more effective methods to mitigate the impact of secondary electrons generated during the lithography process.

EUV Lithography - Balancing Technological Advancements with Energy Challenges

EUV lithography, pivotal in advanced semiconductor manufacturing, faces significant energy consumption challenges. The generation of EUV light, typically via laser-pulsed tin plasma, is inherently energy-intensive. Additionally, maintaining the necessary vacuum environment and cooling systems for these high-precision machines further escalates energy use. As EUV technology becomes more prevalent, especially for producing smaller, more efficient chips, optimizing energy efficiency is critical. Future developments are expected to focus on more efficient light sources, improved system design for energy conservation, and advanced thermal management, aiming to reduce the overall energy footprint of EUV lithography processes.

The semiconductor industry, traditionally known for its high environmental impact, is increasingly embracing sustainability. With the global demand for semiconductors rising, manufacturers face the challenge of scaling up production while addressing substantial water and electricity usage and managing hazardous waste from gases used in manufacturing. Historically, the focus has been on balancing power, performance, and cost. Recently, however, sustainability has emerged as a crucial consideration, with many facilities actively working to decarbonize their supply chains and reduce overall environmental impact (data from imec)

EUV Lithography's Hydrogen Demand: A Growing Concern in Chip Manufacturing

EUV Lithography, also raises concerns regarding its significant hydrogen consumption. The EUV process relies heavily on hydrogen gas to maintain the cleanliness of the optical elements, particularly for preventing tin deposition on the mirrors. The need for a continuous supply of hydrogen to facilitate this cleaning process contributes to the overall operational costs and resource demands of EUV systems. As EUV technology becomes more widespread in chip manufacturing, addressing the sustainability and efficiency of hydrogen usage will be essential, both from an environmental and economic perspective.

In EUV lithography, managing hydrogen usage presents distinct challenges. The technology requires hydrogen for removing contaminants from critical mirrors, demanding systems capable of handling high volumes while maintaining vacuum integrity. This necessity places a premium on innovative system designs that minimize the footprint and energy consumption associated with hydrogen management, directly impacting the cost and efficiency of semiconductor manufacturing. Safety considerations, given hydrogen's flammability, are paramount. Advanced, fuel-free hydrogen management strategies are employed to ensure safety and environmental compliance. These strategies focus on reducing flammability risks and eliminating the need for additional fuels, thereby minimizing carbon emissions and contributing to sustainable manufacturing practices.

Continued research and development in these areas are essential for the advancement of EUV lithography, ensuring it meets the rapidly evolving demands of the semiconductor industry.

Sources: 

Christophe Fouquet’s ASML must reinvent itself – Bits&Chips (bits-chips.nl)

www.imec.be

www.edwards.com

Wikipedia

2023 update to IRDS roadmap reminds key EUV issues.

1. EUV dose triples every four nodes => increasing electron blur?
2. EUV cannot replace multiple patterning, even with higher NA.https://t.co/hZzkfKGfyr

— Fred Chen (@DrFrederickChen) December 28, 2023

Breakthrough in Digital Lithography by Applied Materials and Ushio Boosts AI Computing Power

Ushio, Inc. have announced a significant strategic partnership, marking a new era in digital lithography technology. This collaboration aims to spearhead the transition to heterogeneous chiplet integration on large substrates like glass, a move crucial for advancing Artificial Intelligence (AI) computing capabilities.

This new digital lithography system, pioneered by Applied Materials and Ushio, is tailor-made for patterning advanced substrates vital in the AI era. With the growing demand for AI workloads, there's an increased need for larger, more functional chips. Traditional methods can't keep up with AI's performance requirements, hence the shift to heterogeneous integration (HI) techniques. These involve combining multiple chiplets in an advanced package, offering performance and bandwidth comparable to monolithic chips.

The partnership leverages Applied Materials' expertise in large substrate processing and Ushio's experience in lithography for packaging. Dr. Sundar Ramamurthy from Applied Materials highlights the new Digital Lithography Technology (DLT) as a game-changer for customers' advanced substrate roadmaps. William F. Mackenzie of Ushio emphasizes their long-standing experience in lithography systems and their commitment to this new venture.

The DLT system stands out as the only technology capable of achieving the necessary resolution for advanced substrate applications while maintaining high-volume production throughput. It can pattern line widths less than 2-microns, allowing unprecedented area density for chiplet architectures on various substrates, including glass.

Applied Materials is responsible for R&D and creating a scalable roadmap for the DLT system, aiming to push innovation in advanced packaging to 1-micron line widths and beyond. Ushio will use its established manufacturing and customer infrastructure to facilitate the technology's adoption.

While this announcement is forward-looking and subject to the usual risks and uncertainties of the tech industry, it heralds a new chapter in computing technology, potentially transforming the landscape of high-performance computing in the AI era.

- Applied Materials, Inc. is a leader in materials engineering solutions, essential in producing new chips and advanced displays worldwide.

- Ushio, Inc., established in 1964, specializes in manufacturing and selling various light sources and optical equipment, with a significant presence in industrial processes and visual imaging.

For more information or media inquiries, contact Ricky Gradwohl for Applied Materials and the Corporate Communication Department for Ushio. 

Photos and more details are available on here Breakthrough Digital Lithography Technology From Applied Materials and Ushio to Enable More Powerful Computing Systems for the AI Era | Applied Materials.

ASML's 2023 Outlook: Surging Ahead in Semiconductor Equipment Despite Challenges and Export Controls

In 2023, ASML, the leading semiconductor lithography equipment supplier, is set to achieve remarkable success, outpacing its rivals and emerging as the number 1 provider of Wafer Fabrication Equipment. Boasting an impressive 30% revenue growth forecast for the year, ASML is thriving amidst an industry landscape marked by its consistent performance. With a substantial backlog of cutting-edge Deep Ultraviolet (DUV) and Extreme Ultraviolet (EUV) systems and surging demand from China, ASML's growth continues despite hurdles like supply chain disruptions and regulatory changes, ASML remains a beacon of innovation and resilience in the semiconductor sector.

By Abhishek Kumar Thakur and Jonas Sundqvist

ASML, a leading supplier of semiconductor equipment, is poised for a significant year in 2023, projected to surpass Applied Materials (AMAT) as the top provider of Wafer Fabrication Equipment. This achievement is attributed to ASML's robust revenue growth, expected to reach a remarkable 30% increase in 2023, while Applied Materials faces a decline of 20% according to Seeking Alpha*. ASML's success can be attributed to a substantial backlog of Deep Ultraviolet (DUV) and Extreme Ultraviolet (EUV) systems, driven by heightened demand in China.

* Fact check: Due to strong DUV revenue and despite the increased uncertainties, ASML expects strong growth for 2023 with a net sales increase towards 30% and a slight improvement in gross margin, relative to 2022. ASML Holding revenue for the twelve months ending June 30, 2023 was $27.293B, a 25.97% increase year-over-year. AMAT revenue is estimated to increase by 2.6% to 26.33 B. Meaning ASML would pass bu end of 2023.

https://finance.yahoo.com/quote/AMAT/analysis/ 

Despite facing challenges like supply chain disruptions and a factory fire, ASML has consistently ranked among the top three semiconductor equipment suppliers since 2017. Their backlog of EUV systems, combined with growing acceptance of DUV tools, contributes to their strong performance.

However, potential headwinds include supply chain concerns, past issues like the Berlin factory fire, and looming sanctions affecting exports to China. While ASML has addressed some challenges, the possibility of US sanctions in 2024 poses a threat to its growth.

Furthermore, ASML now faces new export controls imposed by the Netherlands, impacting shipments to China. While the company downplays these controls' immediate financial impact, they are expected to affect specific DUV systems, adding to global efforts to limit China's semiconductor advancements.

In this volatile landscape, ASML's ability to adapt to evolving regulations and maintain its technological leadership will be crucial. The impact of these restrictions, especially on shipments to China, could influence the company's growth trajectory in the semiconductor industry. Despite these challenges, ASML remains a prominent player with significant potential in the semiconductor equipment market.

ASML is set to deliver the industry's first High-NA extreme ultraviolet (EUV) lithography scanner by the end of 2023, marking a significant development for advanced chip manufacturing. The Twinscan EXE:5000 pilot scanner with a 0.55 numerical aperture (NA) will enable chipmakers to explore High-NA EUV technology. This innovation is crucial for achieving an 8nm resolution, suitable for manufacturing technologies beyond 5nm nodes. Intel is expected to be the first customer, but integration and adoption details are still uncertain. This advancement requires substantial investments, with reports suggesting costs of $300-400 million per unit.

To add some colour, initially, Intel had plans to employ ASML's High-NA tools for its 18A (1.8 nm) production node, scheduled for high-volume manufacturing in 2025, aligning with ASML's Twinscan EXE:5200 delivery. However, Intel accelerated its 18A production, moving it to the latter part of 2024. This change in strategy involved the use of ASML's Twinscan NXE:3600D/3800E with two exposures and Applied Material's Endura Sculpta pattern-shaping system. The objective was to reduce reliance on EUV double patterning techniques. Applied Materials' Centura Sculpta is a pattern-shaping machine equipped with a unique algorithm that can manipulate patterns produced by an EUV scanner. It has the capability to stretch these patterns in a user-defined direction along the X-axis. This process effectively reduces the space between features and enhances pattern density. This means that moving ahead ASML and Applied Materials are entering an interesting competitive space previously not encountered.

ASMLs Products

As an background, ASML specializes in the production of cutting-edge lithography systems crucial for semiconductor manufacturing. Their product portfolio includes the following key offerings:

Extreme Ultraviolet (EUV) Lithography Machines: ASML's EUV lithography machines are at the forefront of semiconductor manufacturing technology. These machines use extremely short wavelengths of light to create intricate patterns on silicon wafers, enabling the production of advanced and smaller semiconductor chips. EUV technology is essential for next-generation processors and memory chips.

Deep Ultraviolet (DUV) Lithography Machines: DUV lithography systems are another vital component of ASML's product lineup. They use longer wavelengths of light compared to EUV and are employed for a wide range of semiconductor applications, including memory and logic chip production. ASML's DUV systems are known for their precision and reliability.

TWINSCAN Series: Within the DUV lithography category, ASML offers the TWINSCAN series, which includes machines like the TWINSCAN NXT:2000i, NXT:2050i, and NXT:2100i. These systems are designed for immersion lithography, where the wafer and the lens are submerged in a liquid, enhancing precision and resolution.

EUV High Numerical Aperture (NA) Systems: ASML has been advancing its lithography machines by increasing the numerical aperture (NA), a key parameter that affects resolution. High-NA systems are capable of printing even smaller features on semiconductor wafers, enabling the production of highly advanced chips.

ASML's lithography machines are considered critical infrastructure for semiconductor manufacturing, and the company's technological leadership in this area has positioned it as a dominant player in the industry. The company's ability to innovate and adapt its lithography systems to meet the ever-increasing demands of semiconductor manufacturers has been a key factor in its success and growth prospects. However, the recent export controls and geopolitical pressures, particularly concerning shipments to China, introduce additional challenges and uncertainties for ASML and its specialized products.

Sources:

ASML Hit With New Dutch Limits on Chip Gear Exports to China - Bloomberg

ASML To Top WFE Semiconductor Equipment In 2023, Topping Applied Materials | Seeking Alpha

ASML to ship first pilot tool in its next product line in 2023, CEO says | Reuters

ASML to Deliver First High-NA EUV Tool This Year (anandtech.com)

EUV Alternative Speeds Up Chip Production - EE Times

BALD Engineering - Born in Finland, Born to ALD: ASML Remains on Track to Deliver High NA EUV Machines in 2023

BALD Engineering - Born in Finland, Born to ALD: Netherlands' chip tool export controls take effect for DUV Lithography and ALD

BALD Engineering - Born in Finland, Born to ALD: Applied Materials’ Pattern-Shaping Technology - Centura Sculpta

An Update on Directed Self-Assembly (DSA) for Advancing Micro and Nano Fabrication

Revolutionizing fabrication, Directed Self-Assembly (DSA) innovates micro to nano devices and materials. It leverages block co-polymer morphology for precise patterns and guides micro/nano particles, enhancing manufacturing. In semiconductors, DSA addresses lithography challenges, while Imec's research showcases DSA-EUV synergy for defect-free outcomes. Complex rectification processes, illustrated by Imec, spotlight improved Critical Dimension Uniformity and Pattern Placement Error control. As DSA advances, its collaboration with EUV promises precision, efficiency, and innovation across industries.

DSA has emerged as a groundbreaking technique for mass-producing micro to nano devices and materials with precision and efficiency. This method harnesses the inherent properties of materials to assemble them into intricate structures, revolutionizing manufacturing processes across various industries.

DSA leverages block co-polymer morphology to create patterns, enhancing feature control and shape accuracy. This involves guiding the assembly of micro and nano particles to achieve desired structures, made possible by the precise control of surface interactions and polymer thermodynamics. The key advantage of DSA is its ability to create structures at remarkably small scales, enabling advancements in diverse fields.

In the semiconductor industry, DSA offers a new perspective on lithography challenges. Despite initial setbacks, DSA is being revisited to address critical issues such as stochastic defects in extreme ultraviolet (EUV) lithography. These defects, which can contribute significantly to patterning errors, have led semiconductor manufacturers to explore DSA as a solution to rectify these problems. Notably, DSA is not replacing traditional methods but rather enhancing them. It is being integrated with existing manufacturing processes to enable increased resolution and precision, all while reducing costs.

However, challenges persist in integrating DSA into high-volume manufacturing. Defect control remains a primary concern, as the technology strives to meet industry standards of minimal defectivity. Common defects include line bridging, collapse, bubbles, and dislocations. Efforts are ongoing to optimize annealing temperature, etching methods, and film thickness to reduce these defects. Another challenge is the complexity of pattern inspection, which demands accurate metrology methods. Researchers are exploring machine learning-based approaches to automate the inspection process and achieve higher throughput.

Despite these challenges, DSA is being applied to various applications beyond semiconductors. Tissue engineering benefits from the precision of directed assembly, enabling the controlled organization of cells into desired micro-structures. In nanotechnology, DSA facilitates the creation of precise nanostructures, leading to advancements in areas such as graphene nanoribbon arrays and thin-film quantum materials.

Revolutionizing EUV Lithography with Directed Self-Assembly (DSA)

EUV lithography has revolutionized semiconductor manufacturing but comes with its share of challenges, particularly in addressing line roughness and stochastic defects. DSA has now gained attention as a potential game-changer to tackle these issues in EUV lithography.

Recent research from Imec sheds light on the promising synergy between EUV and DSA in overcoming lithography challenges. In the study titled "EUV Lithography Line Space Pattern Rectification Using Block Copolymer Directed Self-Assembly: A Roughness and Defectivity Study," led by Julie Van Bel and team, the researchers explored the combination of DSA with EUV. Their findings indicate that this integration surpasses DSA processes based on Immersion lithography, offering lower line width roughness and freedom from dislocation defects.

Another study, "Mitigating Stochastics in EUV Lithography by Directed Self-Assembly," led by Lander Verstraete and collaborators, delved into the application of DSA to mitigate stochastic defects in EUV processing.

Imec's approach to rectify defects in EUV lithography involves intricate processes, as illustrated in Figures below. In the top Figure, the team outlines the process for rectifying defects in EUV Line/Space Patterns using DSA. Meanwhile, the lower Figure details the rectification process for defects in EUV Contact Patterns.

Imec's approach to rectify defects in EUV lithography involves intricate processes, as illustrated in the figures below. In the top figure, the team outlines the process for rectifying defects in EUV Line/Space Patterns using Directed Self-Assembly (DSA). Meanwhile, the lower figure details the rectification process for defects in EUV Contact Patterns. These illustrations highlight the potential of DSA in enhancing lithographic precision, addressing challenges related to line roughness and stochastic defects, and achieving improved Local Critical Dimension Uniformity (LCDU) and Pattern Placement Error control in semiconductor manufacturing.

The results are particularly promising for line/spaces at a 28nm pitch, primarily addressing bridge defects. However, at a 24nm pitch, further improvement is necessary due to an excess of bridge defects. Notably, the type and frequency of defects correlate with the formulation of the block copolymer and the duration of the annealing process.

For contact arrays, the combination of EUV and DSA demonstrates improved Local Critical Dimension Uniformity (LCDU) and Pattern Placement Error. This advancement also enables the use of a lower dose, contributing to enhanced precision and efficiency in semiconductor manufacturing.

Imec's research underscores the potential of DSA to revolutionize EUV lithography by addressing line roughness and stochastic defects. The successful integration of EUV and DSA holds the promise of enhancing semiconductor manufacturing processes, achieving higher precision, and enabling the production of advanced devices with improved quality. As researchers continue to refine these methods, the collaboration between EUV and DSA is set to shape the future of lithography and microfabrication.

In conclusion, DSA is revitalizing micro and nano fabrication by offering accurate and efficient methods for mass production. While challenges like defect control and metrology persist, DSA's potential to shape the future of industries such as semiconductors, biomedicine, and nanotechnology is undeniable. As research continues to refine DSA processes and overcome hurdles, its role in advancing technology and innovation is set to expand further.

Directed Self-Assembly Finds Its Footing (semiengineering.com)

SPIE 2023 – imec Preparing for High-NA EUV - SemiWiki

Directed assembly of micro- and nano-structures - Wikipedia

Canon, SCREEN and Tokyo Electron to join Japan advanced chipmaking project for 2nm

Canon has partnered with Tokyo Electron and Screen Semiconductor Solutions to develop advanced chipmaking production technology with support from the Japanese government according to a report by Nikkei Asia.

♦ The $386mil USD funding from the Japanese government is through the National Institute of Advanced Industrial Science and Technology, along with the Ministry of Economy, Trade and Industry (METI).

♦ Japans semiconductor production industry has lost ground in recent years to Taiwanese chipmakers and companies like Intel.

The goal is to develop and implement a 2-nanometer or smaller process for chips by the mid-2020s.

Source (Paywall): LINK

Tokyo Electron semiconductor fab professionals shuffling wafers (credit: Tokyo Electron)

Master Thesis in Nanotechnology with Alixlabs in Sweden on Atomic Level Fragmentation

Come and join us in Lund Sweden for an exciting Master Thesis in Atomic Level Fragmentation - the new option for extending optical lithography cheaper, greener, and faster than any advanced multi-patterning scheme!

Operating within Lind Nano Lab we guarantee a safe & flexible workplace under ISO 5 and ISO 7 Cleanroom conditions, 24/7 operation, and remote working from wherever you need to be when outside the cleanroom.

Lund Nano Lab : LINK

Thesis description and application : LINK

View across The Science City of Lund in South Sweden direction Copenhagen in Denmark across the straight of Öresend connected by the longest bridge in Europe.