Atomic Layer Etching as a Scaling Enabler: From Isotropic Chemistry to Selective, Directional, and Geometry-Driven Patterning

Continued scaling in semiconductor manufacturing increasingly relies on atomic-scale control of etching for complex 3D material stacks, making patterning precision a growing industrial bottleneck. Atomic layer etching (ALE) has emerged as a key enabler, with plasma-driven anisotropy and surface-chemistry control allowing improved selectivity and profile fidelity for advanced logic and memory integration. Current approaches emphasize decoupling surface modification from material removal to enable low-temperature, highly controlled processes.

From an industry perspective, the focus is shifting toward systematic ALE process development frameworks that combine thermodynamic screening, tailored half-cycle chemistries, and experimental verification of etch rates and selectivity. These strategies are increasingly relevant as device architectures push beyond conventional materials and dimensions. At the same time, ALE is gaining attention for its potential to reduce process complexity, energy use, and chemical consumption, positioning it as both a scaling and sustainability enabler for future semiconductor manufacturing.

In a recent paper by Smith et al (reference below), Thermal ALE is described as a purely chemical, vapor- or gas-phase process in which both the surface modification and removal steps are self-limiting and thermally activated. Volatile products are typically formed through ligand-exchange reactions that generate metalorganics. Because no ions are involved, this mode of ALE is intrinsically isotropic, leading to uniform material removal in all directions. This makes thermal ALE attractive for conformal trimming, lateral recessing, and highly selective etches, but fundamentally limits its ability to produce vertical, profile-controlled features.

(a) Periodic table of the elements showing which metals, metal oxides, and metal nitrides have had ALE processes developed for them. In developing a new ALE process, determining the nature of the volatile etch product is critical, with some metals proving more favorable to etching via the formation of volatile metalorganics and others via volatile metal halides. Data compiled from the ALE Database [reference]. (b) An outline of the pathways by which reported ALE processes can proceed. Metals, metal oxides, and metal nitrides can be halogenated, with the modified layer removed by subsequent Ar⁺ sputtering or ligand exchange. Metals can be oxidized or nitrided, and the metal oxide or nitride subsequently etched. (c) Gibbs free energy minimization and volatility diagram analysis can be used to theoretically screen possible etch processes. (d) Various surfaces of Ni modified with (1) surface O, (2) mixed surface and subsurface O, and (3) subsurface O. The Gibbs free energy of reaction showed the importance of having an oxidized sublayer to achieve favorable thermodynamic etching. Adapted from ref [reference]. (e) Analysis of Gibbs free energy of reaction: nitridation of nickel could form metastable Ni3N, which can be etched through favorable reactions with formic acid, forming dimers of nickel formates. by Smith et al (reference below)

In contrast, plasma ALE introduces ions as an active control parameter, most commonly during the removal step. A plasma first forms a chemically modified surface layer, such as a halogenated or oxidized film, which is then selectively removed by directional ion bombardment within a narrow ALE energy window. The momentum of the ions provides anisotropy, enabling vertical etching with atomic-scale precision while suppressing continuous sputtering. This directionality comes at the cost of tighter process windows and increased sensitivity to ion-induced damage.

A hybrid plasma–thermal ALE approach is presented as a way to decouple anisotropy from volatilization chemistry. In this scheme, plasma exposure is used to directionally modify the surface or precisely control the thickness of the modified layer, while removal proceeds via isotropic, thermally driven ligand-exchange reactions. This allows anisotropy to be engineered through selective surface modification rather than sputtering alone. Overall, the key conclusion is that isotropic versus directional behavior in ALE is determined by how and where ions are used, not simply by whether the process is labeled thermal or plasma.

Comment on Geometry

From an industrial standpoint, atomic layer etching is emerging as a core patterning technology as device scaling shifts toward complex 3D architectures and heterogeneous material stacks where conventional plasma etching reaches its limits. Smith et al. highlight that future adoption will be driven by selective ALE, enabled by surface-chemistry engineering, controlled anisotropy, and precise balance between etching and deposition rather than brute-force sputtering. In this landscape, AlixLabs’ use of geometrical selectivity extends the ALE paradigm by exploiting feature pitch and local geometry as an additional selectivity axis, enabling pattern multiplication and critical dimension scaling without added lithography complexity. The convergence of chemical, directional, and geometrical selectivity positions ALE not as a niche technique, but as a scalable, cost- and sustainability-aligned solution for next-generation semiconductor manufacturing.

The relevance of these advances is underscored by their recent and upcoming exposure at major industry forums. Results demonstrating sub-10 nm, high-aspect-ratio patterning with APS™ were presented at the 248th Electrochemical Society (ECS) Meeting in October 2025, marking an important milestone in validating the technology on bulk silicon using mature lithography. This momentum continues at SPIE Advanced Lithography + Patterning 2026, where AlixLabs will present new APS™ results spanning nanoimprint lithography and simplified self-aligned quadruple patterning, including joint work with UMC. Together, these events signal APS™ and geometrically selective ALE moving from concept and lab validation toward broader industrial evaluation and integration.

AlixLabs announced that Dr. Dmitry Suyatin, CIPO and Co-Founder, presented new APS™ (Atomic Layer Etching Pitch Splitting) results at the 248th ECS Meeting in Chicago (October 12–16, 2025), demonstrating high-aspect-ratio, narrow-fin patterning on bulk silicon with critical dimensions below 10 nm using standard 193-nm immersion lithography. The results reinforce APS™ as a viable path to advanced logic patterning without next-generation scanners, enabling reduced process complexity and cost. Supported by recent patent milestones and progress toward a beta tool planned for operation in fall 2026, APS™ is positioned to move from lab-scale validation toward production-grade refinement, aligning with AlixLabs’ goal of making advanced semiconductor manufacturing more accessible and sustainable.

AlixLabs announced its participation at SPIE Advanced Lithography + Patterning in San Jose, where two abstracts by Reza Jafari Jam et al and Robin Athlé et al have been accepted for oral presentation, including one in collaboration with United Microelectronics Corporation (UMC). The presentations will showcase recent progress in APS™ (Atomic Layer Etching Pitch Splitting), demonstrating sub-13 nm half-pitch patterning on silicon and a simplified alternative to self-aligned quadruple patterning that delivers a 4× density increase using a streamlined three-step process. Together, the talks highlight APS™ as a precise, cost-effective, and more sustainable approach to advanced nano-patterning that reduces complexity compared with conventional multi-patterning schemes.

Reference:

AlixLabs – News

Adapted from Smith, T. G. and Chang, J. P., Atomic Layer Etching in Patterning Materials: Anisotropy, Selectivity, Specificity and Sustainability, Plasma Chemistry and Plasma Processing, 46:9 (2026), © The Author(s) 2026. Published by Springer Nature and licensed under CC BY 4.0.

Smith, T. G., Chang, J. P., Atomic Layer Etching in Patterning Materials: Anisotropy, Selectivity, Specificity and Sustainability, Plasma Chemistry and Plasma Processing, 2026, 46:9.

Atomic Layer Etching in Patterning Materials: Anisotropy, Selectivity, Specificity and Sustainability | Plasma Chemistry and Plasma Processing

Intel Foundry Advances Future Logic Scaling with Manufacturable 2D Transistors and High NA EUV Integration

Intel Foundry has demonstrated concrete momentum in de-risking 2D field-effect transistors as a future scaling path beyond silicon, through long-term collaboration with Imec. Results presented at IEDM show a world-first, 300 mm fab-compatible integration of key 2DFET modules, including source/drain contacts and gate stacks, using transition-metal dichalcogenide channels (WS₂ and MoS₂ for n-type, WSe₂ for p-type devices). The core innovation is a selective oxide etch applied to high-quality Intel-grown 2D layers capped with AlOx/HfO₂/SiO₂, enabling damascene-style top contacts while preserving the integrity of atomically thin channels. 

Fab-compatible 2D FET process integration on 300 mm wafers, demonstrating selectively recessed oxide caps that enable damascene-style top contacts on WS₂, MoS₂, and WSe₂ channels, along with replacement-oxide gate stacks and interlayer-selective removal that scales gate CET from 2.5 nm to 1.5 nm. The work establishes manufacturable contact and gate modules as fundamental building blocks for future 2D transistor integration (IEDM Paper 10.1, Q. Smets et al.).

By validating these processes in production-class integration flows, Intel Foundry is addressing two of the most critical barriers to 2D transistor adoption—contact resistance and gate integration—while enabling realistic benchmarking, modeling, and design pathfinding. This work showcases Intel Foundry’s strategy of emphasizing manufacturability early in research, positioning 2D transistors as a credible, scalable option for future logic nodes and stacked transistor architectures.

Fab-compatible 2D FET process integration demonstrated on 300 mm wafers. An imec-led research team reports new manufacturable process modules enabling scalable integration of 2D field-effect transistors in a 300 mm pilot line. Exploiting the strong chemical selectivity and anisotropic van der Waals structure of transition-metal dichalcogenides, the work demonstrates for the first time a selectively recessed oxide cap that enables damascene-style top contacts on monolayer WS₂, MoS₂, and multilayer WSe₂ channels, resulting in improved contact resistance. A replacement-oxide gate stack with scaled equivalent oxide thickness is also shown. In addition, a novel interlayer-selective removal process based on liquid intercalation reduces the top-gate capacitance-equivalent thickness from 2.5 nm to 1.5 nm. Together, these modules form fundamental building blocks for future 2D integration technologies. Top row: epitaxial TiN growth enabled by a 2D template (left, center) and chemical confirmation of a Ru top contact on a multilayer WSe₂ channel (right). Bottom row: schematic comparison of the baseline top-gate stack comprising interlayer, cap, and top-up oxides; full replacement-oxide process; and selective lateral interlayer removal from contact trenches. Based on Paper 10.1, “Selective Etch Process for Fab-Compatible Top Contacts, Replacement Oxide and Interlayer Removal in 2D FETs,” Q. Smets et al., presented at IEDM.

In parallel with its 2D transistor research, Intel Foundry has made significant progress in High Numerical Aperture EUV lithography as a cornerstone enabler for future device scaling. In close collaboration with ASML, Intel Foundry has completed acceptance testing of the TWINSCAN EXE:5200B, the most advanced High NA EUV scanner currently available. This system builds on the first-generation EXE:5000 platform while extending productivity to 175 wafers per hour and achieving overlay performance of 0.7 nm, metrics that are directly relevant to high-volume manufacturing rather than purely experimental use. Intel’s early access to High NA EUV, beginning with the first commercial installation in its Oregon R&D fab in 2023, positions the company as a lead development partner shaping how High NA lithography is qualified, integrated, and eventually deployed in production logic nodes.

From a technology perspective, the EXE:5200B introduces several enabling innovations that are critical for advanced transistor architectures, including gate-all-around and future stacked devices. A higher-power EUV source supports practical exposure doses and improved resist process windows, helping control line edge and line width roughness at extremely small critical dimensions. A redesigned wafer stocker architecture improves lot logistics and thermal stability, which is especially important for multipass and multiexposure flows anticipated with High NA patterning. Finally, tighter alignment control reflects advances in stage mechanics, sensing, and environmental isolation, all of which become essential as overlay tolerances approach the sub-nanometer regime. For Intel Foundry customers, these capabilities translate into more flexible design rules, reduced reliance on complex multi-patterning schemes, fewer masks and process steps, and faster yield learning. Together, Intel’s High NA EUV progress and its 2D transistor integration work reflect a coherent strategy: pairing next-generation lithography with manufacturable device innovations to ensure that future scaling paths are both technically viable and production-ready.

Sources:

How Collaboration in High NA EUV and Transistor R&D Are Shaping Future Waves of Device Innovation

IEEE IEDM 2025 | 10-1 | Selective Etch Process for Fab-compatible Top Contacts, Replacement Oxide and Interlayer Removal in 2D FETs

The 2026 Area Selective Deposition Workshop (ASD 2026)

The ASD Workshop was initiated in 2016 to provide a scientific communication channel to learn and exchange about selective deposition techniques. It has since offered a forum for open discussions between researchers from academia and industry. The meeting will include one day of Tutorials followed by the Workshop at ETEC Building (University at Albany). The last day of the workshop will highlight the state of the art of SC devices and processes at NY state with invited presentation from our main industrial partners at the NY CREATES’ Albany NanoTech Complex.

The 2026 Area Selective Deposition Workshop (ASD 2026) will take place March 29-April 1, 2026, at the University at Albany in New York, but it will be in two different locations:

March 29-31, 2026: ETEC Building

April 1, 2026: NY CREATES’ Albany NanoTech Complex

Abstract submission: Abstracts

Samsung Researchers Achieve Near-Perfect Grain Orientation in Atomic Layer Deposited Ruthenium for Next-Generation Interconnects

Researchers at the Samsung Advanced Institute of Technology (SAIT) have unveiled a breakthrough in interconnect materials at IEDM 2025 with their paper “Grain-Orientation-Engineering of Atomic Layer Deposited Ruthenium Interconnect Technology.” As semiconductor scaling pushes below 10 nm, conventional copper wiring faces mounting resistance and reliability challenges. The SAIT team demonstrated that ruthenium (Ru), deposited via atomic layer deposition (ALD), can serve as a superior alternative by precisely controlling its crystallographic orientation. Through tailored ALD cycles, they achieved more than 99 percent texture quality in Ru films deposited on amorphous underlayers—an unprecedented level of structural order that dramatically reduces electron scattering at grain boundaries.

The study introduces a “supercycle-based area-selective deposition” approach that enables bottom-up via filling, producing c-axis-oriented single-crystal Ru vias. This method not only delivers void-free filling in narrow, high-aspect-ratio structures but also supports excellent conformality, making it highly compatible with advanced three-dimensional BEOL (back-end-of-line) architectures. By demonstrating atomic-scale control over film orientation and growth direction, the researchers show how ALD Ru can overcome the resistivity limitations of conventional PVD methods and outperform Cu in nanoscale interconnect applications.

Beyond resistivity improvements, the findings have broader implications for the semiconductor industry’s transition toward Ru-based interconnect schemes. A highly oriented ALD Ru process could simplify integration by minimizing the need for thick diffusion barriers and improving electromigration resistance. The work reinforces ALD’s growing importance not just for conformal coatings but as an enabler of crystallographic precision at the atomic level. Samsung’s demonstration positions ruthenium as a front-runner for sub-10 nm and 3D interconnect nodes—bridging the gap between conventional BEOL metals and the emerging era of atomic-scale device engineering.

Sources: 

IEEE IEDM 2025 | 33-6 | Grain-Orientation-Engineering of Atomic Layer Deposited Ruthenium Interconnect Technology

SAIT | Samsung Semiconductor Global

ASM Charts the Future of ALD: Scaling Innovation, Integration, and Intelligence Toward 2030

ASM used its 2025 Investor Day to set a bold 2030 ambition of more than €5.7 billion revenue, operating margins above 30%, and free cash flow above €1 billion. The company has consolidated a leading position in ALD with over 55% market share in their segments they where they chose to compete and is scaling its Epi business from 12% in 2020 to 25% in 2024. ALD remains the central growth driver, with the market for single-wafer ALD expected to outpace overall wafer fab equipment and reach $5.1–6.1 billion by 2030, while Si Epi is forecast at $2.5–3.2 billion with a 9–13% CAGR. 

The single-wafer ALD market is projected to grow strongly from about 3.0 billion dollars in 2024 to between 5.1 and 6.1 billion dollars by 2030, representing a 9–13 percent compound annual growth rate, outpacing the overall wafer fab equipment market, which is expected to grow at 6 percent annually from 110 billion dollars in 2024 to 155 billion dollars in 2030. This growth is driven by the increasing number of ALD layers required in leading-edge logic and foundry processes as well as in advanced DRAM, both in the cell and peripheral CMOS areas. By 2030, ASM aims to maintain a market share above 55 percent, sustaining its lead in logic and foundry while also expanding its position in memory.

Node and memory inflections significantly expand ASM’s served markets, adding $400 million in their served available market from 3nm FinFET to 2nm GAA, and a further $450–500 million from 2nm to 1.4nm, while DRAM transitions contribute another $400–450 million. FEOL ALD layers grow fastest, with roughly 60% of ALD demand at 1.4nm coming from the transistor front end. In advanced packaging, a total available market of $11.5 billion by 2030 supports ASM’s plan to double its served available market to more than 30% of that market. 

Services are projected to grow at more than 12% CAGR through 2030, with half of revenues moving to outcome-based models and new “dry clean” refurbish technology delivering ~10× selectivity, ~5× part life, over 95% CO₂e reduction, and more than 2× cost-of-ownership benefits. 

ASM also introduced its XP8E common platform integrating clean, treat, inhibit, and ALD steps for 2nm ASD flows, and highlighted AI/ML deployment in high-volume manufacturing for anomaly detection, predictive maintenance, and improved first-time-right performance.

ASM’s XP8E common platform is positioned as a key enabler for the 2nm and beyond era, where Area-Selective Deposition and advanced integration schemes require multiple tightly coupled process steps. By bringing clean, treat, inhibit, and ALD into a single cluster, XP8E reduces wafer handling, shortens cycle times, and improves process control. This integration is critical for scaling as the number of ALD steps grows with each node, and it directly addresses challenges in pattern fidelity, defectivity, and variability that can otherwise undermine yield at 2nm. The platform is designed to be modular and flexible, so customers can configure it for different ASD and high-k/metal gate flows, while also benefiting from a common hardware base that simplifies fab operations, service, and parts management.

Alongside new hardware, ASM is embedding AI and machine learning capabilities into high-volume manufacturing. These tools enable real-time anomaly detection to flag subtle deviations in process behavior before they impact yield, and provide “top contributor” insights that help engineers rapidly identify root causes. Predictive maintenance, including ASM’s PM-Bot automation, improves precision and ensures higher first-time-right rates, cutting downtime and labor intensity. Over time, this creates a closed-loop system where data from thousands of wafers continuously refines process windows, stabilizes tool performance, and enhances cost-of-ownership. In combination, XP8E’s process integration and AI-driven control systems aim to deliver the repeatability, selectivity, and productivity gains required for the 2nm transition and future GAA nodes.

ASMs ALD History - from 1974 to 2024, 50+ years of ALD

The timeline highlights key milestones in the history of ALD and ASM’s leadership in the field. It begins in 1974 with Dr. Tuomo Suntola’s invention of ALD, followed by the founding of Microchemistry in Helsinki in 1987. ASM entered the scene in 1998 with the release of its first 200 mm Pulsar tool and strengthened its position by acquiring Microchemistry from Neste in 1999 and securing Sherman PEALD patents in 2000. Growth continued with the acquisition of Genitech in 2004. In 2008, ASM’s Pulsar tool was recognized as Product of the Year, cementing its reputation. More recently, ASM expanded its product portfolio with the introduction of the dual-chamber Synergis ALD system in 2018, the XP8 quad chamber module in 2019, and the Prominis ALD and XP8E platform in 2024. Strategic acquisitions, such as Reno Sub-Systems in 2022, further enhanced ASM’s technology base, illustrating a steady path of innovation and consolidation in ALD leadership over five decades.

The timeline illustrates ASM’s journey in atomic layer deposition from its origins to modern platforms. ALD was invented by Dr. Tuomo Suntola in 1974, followed by the founding of Microchemistry in 1987. ASM entered the field with the release of its first 200 mm Pulsar tool in 1998, strengthened its position by acquiring Microchemistry from Neste in 1999 (Finland), and expanded its patent base with Sherman PEALD patents in 2000. Key milestones include the acquisition of Genitech (Korea) in 2004, industry recognition for Pulsar in 2008, the introduction of Synergis in 2018 and XP8 in 2019, and the acquisition of Reno Sub-Systems in 2022. Most recently, ASM launched the Prominis ALD and XP8E platform in 2024, underscoring more than 50 years of continuous innovation and leadership in ALD.

The Finnish angle in ASM’s ALD story is both historic and ongoing. Atomic Layer Deposition was invented in Finland in 1974 by Dr. Tuomo Suntola, originally called Atomic Layer Epitaxy. The technology was developed at Microchemistry Ltd., a Finnish company founded in Helsinki in 1987 under Neste. When ASM acquired Microchemistry in 1999, they started gaining the pioneering ALD patents, know-how, and expertise that underpin its leadership today. Finland continues to play an active role through the University of Helsinki and ASM’s Chemical Innovation Group in Helsinki, where precursor chemistry and process research are carried out in close collaboration with Finnish scientists. In this way, Finland provided both the origin of ALD for ASM and remains an important innovation hub supporting ASM’s growth and leadership.

The ASM Pulsar “HIG source” for solids (or the solid precursor delivery subsystem) is a core enabler for ASM’s ability to use low-vapor-pressure solid precursors in ALD. The original innovation from ASM Microchemistry has been further developed over decades and is now still a key technology on the new platform for Molybdenum ALD seen below. It involves a heated sublimation mechanism (sometimes mounted close to or integrated with the reactor), controlled inert gas valves, purge isolation, and precise flux control to feed vapor from a solid into the ALD chamber. The architecture seeks to avoid cold spots or condensation and maintain consistent, controllable precursor delivery pulses.

Genitech was a South Korean company specializing in plasma enhanced ALD and thin film deposition. ASM acquired the company in 2004 to expand its capabilities in plasma based processes and complement its existing thermal ALD portfolio. The acquisition gave ASM a stronger position in PEALD for applications such as high k dielectrics and metal gate stacks used in advanced logic and memory. Genitech’s technology was integrated into ASM’s Pulsar and subsequent platforms, helping establish ASM’s leadership in both thermal and plasma ALD.

ASM acquired Reno Sub-Systems in 2022. Reno is a US-based company specializing in RF power delivery systems and matching networks for plasma tools. Their solid-state RF technology is valued for faster response times, higher precision, and better process stability compared to legacy RF solutions. By integrating Reno’s subsystems into its platforms, ASM strengthened its capability in plasma-based ALD and PEALD, where fine RF control is critical for uniformity, repeatability, and advanced film properties.

Future Outlook

ASM ties its deposition processing capability to its tool portfolio—Pulsar, EmerALD, Synergis, Prominis, XP8E, and others—which are engineered with small-volume reactors, advanced plasma control, and integrated multi-step clustering (clean, treat, inhibit, deposit).

Looking ahead, ASM is uniquely positioned to remain the clear leader in atomic layer deposition as the semiconductor industry advances to 2nm and beyond. The company’s deep history in ALD, dating back to Dr. Tuomo Suntola’s invention in 1974, has evolved into a robust technology portfolio that now commands more than 55 percent market share where ASM chooses to compete. 

With single-wafer ALD forecast to nearly double in size by 2030 and outpace overall wafer fab equipment growth, ASM is set to capture outsized value from both logic and memory inflections. Its proven expertise in solid source precursor delivery, trailing back to the the Pulsar HIG sublimation system and F120 Microchemistry research reactors, now expands to new material capabilities such as molybdenum ALD for advanced node metallization. At the same time, ASM is broadening its impact through the XP8E common platform, which integrates multiple critical steps into one cluster with embedded AI and machine learning into high-volume manufacturing for real-time control. ASM’s combination of process innovation, equipment integration, and data-driven intelligence places the company at the center of semiconductor scaling, ensuring its leadership in enabling Moore’s Law through the next decade.

Sources:

ASM InvestorDay 2025

Breaking the Copper Bottleneck: Lam Research’s Mo-ALD ALTUS Halo Enables Next-Generation Hybrid Metallization

Lam Research now offers molybdenum (Mo) atomic layer deposition (ALD) with its ALTUS Halo platform, introduced in 2025 as the first high-volume ALD tool designed for Mo metallization. The system enables conformal and selective, bottom-up deposition of low-resistivity, void-free Mo films, targeting advanced logic, memory, and 3D NAND applications where conventional copper and tungsten interconnects face scaling and reliability limits. This positions Lam’s Mo-ALD as a key enabler for next-generation BEOL hybrid metallization schemes.

Current density of various metal/via schemes. Red and green areas indicate higher current density.  

Hybrid metallization using Mo shows strong potential to overcome the scaling limitations of conventional copper dual damascene (Cu DD) processes in advanced semiconductor BEOL interconnects. As device dimensions shrink, Cu faces challenges such as increased resistivity, barrier thickness limitations, and stress-induced voids (SIVs), all of which degrade performance. Mo hybrid metallization, which uses bottom-up barrierless metal deposition before a conventional Cu process, significantly reduces resistance—by about 55% compared to Cu DD—and further by 15% with selective barrier deposition (SBD). This lower resistance translates into higher current densities and improved reliability. Stress distribution studies also reveal that Mo hybrid vias exhibit lower void formation risks than Cu due to smaller stress gradients at the via/barrier interfaces.

Comparison of via and line resistance for conventional Cu dual damascene and Mo hybrid metallization schemes. Mo vias reduce total resistance by ~35% without selective barrier deposition (SBD), with an additional ~20% reduction when fully replacing Cu. Applying SBD further lowers resistance, achieving up to ~55% reduction compared to the Cu baseline.

Optimization studies, performed with SEMulator3D® simulations, identified key parameters like via critical dimensions, height, and material stress properties that impact resistance, capacitance, and hydrostatic stress. Findings show that increasing Mo via height lowers resistance but raises stress, suggesting an optimal fill height around 25 nm for balancing performance and reliability. Intrinsic stress of Mo and process temperature tuning were also shown to mitigate stress-induced reliability issues, with 400°C identified as a favorable condition. Ultimately, hybrid metallization with Mo offers a scalable path forward, combining electrical and mechanical benefits, while virtual DOE and process modeling enable predictive optimization without extensive wafer-based experiments.

Sources:

Breaking the Copper Bottleneck With Molybdenum Hybrid Metallization

Lam Research Ushers in New Era of Semiconductor Metallization with ALTUS® Halo for Molybdenum Atomic Layer Deposition - Feb 19, 2025

TSMC’s 2 nm Fabs Lock Out China OEMs, Securing ALD and Process Tool Demand for US, European, and Japanese Tier-1 Suppliers

TSMC’s decision to exclude Chinese equipment vendors from its 2 nm fabs in Taiwan and the US reshapes the competitive landscape in favor of Japanese, American, and European suppliers. With the 2 nm node set to become the largest in history by wafer volume and revenue potential, this policy shift effectively concentrates demand among a handful of Tier 1 players —ASMI, TEL, Applied Materials, and Lam Research—who already dominate in deposition, etch, and cleaning tools essential for nanosheet GAA and backside power delivery. No need to mention ASML.

Announced in January: TSMC is advancing with its 2 nm (N2) technology, establishing a pilot line at its Hsinchu Baoshan Fab 20 with an initial monthly output of around 3,000–3,500 wafers. By combining production from Hsinchu and Kaohsiung, the company expects to exceed 50,000 wafers per month by the end of 2025 and reach about 125,000 wafers per month by the end of 2026. Output at Hsinchu should rise to 20,000–25,000 wafers per month by late 2025 and 60,000–65,000 by early 2027, while Kaohsiung is projected to produce 25,000–30,000 wafers monthly by late 2025 and also expand to 60,000–65,000 by early 2027. Chairman C.C. Wei has highlighted that demand for 2 nm exceeds that of 3 nm, driven by its 24–35% lower power consumption, 15% performance boost at the same power, and 15% higher transistor density. Apple will be the first adopter, followed by MediaTek, Qualcomm, Intel, NVIDIA, AMD and Broadcom.

TSMC will start 2 nm mass production in Taiwan in the second half of 2025, initially with Fab 22 in Kaohsiung as the anchor site for yield learning. The first ramp is set at 40,000 wafers per month, expanding to 100,000 wafers per month in 2026 and reaching 200,000 wafers per month by 2027, making N2 the largest and most profitable node in TSMC’s history.

In the US, Arizona Fab 21 is being developed in phases. Phase 1 is already producing 4 nm chips, Phase 2 will start 3 nm by late 2025 or early 2026, and Phase 3 is planned for 2 nm and A16-class chips toward the end of the decade. This ensures that while Taiwan remains the cost-optimized base for N2 production, Arizona provides premium, subsidy-supported capacity for US customers, diversifying geographic and geopolitical risk.

Overall, Taiwan will carry the bulk of N2 output and cost efficiency, while Arizona secures local supply for strategic US clients like Apple, Nvidia, AMD, and Intel. By 2027, with 200,000 wafers per month globally, N2 alone could generate nearly $50 billion annually, cementing TSMC’s central role in powering AI and HPC expansion.

The move aligns directly with Washington’s Chip EQUIP Act, which ties subsidies to avoiding “foreign entities of concern.” By pre-emptively removing Chinese tools, TSMC safeguards its access to US incentives while giving its global customers—Apple, Nvidia, AMD, and Intel—assurance that supply chains are insulated from geopolitical risk. This codifies the leading suppliers as the “trusted” baseline for advanced-node capacity worldwide, effectively reinforcing their moat at the most profitable process node ever.

For ASMI, TEL, AMAT, and Lam, the outlook is very positive. With Chinese competitors pushed out, these companies can win more business and have stronger pricing power. At the same time, 2 nm wafer prices are climbing toward $30,000, far above older smartphone-focused nodes. TSMC is reviewing its suppliers for profit margins and China ties, but these four are essential for 2 nm production, so they are more likely to gain from rising demand and higher-value tools than lose ground. Put simply, the 2 nm era is set to drive lasting growth and profits for them as AI adoption accelerates through 2027.

Chinese semiconductor equipment OEMs that are cut out from TSMC’s 2 nm fabs under the new restrictions and supplier realignment:

• AMEC (Advanced Micro-Fabrication Equipment Inc.) – leading Chinese etch tool supplier, with relevance in dielectric etch and epitaxy
• Naura Technology Group – broad portfolio in etch, deposition, and cleaning tools
• Mattson Technology (China-owned, via E-Town Dragon Semiconductor) – focuses on dry strip, rapid thermal processing (RTP), and etch
• SMEE (Shanghai Micro Electronics Equipment) – China’s only domestic lithography tool maker (far behind in capability, but relevant in domestic fabs)
• Kingsemi – maker of ALD/CVD equipment, mainly for memory and advanced logic
• Piotech – deposition (CVD, PECVD, ALD) equipment vendor
• ACM Research (China) – cleaning and electrochemical deposition tools (though headquartered in the US, its operations are China-based and increasingly seen as China OEM)

At TSMC’s 2 nm fabs, the exclusion of Chinese equipment vendors channels ALD equipment demand entirely to US, European, and Japanese suppliers. ASM International (Europe) remains the clear leader in single-wafer ALD for high-k metal gate stacks and nanosheet spacers, with Applied Materials and Lam Research (US) competing in selective and plasma ALD for gate-all-around and backside power steps, while Tokyo Electron and Kokusai Electric (Japan) cover both single-wafer and batch ALD, particularly for spacer and liner deposition. By contrast, Chinese ALD players such as Naura, Kingsemi, and Piotech, while active in domestic logic and memory at 28–14 nm and some 7 nm non-EUV capacity, will not gain any capability at N2 and are explicitly excluded under TSMC’s supplier policy and US subsidy rules, leaving the largest and most profitable ALD opportunity in history to be divided among the established US, European, and Japanese Tier-1 suppliers.

Sources:

TSMC reportedly cuts Chinese chipmaking tools from 2nm fabs as suppliers face scrutiny due to emerging new US restrictions | Tom's Hardware

https://open.substack.com/pub/drrobertcastellano/p/tsmcs-2-nm-era-technology-leadership?r=l0uj0&utm_campaign=post&utm_medium=web&showWelcomeOnShare=false

TSMC Is Getting Ready to Launch Its First 2nm Production Line | TechPowerUp

Chipmetrics expands metrology portfolio with advanced test chips and wafer solutions for next-gen ALD semiconductor processes

Finnish metrology specialist Chipmetrics has expanded its portfolio with a new range of advanced test chips and wafer solutions aimed at accelerating prototyping and enhancing precision in next-generation semiconductor process development. The new releases include the ASD-1b area-selective deposition chip, a High Surface Area wafer, and pre-coated High Aspect Ratio test structures such as PillarHall and VHAR1. These tools are designed to simulate real-world manufacturing conditions with greater accuracy, helping engineers optimise processes more efficiently and reduce development cycles in ALD and other thin-film applications.

The ASD-1b chip provides a tricolour material layout with metal, SiO₂ and Si₃N₄ surfaces, enabling detailed assessment of selectivity and defectivity across multiple deposition techniques. Meanwhile, the new HSA wafer delivers up to 300 times greater surface area sensitivity through deep trench designs, supporting ultra-sensitive material studies. By offering pre-coated HAR structures, Chipmetrics addresses the growing industry demand for realistic conformality and uniformity testing. According to CEO Mikko Utriainen, these solutions are set to streamline benchmarking of new chemistries and processes, giving development teams faster, clearer feedback to advance semiconductor innovation.

Chipmetrics’ new metrology tools for advanced thin film process development. Left: Pre-coated high aspect ratio test structures, including PillarHall® (lateral AR > 1000) and VHAR1 (vertical AR = 200), for evaluating conformality and film penetration. Centre: The ASD-1b area selective deposition test chip with tricolour material layout for testing selectivity across Cu, SiO₂ and Si₃N₄ surfaces. Right: High Surface Area (HSA) wafer combining a 150 mm VHAR1 wafer within a 300 mm pocket wafer, providing up to 300× enhanced surface area for sensitive material studies.

Source:

Chipmetrics Expands Product Line with Advanced ALD Test Chips and Wafer Solutions - Chipmetrics

3rd and Last Call for Papers, and List of Speakers / Symposium on ALD & ALE Applications #21, at 248th ECS Fall Meeting / Oct. 12-16, 2025 in Chicago, USA

This fall, the 248th ECS Meeting will be held on Oct. 12-16, 2025 in Chicago (IL, USA), and is expected to gather some 3,000 participants and 40 exhibitors from both academia and industry.

The conference has a strong focus on emerging technology and applications in both solid-state science & technology and electrochemistry.

• General information and the Meeting Program can be found here: Important Information and Call for Papers.
• For more information about our annual symposium G01 and the conference website: Meeting Information. 

The organizers of symposium G01 on “Atomic Layer Deposition & Etching Applications, 21” encourage you to submit your abstract(s) on topics, comprising but not limited to: 

1. Semiconductor CMOS applications: development and integration of ALD high-k oxides and metal electrodes with conventional and high-mobility channel materials; 

2. Volatile and non-volatile memory applications: extendibility, Flash, MIM, MIS, RF capacitors, etc.; 3. Interconnects and contacts: integration of ALD films with Cu and low-k materials; 

4. Fundamentals of ALD processing: reaction mechanisms, in-situ measurement, modeling, theory; 

5. New precursors, delivery systems & sustainability issues; 

6. Optical, photonic and quantum applications; applications aiming at Machine Learning, Artificial Intelligence 

7. Coating of nanoporous materials by ALD; 

8. Molecular Layer Deposition (MLD) and hybrid ALD/MLD; 

9. ALD for energy conversion applications such as fuel cells, photovoltaics, etc.; 

10. ALD for energy storage applications; 

11. Productivity enhancement, scale-up and commercialization of ALD equipment and processes for rigid and flexible substrates, including roll-to-roll and spatial processing; 

12. Area-selective ALD; 

13. Atomic Layer Etching (‘reverse ALD’) and related topics aiming at self-limited etching, such as atomic layer cleaning, etc. 

FYI: Last year at the PRiME 2024 Meeting in Honolulu, our symposium G01 on ALD & ALE Applications 20 attracted some 80 participants, attending a full 3-days schedule with 50 presentations (42 oral, of which 16 invited, plus 8 poster presentations). We expect to be at least as successful this Fall in Chicago. 

Abstract submission 

Meeting abstracts should be submitted not later than the deadline of March 28, 2025 via the ECS website: Submission Instructions

Submission Instructions Invited speakers A list of invited speakers follows below: 

Visa and travel For extensive information, see last year’s version: VISA AND TRAVEL INFORMATION

In addition, ECS’ Francesca Di Palo (francesca.dipalo@electrochem.org) can provide you with an official participation letter issued by the Electrochemical Society. For (limited) general travel grant questions, please contact travelgrant@electrochem.org. 

As in the past years, we expect also our symposium to be able provide some partial travel allowance to selected speakers. We are looking forward to meeting you all at our symposium G01 on ALD & ALE Applications 21, in Chicago | Oct. 12-16, 2025!

TU Eindhoven and LONGi Advance ALD ZnO Passivating Contacts, Achieving 24.3 Percent Efficiency in Silicon Solar Cells

Atomic layer deposition of ZnO for contact passivation in silicon solar cells has emerged as a promising alternative to TOPCon technology, with the recent breakthrough of zinc oxide passivating contacts achieving 24.3 percent efficiency in a LONGi solar cell. This development builds on research led by Bart Macco’s group at Eindhoven University of Technology, which pioneered the concept of ZnO passivating contacts. The breakthrough was further demonstrated by LONGi, which successfully integrated the technology into high-efficiency solar cells.

Key advancements include the use of an interfacial SiO2 layer for passivation, Al2O3 capping to retain hydrogen during annealing, and selective Al2O3 removal to enable electrical contact while preserving passivation. The integration of a low-work-function LiF layer has improved contact resistivity, reducing the need for heavy silicon doping.

ALD ZnO offers lower-temperature processing, thinner layers around five nanometers, and elimination of toxic dopants compared to doped poly-Si in TOPCon. With potential advantages in scalability, industrial feasibility, and initial efficiency gains, ZOPCon could surpass TOPCon, though further research is needed to enable bifacial designs, optimize lateral conductivity, and enhance stability for large-scale production.

Sources

Passivating Contacts for Silicon Solar Cells: A Zinc Oxide Breakthrough? – Atomic Limits

Intel Unveils 6 nm Gate Length Silicon RibbonFET CMOS and Breakthroughs in Semiconductor Scaling at IEDM 2024

Intel Corporation / Intel Foundry has demonstrated and extensively characterized gate-all-around Silicon RibbonFET CMOS transistors with a 6 nm gate length (LG). The study showcases nanoribbon silicon thickness (Tsi) scaling down to 3 nm, enhancing short-channel effects without compromising performance. Effective workfunction engineering mitigates threshold voltage increases caused by quantum confinement at scaled Tsi, enabling reduced threshold voltage at highly scaled gate lengths. Injection velocity of 1.13x10^7 cm/s is maintained at LG=6nm without degradation down to Tsi=3 nm, highlighting advancements crucial for continued gate length scaling and the ongoing realization of Moore's Law.

Intel Foundry made groundbreaking announcements at the IEEE International Electron Devices Meeting (IEDM) 2024, showcasing advancements that propel semiconductor technology into the next decade and beyond. Highlights include innovations in transistor and interconnect scaling, advanced packaging, and emerging materials to support the industry’s roadmap toward achieving 1 trillion transistors on a chip by 2030. Intel demonstrated a 25% capacitance reduction using subtractive ruthenium for interconnections, achieved a 100x throughput improvement in advanced packaging through Selective Layer Transfer (SLT), and advanced gate-all-around (GAA) transistor scaling with Silicon RibbonFET CMOS at a 6 nm gate length. Additionally, Intel unveiled new work on gate oxide modules for scaled 2D FETs, addressing the next phase of GAA scaling.

Among the key technical breakthroughs, subtractive ruthenium stands out as a metallization alternative to copper for interconnects, offering significant capacitance reductions at tight pitches while being cost-effective and scalable for high-volume manufacturing. SLT further revolutionizes advanced packaging with ultra-fast, flexible chip-to-chip assembly, enabling smaller, higher-density chiplets for AI and other demanding applications. For transistor scaling, Intel’s demonstration of Silicon RibbonFET CMOS at 6 nm gate length delivers industry-leading short-channel effects and performance, paving the way for continued scaling under Moore’s Law. Additionally, Intel’s progress with 2D GAA NMOS and PMOS transistors and gate oxide development signals readiness for post-silicon semiconductor technologies.

Intel also highlighted progress in gallium nitride (GaN) technology, demonstrating the first 300 mm GaN-on-TRSOI substrates for high-performance power and RF electronics. These developments, alongside Intel’s continued focus on advanced memory integration, hybrid bonding, and modular system expansion, underscore its commitment to addressing challenges in AI, energy efficiency, and thermal management. With these innovations, Intel Foundry continues to lead the charge in semiconductor advancements, ensuring a robust path forward for the trillion-transistor era.

Source: Intel IEDM 2024 Innovations

Lam Research Sees Growth Opportunities in Etch and Deposition Technologies Despite NAND Downturn

In its Q1 2025 earnings call, Lam Research reported strong performance and emphasized growth opportunities, particularly in etch and deposition technology. CEO Tim Archer highlighted optimism for NAND spending recovery in 2025, supported by technology upgrades and a transition to molybdenum through Lam’s advanced Atomic Layer Deposition (ALD). Lam is positioned to capture opportunities in advanced semiconductor nodes like gate-all-around and EUV patterning, while its expanded offerings in high-bandwidth memory (HBM) and advanced packaging align with growing demand in AI and high-performance computing. Despite regulatory challenges in China, Lam continues to serve this market by focusing on upgrades and services. Looking ahead, Lam expects to outpace industry growth, driven by its strategic positioning across advanced technologies.

In its Q1 2025 earnings call, Lam Research Corporation (NASDAQ: LRCX) reported solid performance and reiterated optimism for growth in 2025, largely driven by demand for etch and deposition technologies. CEO Tim Archer emphasized Lam’s strategic positioning in an industry experiencing technological shifts, despite a prolonged downturn in NAND spending.

Lam anticipates a recovery in NAND spending in 2025, largely driven by technology upgrades rather than new capacity expansions. Key factors include a transition from tungsten to molybdenum in NAND structures, which improves performance by reducing resistivity. Lam is well-positioned in this area due to its extensive installed base and production wins, projecting an advantageous position as these upgrades scale into 2025.

NAND Technology Upgrades Set to Drive Etch and Deposition Demand in 2025

While the NAND segment has been in a prolonged downturn, Lam anticipates a recovery in 2025 as manufacturers upgrade to advanced nodes. The push toward 3D NAND layers exceeding 200 is essential to meet the growing demand for high-speed, high-capacity storage in data centers and client devices. Currently, about two-thirds of NAND capacity remains at older technology nodes, highlighting significant room for technology upgrades. Lam’s extensive installed base of NAND equipment positions it well to benefit as customers look to improve efficiency and performance.

Furthermore, Archer highlighted a shift from tungsten to molybdenum as a key materials change in NAND, addressing word line resistance challenges. This transition is particularly favorable for Lam, as it has already secured production wins in molybdenum deposition, which will scale up throughout 2025. These advancements are expected to enhance Lam's leadership position in NAND technology transitions.

Lam's product offerings mentioned in the reporting, along with their primary applications and strategic impacts.

Advanced Logic and Foundry Nodes: Key Growth Segments for Lam

Lam is also poised to benefit from shifts in advanced logic and foundry nodes, which are increasingly adopting gate-all-around architectures, backside power distribution, and advanced EUV patterning. These cutting-edge technologies require more intensive use of etch and deposition processes, aligning with Lam’s expertise and product offerings.

Archer noted the company's recent wins in selective etch tools and other innovations that support these advanced nodes, positioning Lam favorably as customers transition to architectures with greater power and performance needs. This expanding demand from foundry and logic customers offers a substantial growth opportunity for Lam’s advanced etch and deposition technologies.

Advanced Packaging Driven by AI Fuels Revenue Growth

The AI and high-performance computing boom has intensified demand for advanced packaging, particularly for high-bandwidth memory (HBM). Lam’s copper plating technology, SABRE 3D, has experienced substantial adoption, doubling its market share this year. This growth has been fueled by the rising complexity of 2.5D and 3D packages, which require high-performance interconnections to support AI-driven systems.

Lam anticipates this trend will continue into 2025 as the industry moves toward more advanced and intricate packaging solutions. According to Archer, advanced packaging will play a critical role in the semiconductor ecosystem for the foreseeable future, and Lam’s early investment in this technology has positioned it for continued market share gains.

Supporting Installed Base and Productivity in Memory Markets

Lam’s Customer Support Business Group (CSBG) has also shown growth, focusing on productivity enhancements and tool reuse. With Lam’s extensive tool installations in both DRAM and NAND, customers are prioritizing upgrades over entirely new systems, especially as they look to improve cost efficiency during NAND’s down cycle. This focus on tool reuse has led to recent market share gains for Lam, as existing tools are upgraded for better value than new installations.

As DRAM and NAND customers intensify efforts to reduce costs, Lam’s service-oriented model and productivity solutions, including equipment intelligence services, have seen greater adoption. This trend underscores Lam's ability to support its customers' evolving needs in an era of increased etch and deposition intensity.

Lam Research Leverages ALD for Moly Transition in NAND, Driving Next-Gen Semiconductor Performance

Lam Research's perspective on ALD is optimistic, particularly as it becomes increasingly essential in NAND technology upgrades. The company highlighted the industry's ongoing shift from tungsten to molybdenum (moly) for improved resistivity in 3D NAND structures, a transition that Lam’s ALD technology is well-positioned to support. Lam has already secured production wins for ALD applications with molybdenum, expected to ramp up significantly in 2025. This capability extends beyond NAND, with potential applications in DRAM and advanced logic/foundry nodes, underscoring ALD’s growing importance in meeting next-generation semiconductor demands.

Lam Research Adapts to Regulatory Challenges as China Revenue Set to Decline in 2025

In its Q1 2025 earnings presentation, Lam Research highlighted key developments and expectations for the China market. China accounted for roughly 37% of Lam's revenue in the September quarter, but the company anticipates this share will decrease to around 30% by December and potentially decline further in 2025. This projected downturn reflects both anticipated shifts in demand and the impact of U.S. export restrictions on advanced semiconductor equipment sales to China. Lam acknowledged the challenges posed by ongoing and potential new U.S. export controls, which could limit its ability to sell to certain advanced technology segments in China. Nevertheless, Lam remains committed to supporting its domestic Chinese customers within the boundaries of regulatory compliance, expecting demand in restricted segments to normalize as global WFE (wafer fabrication equipment) spending adjusts.

Much of Lam's business in China now focuses on servicing domestic fabs with tools for trailing-edge and specialty node processes, areas that generally remain unaffected by export controls. Through its Reliant product line, Lam continues to support these nodes, emphasizing upgrades and maintenance services as primary offerings in a market constrained by new advanced technology sales. Despite potential reductions in advanced equipment sales, the company is confident that its service and support model will help stabilize revenue in the region. By prioritizing productivity solutions and customer support, Lam is adapting to a complex regulatory environment while anticipating that China’s share of its revenue will gradually normalize amid a broader decline in WFE spending in the country.

Strategic Positioning in 2025 and Beyond

In summary, Lam Research is set to capitalize on a growing demand for etch and deposition technology driven by the industry’s shift to advanced architectures. Archer concluded the call with optimism, stating that the company is well-positioned to capture market share as the semiconductor industry increasingly relies on complex, three-dimensional structures. With its advanced product offerings, Lam expects to outperform overall wafer fabrication equipment (WFE) growth in 2025, strengthening its leadership across multiple semiconductor sectors.

New Export Controls on ALD, ALE and ASD Technologies Effective September 2024 to Safeguard National Security

The US Bureau of Industry and Security (BIS) is introducing* stringent export controls targeting advanced technologies essential to national security, particularly within the semiconductor, quantum computing, and additive manufacturing sectors. These controls include new and revised Export Control Classification Numbers (ECCNs) and specific restrictions on critical equipment and materials, such as those involved in Gate-All-Around Field-Effect Transistor (GAAFET) technology, Atomic Layer Etching (ALE), and Atomic Layer Deposition (ALD). The controls aim to safeguard U.S. technological leadership while harmonizing with international export control standards. Specific restrictions apply to high-precision wafer processing equipment and isotopically enriched materials used in quantum computing, reflecting the critical importance of these technologies. These measures ensure that while international collaboration continues, sensitive technologies remain protected under national security protocols.

BIS has introduced new export controls focused on advanced technologies, particularly in the semiconductor, quantum computing, and additive manufacturing sectors. These controls include new Export Control Classification Numbers (ECCNs), revisions to existing ones, and the addition of new license exceptions for countries with similar technical controls. This rule aims to protect national security and advance foreign policy objectives by aligning U.S. export controls with those of international partners. The controls cover a wide range of items, including quantum computing technologies and semiconductor manufacturing equipment, reflecting the critical importance of these technologies to national security. The rule is effective immediately, though there are delayed compliance dates for certain items, allowing businesses time to adjust to the new requirements.

BIS has also established a framework to differentiate between items controlled multilaterally and those controlled through Implemented Export Controls (IEC), which are harmonized with international partners. The new regulations include provisions for annual reporting, particularly concerning the deemed export of quantum technology and software, highlighting the global nature of innovation in these fields. The rule is designed to support U.S. technology leadership while ensuring that export controls do not impede international collaboration, particularly in areas like quantum computing, where global expertise is crucial. Comments on the rule and its potential impact on supply chains and compliance programs are invited, with a focus on refining the scope and clarity of the new ECCNs and license exceptions.

BIS specifies that the restrictions on GAAFET (Gate-All-Around Field-Effect Transistor) technology primarily focus on the "technology" required for the "development" or "production" of GAAFET structures. This includes process recipes and other detailed specifications necessary for fabricating these advanced semiconductor devices. These restrictions are captured under ECCN 3E905, which applies to the "technology" for GAAFETs but does not extend to vertical GAAFET architectures used in 3D NAND. The export, reexport, or transfer of this technology to certain countries requires a license due to its national security and regional stability implications. However, the rules include specific exceptions for existing collaborations and provisions for continued access under certain conditions.

The specific wafer processing technologies restricted for export include:

Dry Etching Equipment:

Equipment designed for isotropic dry etching, as well as anisotropic etching of dielectric materials. These include technologies that enable the fabrication of high aspect ratio features, with aspect ratios greater than 30:1 and a lateral dimension on the top surface of less than 100 nn.  

The specific restrictions on Atomic Layer Etching (ALE) equipment are detailed under the export control regulations. The BIS has imposed controls on equipment designed or modified for anisotropic dry etching, which includes certain types of ALE equipment. These tools, particularly those using RF pulse-excited plasma, pulsed duty cycle excited plasma, and other advanced techniques, are now restricted due to their critical role in the precise fabrication of high-performance semiconductor devices. The restrictions apply to ALE equipment that is capable of producing high aspect ratio features, which are essential for advanced semiconductor manufacturing, making these tools subject to national security and regional stability controls .

Deposition Technologies:

Equipment designed for the selective bottom-up chemical vapor deposition (CVD) of tungsten fill metal, and other deposition processes such as those for tungsten nitride, tungsten, and cobalt layers. This also includes atomic layer deposition (ALD) equipment designed for area selective deposition of barriers or liners.

The restrictions on Atomic Layer Deposition (ALD) equipment are focused on several key types of equipment essential for advanced semiconductor manufacturing. Specifically, ALD equipment designed for area-selective deposition of barriers or liners using organometallic compounds is controlled. This includes equipment capable of area-selective deposition (ASD) that enables fill metal contact to an underlying electrical conductor without a barrier layer at the fill metal via interface to the conductor. Additionally, ALD equipment designed for depositing tungsten (W) to fill interconnects or channels less than 40 nm wide is also restricted. These restrictions are imposed due to the critical role these technologies play in the precision required for the fabrication of next-generation semiconductor devices.

These technologies are controlled under ECCNs (Export Control Classification Numbers) such as 3B001 and related classifications, and are subject to national security (NS) and regional stability (RS) controls.

The specific materials, chemicals, or precursors that are being restricted under the new export controls include:

These restrictions reflect the importance of controlling advanced materials that play a crucial role in emerging technologies, particularly those with significant national security implications, i.e., quantum technologies.

Epitaxial Materials: This includes materials with at least one epitaxially grown layer of silicon or germanium containing a specified percentage of isotopically enriched silicon or germanium. These materials are controlled due to their critical role in developing spin-based quantum computers.

Fluorides, Hydrides, Chlorides: Specific chemicals of silicon or germanium that contain a certain isotopic composition are also restricted. These chemicals are essential in semiconductor manufacturing processes, particularly in the development of quantum technologies.

Silicon, Silicon Oxides, Germanium, or Germanium Oxides: These materials, when isotopically enriched, are restricted due to their applications in quantum computing and other advanced technologies. The control extends to various forms such as substrates, lumps, ingots, boules, and preforms . 

* The new export controls introduced by the Bureau of Industry and Security (BIS) are effective as of September 6, 2024. However, there are delayed compliance dates for certain items, allowing businesses until November 5, 2024, to comply with the new requirements, particularly for specific quantum technologies and related equipment. This delayed compliance is intended to give affected parties time to adjust to the new regulations.

Source:

2024-19633.pdf (SECURED) (govinfo.gov)

Impact of Deposition Mechanisms on Feature Sizes in Area-Selective Atomic Layer Deposition of TiO2 and HfO2

A study from Georgia Techinvestigates the mechanisms behind area-selective atomic layer deposition (AS-ALD) of titanium dioxide (TiO2) and hafnium dioxide (HfO2) on poly(methyl methacrylate) (PMMA) and silicon (Si) substrates, emphasizing their effects on feature sizes and film thickness. The researchers found that TiO2 exhibits highly selective deposition on Si compared to PMMA, though the PMMA sidewalls inhibit deposition, resulting in smaller feature dimensions than the original patterns. In contrast, HfO2, while less selective, combines selective deposition with a lift-off mechanism, allowing for smaller feature sizes but limiting the possible thickness before full coverage occurs.

The study highlights that TiO2's truly area-selective deposition mechanism causes significant sidewall inhibition, restricting the achievable feature size to larger dimensions. However, HfO2's combination of selective deposition and lift-off results in less sidewall inhibition, enabling the formation of much smaller features. The research further suggests that the choice of deposition material and the mechanism it employs critically influences the minimum feature sizes that can be achieved in semiconductor fabrication, with practical implications for future device miniaturization.

Summary of the mechanisms for AS-ALD of TiO2 and HfO2 using a PMMA area-selective mask, along with the corresponding benefits and limitations of each material. J. Phys. Chem. C 2024, XXXX, XXX, XXX-XXX

The findings underscore that the AS-ALD mechanism—whether a pure area-selective process or a combination with lift-off—directly affects the precision and scalability of nanofabrication. TiO2's area-selective mechanism is more effective for creating precise patterns but is limited by sidewall effects, while HfO2 offers greater flexibility in feature size at the cost of potential thickness limitations due to less selective deposition behavior. Potentially the research provides valuable insights for optimizing deposition techniques in advanced semiconductor manufacturing.

Source

Mechanisms of Area-Selective Atomic Layer Deposition and Their Impact on Feature Sizes | The Journal of Physical Chemistry C (acs.org)