3rd and Last Call for Papers, and List of Speakers / Symposium on ALD & ALE Applications #21, at 248th ECS Fall Meeting / Oct. 12-16, 2025 in Chicago, USA

This fall, the 248th ECS Meeting will be held on Oct. 12-16, 2025 in Chicago (IL, USA), and is expected to gather some 3,000 participants and 40 exhibitors from both academia and industry.

The conference has a strong focus on emerging technology and applications in both solid-state science & technology and electrochemistry.

• General information and the Meeting Program can be found here: Important Information and Call for Papers.
• For more information about our annual symposium G01 and the conference website: Meeting Information. 

The organizers of symposium G01 on “Atomic Layer Deposition & Etching Applications, 21” encourage you to submit your abstract(s) on topics, comprising but not limited to: 

1. Semiconductor CMOS applications: development and integration of ALD high-k oxides and metal electrodes with conventional and high-mobility channel materials; 

2. Volatile and non-volatile memory applications: extendibility, Flash, MIM, MIS, RF capacitors, etc.; 3. Interconnects and contacts: integration of ALD films with Cu and low-k materials; 

4. Fundamentals of ALD processing: reaction mechanisms, in-situ measurement, modeling, theory; 

5. New precursors, delivery systems & sustainability issues; 

6. Optical, photonic and quantum applications; applications aiming at Machine Learning, Artificial Intelligence 

7. Coating of nanoporous materials by ALD; 

8. Molecular Layer Deposition (MLD) and hybrid ALD/MLD; 

9. ALD for energy conversion applications such as fuel cells, photovoltaics, etc.; 

10. ALD for energy storage applications; 

11. Productivity enhancement, scale-up and commercialization of ALD equipment and processes for rigid and flexible substrates, including roll-to-roll and spatial processing; 

12. Area-selective ALD; 

13. Atomic Layer Etching (‘reverse ALD’) and related topics aiming at self-limited etching, such as atomic layer cleaning, etc. 

FYI: Last year at the PRiME 2024 Meeting in Honolulu, our symposium G01 on ALD & ALE Applications 20 attracted some 80 participants, attending a full 3-days schedule with 50 presentations (42 oral, of which 16 invited, plus 8 poster presentations). We expect to be at least as successful this Fall in Chicago. 

Abstract submission 

Meeting abstracts should be submitted not later than the deadline of March 28, 2025 via the ECS website: Submission Instructions

Submission Instructions Invited speakers A list of invited speakers follows below: 

Visa and travel For extensive information, see last year’s version: VISA AND TRAVEL INFORMATION

In addition, ECS’ Francesca Di Palo (francesca.dipalo@electrochem.org) can provide you with an official participation letter issued by the Electrochemical Society. For (limited) general travel grant questions, please contact travelgrant@electrochem.org. 

As in the past years, we expect also our symposium to be able provide some partial travel allowance to selected speakers. We are looking forward to meeting you all at our symposium G01 on ALD & ALE Applications 21, in Chicago | Oct. 12-16, 2025!

TU Eindhoven and LONGi Advance ALD ZnO Passivating Contacts, Achieving 24.3 Percent Efficiency in Silicon Solar Cells

Atomic layer deposition of ZnO for contact passivation in silicon solar cells has emerged as a promising alternative to TOPCon technology, with the recent breakthrough of zinc oxide passivating contacts achieving 24.3 percent efficiency in a LONGi solar cell. This development builds on research led by Bart Macco’s group at Eindhoven University of Technology, which pioneered the concept of ZnO passivating contacts. The breakthrough was further demonstrated by LONGi, which successfully integrated the technology into high-efficiency solar cells.

Key advancements include the use of an interfacial SiO2 layer for passivation, Al2O3 capping to retain hydrogen during annealing, and selective Al2O3 removal to enable electrical contact while preserving passivation. The integration of a low-work-function LiF layer has improved contact resistivity, reducing the need for heavy silicon doping.

ALD ZnO offers lower-temperature processing, thinner layers around five nanometers, and elimination of toxic dopants compared to doped poly-Si in TOPCon. With potential advantages in scalability, industrial feasibility, and initial efficiency gains, ZOPCon could surpass TOPCon, though further research is needed to enable bifacial designs, optimize lateral conductivity, and enhance stability for large-scale production.

Sources

Passivating Contacts for Silicon Solar Cells: A Zinc Oxide Breakthrough? – Atomic Limits

Intel Unveils 6 nm Gate Length Silicon RibbonFET CMOS and Breakthroughs in Semiconductor Scaling at IEDM 2024

Intel Corporation / Intel Foundry has demonstrated and extensively characterized gate-all-around Silicon RibbonFET CMOS transistors with a 6 nm gate length (LG). The study showcases nanoribbon silicon thickness (Tsi) scaling down to 3 nm, enhancing short-channel effects without compromising performance. Effective workfunction engineering mitigates threshold voltage increases caused by quantum confinement at scaled Tsi, enabling reduced threshold voltage at highly scaled gate lengths. Injection velocity of 1.13x10^7 cm/s is maintained at LG=6nm without degradation down to Tsi=3 nm, highlighting advancements crucial for continued gate length scaling and the ongoing realization of Moore's Law.

Intel Foundry made groundbreaking announcements at the IEEE International Electron Devices Meeting (IEDM) 2024, showcasing advancements that propel semiconductor technology into the next decade and beyond. Highlights include innovations in transistor and interconnect scaling, advanced packaging, and emerging materials to support the industry’s roadmap toward achieving 1 trillion transistors on a chip by 2030. Intel demonstrated a 25% capacitance reduction using subtractive ruthenium for interconnections, achieved a 100x throughput improvement in advanced packaging through Selective Layer Transfer (SLT), and advanced gate-all-around (GAA) transistor scaling with Silicon RibbonFET CMOS at a 6 nm gate length. Additionally, Intel unveiled new work on gate oxide modules for scaled 2D FETs, addressing the next phase of GAA scaling.

Among the key technical breakthroughs, subtractive ruthenium stands out as a metallization alternative to copper for interconnects, offering significant capacitance reductions at tight pitches while being cost-effective and scalable for high-volume manufacturing. SLT further revolutionizes advanced packaging with ultra-fast, flexible chip-to-chip assembly, enabling smaller, higher-density chiplets for AI and other demanding applications. For transistor scaling, Intel’s demonstration of Silicon RibbonFET CMOS at 6 nm gate length delivers industry-leading short-channel effects and performance, paving the way for continued scaling under Moore’s Law. Additionally, Intel’s progress with 2D GAA NMOS and PMOS transistors and gate oxide development signals readiness for post-silicon semiconductor technologies.

Intel also highlighted progress in gallium nitride (GaN) technology, demonstrating the first 300 mm GaN-on-TRSOI substrates for high-performance power and RF electronics. These developments, alongside Intel’s continued focus on advanced memory integration, hybrid bonding, and modular system expansion, underscore its commitment to addressing challenges in AI, energy efficiency, and thermal management. With these innovations, Intel Foundry continues to lead the charge in semiconductor advancements, ensuring a robust path forward for the trillion-transistor era.

Source: Intel IEDM 2024 Innovations

Lam Research Sees Growth Opportunities in Etch and Deposition Technologies Despite NAND Downturn

In its Q1 2025 earnings call, Lam Research reported strong performance and emphasized growth opportunities, particularly in etch and deposition technology. CEO Tim Archer highlighted optimism for NAND spending recovery in 2025, supported by technology upgrades and a transition to molybdenum through Lam’s advanced Atomic Layer Deposition (ALD). Lam is positioned to capture opportunities in advanced semiconductor nodes like gate-all-around and EUV patterning, while its expanded offerings in high-bandwidth memory (HBM) and advanced packaging align with growing demand in AI and high-performance computing. Despite regulatory challenges in China, Lam continues to serve this market by focusing on upgrades and services. Looking ahead, Lam expects to outpace industry growth, driven by its strategic positioning across advanced technologies.

In its Q1 2025 earnings call, Lam Research Corporation (NASDAQ: LRCX) reported solid performance and reiterated optimism for growth in 2025, largely driven by demand for etch and deposition technologies. CEO Tim Archer emphasized Lam’s strategic positioning in an industry experiencing technological shifts, despite a prolonged downturn in NAND spending.

Lam anticipates a recovery in NAND spending in 2025, largely driven by technology upgrades rather than new capacity expansions. Key factors include a transition from tungsten to molybdenum in NAND structures, which improves performance by reducing resistivity. Lam is well-positioned in this area due to its extensive installed base and production wins, projecting an advantageous position as these upgrades scale into 2025.

NAND Technology Upgrades Set to Drive Etch and Deposition Demand in 2025

While the NAND segment has been in a prolonged downturn, Lam anticipates a recovery in 2025 as manufacturers upgrade to advanced nodes. The push toward 3D NAND layers exceeding 200 is essential to meet the growing demand for high-speed, high-capacity storage in data centers and client devices. Currently, about two-thirds of NAND capacity remains at older technology nodes, highlighting significant room for technology upgrades. Lam’s extensive installed base of NAND equipment positions it well to benefit as customers look to improve efficiency and performance.

Furthermore, Archer highlighted a shift from tungsten to molybdenum as a key materials change in NAND, addressing word line resistance challenges. This transition is particularly favorable for Lam, as it has already secured production wins in molybdenum deposition, which will scale up throughout 2025. These advancements are expected to enhance Lam's leadership position in NAND technology transitions.

Lam's product offerings mentioned in the reporting, along with their primary applications and strategic impacts.

Advanced Logic and Foundry Nodes: Key Growth Segments for Lam

Lam is also poised to benefit from shifts in advanced logic and foundry nodes, which are increasingly adopting gate-all-around architectures, backside power distribution, and advanced EUV patterning. These cutting-edge technologies require more intensive use of etch and deposition processes, aligning with Lam’s expertise and product offerings.

Archer noted the company's recent wins in selective etch tools and other innovations that support these advanced nodes, positioning Lam favorably as customers transition to architectures with greater power and performance needs. This expanding demand from foundry and logic customers offers a substantial growth opportunity for Lam’s advanced etch and deposition technologies.

Advanced Packaging Driven by AI Fuels Revenue Growth

The AI and high-performance computing boom has intensified demand for advanced packaging, particularly for high-bandwidth memory (HBM). Lam’s copper plating technology, SABRE 3D, has experienced substantial adoption, doubling its market share this year. This growth has been fueled by the rising complexity of 2.5D and 3D packages, which require high-performance interconnections to support AI-driven systems.

Lam anticipates this trend will continue into 2025 as the industry moves toward more advanced and intricate packaging solutions. According to Archer, advanced packaging will play a critical role in the semiconductor ecosystem for the foreseeable future, and Lam’s early investment in this technology has positioned it for continued market share gains.

Supporting Installed Base and Productivity in Memory Markets

Lam’s Customer Support Business Group (CSBG) has also shown growth, focusing on productivity enhancements and tool reuse. With Lam’s extensive tool installations in both DRAM and NAND, customers are prioritizing upgrades over entirely new systems, especially as they look to improve cost efficiency during NAND’s down cycle. This focus on tool reuse has led to recent market share gains for Lam, as existing tools are upgraded for better value than new installations.

As DRAM and NAND customers intensify efforts to reduce costs, Lam’s service-oriented model and productivity solutions, including equipment intelligence services, have seen greater adoption. This trend underscores Lam's ability to support its customers' evolving needs in an era of increased etch and deposition intensity.

Lam Research Leverages ALD for Moly Transition in NAND, Driving Next-Gen Semiconductor Performance

Lam Research's perspective on ALD is optimistic, particularly as it becomes increasingly essential in NAND technology upgrades. The company highlighted the industry's ongoing shift from tungsten to molybdenum (moly) for improved resistivity in 3D NAND structures, a transition that Lam’s ALD technology is well-positioned to support. Lam has already secured production wins for ALD applications with molybdenum, expected to ramp up significantly in 2025. This capability extends beyond NAND, with potential applications in DRAM and advanced logic/foundry nodes, underscoring ALD’s growing importance in meeting next-generation semiconductor demands.

Lam Research Adapts to Regulatory Challenges as China Revenue Set to Decline in 2025

In its Q1 2025 earnings presentation, Lam Research highlighted key developments and expectations for the China market. China accounted for roughly 37% of Lam's revenue in the September quarter, but the company anticipates this share will decrease to around 30% by December and potentially decline further in 2025. This projected downturn reflects both anticipated shifts in demand and the impact of U.S. export restrictions on advanced semiconductor equipment sales to China. Lam acknowledged the challenges posed by ongoing and potential new U.S. export controls, which could limit its ability to sell to certain advanced technology segments in China. Nevertheless, Lam remains committed to supporting its domestic Chinese customers within the boundaries of regulatory compliance, expecting demand in restricted segments to normalize as global WFE (wafer fabrication equipment) spending adjusts.

Much of Lam's business in China now focuses on servicing domestic fabs with tools for trailing-edge and specialty node processes, areas that generally remain unaffected by export controls. Through its Reliant product line, Lam continues to support these nodes, emphasizing upgrades and maintenance services as primary offerings in a market constrained by new advanced technology sales. Despite potential reductions in advanced equipment sales, the company is confident that its service and support model will help stabilize revenue in the region. By prioritizing productivity solutions and customer support, Lam is adapting to a complex regulatory environment while anticipating that China’s share of its revenue will gradually normalize amid a broader decline in WFE spending in the country.

Strategic Positioning in 2025 and Beyond

In summary, Lam Research is set to capitalize on a growing demand for etch and deposition technology driven by the industry’s shift to advanced architectures. Archer concluded the call with optimism, stating that the company is well-positioned to capture market share as the semiconductor industry increasingly relies on complex, three-dimensional structures. With its advanced product offerings, Lam expects to outperform overall wafer fabrication equipment (WFE) growth in 2025, strengthening its leadership across multiple semiconductor sectors.

New Export Controls on ALD, ALE and ASD Technologies Effective September 2024 to Safeguard National Security

The US Bureau of Industry and Security (BIS) is introducing* stringent export controls targeting advanced technologies essential to national security, particularly within the semiconductor, quantum computing, and additive manufacturing sectors. These controls include new and revised Export Control Classification Numbers (ECCNs) and specific restrictions on critical equipment and materials, such as those involved in Gate-All-Around Field-Effect Transistor (GAAFET) technology, Atomic Layer Etching (ALE), and Atomic Layer Deposition (ALD). The controls aim to safeguard U.S. technological leadership while harmonizing with international export control standards. Specific restrictions apply to high-precision wafer processing equipment and isotopically enriched materials used in quantum computing, reflecting the critical importance of these technologies. These measures ensure that while international collaboration continues, sensitive technologies remain protected under national security protocols.

BIS has introduced new export controls focused on advanced technologies, particularly in the semiconductor, quantum computing, and additive manufacturing sectors. These controls include new Export Control Classification Numbers (ECCNs), revisions to existing ones, and the addition of new license exceptions for countries with similar technical controls. This rule aims to protect national security and advance foreign policy objectives by aligning U.S. export controls with those of international partners. The controls cover a wide range of items, including quantum computing technologies and semiconductor manufacturing equipment, reflecting the critical importance of these technologies to national security. The rule is effective immediately, though there are delayed compliance dates for certain items, allowing businesses time to adjust to the new requirements.

BIS has also established a framework to differentiate between items controlled multilaterally and those controlled through Implemented Export Controls (IEC), which are harmonized with international partners. The new regulations include provisions for annual reporting, particularly concerning the deemed export of quantum technology and software, highlighting the global nature of innovation in these fields. The rule is designed to support U.S. technology leadership while ensuring that export controls do not impede international collaboration, particularly in areas like quantum computing, where global expertise is crucial. Comments on the rule and its potential impact on supply chains and compliance programs are invited, with a focus on refining the scope and clarity of the new ECCNs and license exceptions.

BIS specifies that the restrictions on GAAFET (Gate-All-Around Field-Effect Transistor) technology primarily focus on the "technology" required for the "development" or "production" of GAAFET structures. This includes process recipes and other detailed specifications necessary for fabricating these advanced semiconductor devices. These restrictions are captured under ECCN 3E905, which applies to the "technology" for GAAFETs but does not extend to vertical GAAFET architectures used in 3D NAND. The export, reexport, or transfer of this technology to certain countries requires a license due to its national security and regional stability implications. However, the rules include specific exceptions for existing collaborations and provisions for continued access under certain conditions.

The specific wafer processing technologies restricted for export include:

Dry Etching Equipment:

Equipment designed for isotropic dry etching, as well as anisotropic etching of dielectric materials. These include technologies that enable the fabrication of high aspect ratio features, with aspect ratios greater than 30:1 and a lateral dimension on the top surface of less than 100 nn.  

The specific restrictions on Atomic Layer Etching (ALE) equipment are detailed under the export control regulations. The BIS has imposed controls on equipment designed or modified for anisotropic dry etching, which includes certain types of ALE equipment. These tools, particularly those using RF pulse-excited plasma, pulsed duty cycle excited plasma, and other advanced techniques, are now restricted due to their critical role in the precise fabrication of high-performance semiconductor devices. The restrictions apply to ALE equipment that is capable of producing high aspect ratio features, which are essential for advanced semiconductor manufacturing, making these tools subject to national security and regional stability controls .

Deposition Technologies:

Equipment designed for the selective bottom-up chemical vapor deposition (CVD) of tungsten fill metal, and other deposition processes such as those for tungsten nitride, tungsten, and cobalt layers. This also includes atomic layer deposition (ALD) equipment designed for area selective deposition of barriers or liners.

The restrictions on Atomic Layer Deposition (ALD) equipment are focused on several key types of equipment essential for advanced semiconductor manufacturing. Specifically, ALD equipment designed for area-selective deposition of barriers or liners using organometallic compounds is controlled. This includes equipment capable of area-selective deposition (ASD) that enables fill metal contact to an underlying electrical conductor without a barrier layer at the fill metal via interface to the conductor. Additionally, ALD equipment designed for depositing tungsten (W) to fill interconnects or channels less than 40 nm wide is also restricted. These restrictions are imposed due to the critical role these technologies play in the precision required for the fabrication of next-generation semiconductor devices.

These technologies are controlled under ECCNs (Export Control Classification Numbers) such as 3B001 and related classifications, and are subject to national security (NS) and regional stability (RS) controls.

The specific materials, chemicals, or precursors that are being restricted under the new export controls include:

These restrictions reflect the importance of controlling advanced materials that play a crucial role in emerging technologies, particularly those with significant national security implications, i.e., quantum technologies.

Epitaxial Materials: This includes materials with at least one epitaxially grown layer of silicon or germanium containing a specified percentage of isotopically enriched silicon or germanium. These materials are controlled due to their critical role in developing spin-based quantum computers.

Fluorides, Hydrides, Chlorides: Specific chemicals of silicon or germanium that contain a certain isotopic composition are also restricted. These chemicals are essential in semiconductor manufacturing processes, particularly in the development of quantum technologies.

Silicon, Silicon Oxides, Germanium, or Germanium Oxides: These materials, when isotopically enriched, are restricted due to their applications in quantum computing and other advanced technologies. The control extends to various forms such as substrates, lumps, ingots, boules, and preforms . 

* The new export controls introduced by the Bureau of Industry and Security (BIS) are effective as of September 6, 2024. However, there are delayed compliance dates for certain items, allowing businesses until November 5, 2024, to comply with the new requirements, particularly for specific quantum technologies and related equipment. This delayed compliance is intended to give affected parties time to adjust to the new regulations.

Source:

2024-19633.pdf (SECURED) (govinfo.gov)

Impact of Deposition Mechanisms on Feature Sizes in Area-Selective Atomic Layer Deposition of TiO2 and HfO2

A study from Georgia Techinvestigates the mechanisms behind area-selective atomic layer deposition (AS-ALD) of titanium dioxide (TiO2) and hafnium dioxide (HfO2) on poly(methyl methacrylate) (PMMA) and silicon (Si) substrates, emphasizing their effects on feature sizes and film thickness. The researchers found that TiO2 exhibits highly selective deposition on Si compared to PMMA, though the PMMA sidewalls inhibit deposition, resulting in smaller feature dimensions than the original patterns. In contrast, HfO2, while less selective, combines selective deposition with a lift-off mechanism, allowing for smaller feature sizes but limiting the possible thickness before full coverage occurs.

The study highlights that TiO2's truly area-selective deposition mechanism causes significant sidewall inhibition, restricting the achievable feature size to larger dimensions. However, HfO2's combination of selective deposition and lift-off results in less sidewall inhibition, enabling the formation of much smaller features. The research further suggests that the choice of deposition material and the mechanism it employs critically influences the minimum feature sizes that can be achieved in semiconductor fabrication, with practical implications for future device miniaturization.

Summary of the mechanisms for AS-ALD of TiO2 and HfO2 using a PMMA area-selective mask, along with the corresponding benefits and limitations of each material. J. Phys. Chem. C 2024, XXXX, XXX, XXX-XXX

The findings underscore that the AS-ALD mechanism—whether a pure area-selective process or a combination with lift-off—directly affects the precision and scalability of nanofabrication. TiO2's area-selective mechanism is more effective for creating precise patterns but is limited by sidewall effects, while HfO2 offers greater flexibility in feature size at the cost of potential thickness limitations due to less selective deposition behavior. Potentially the research provides valuable insights for optimizing deposition techniques in advanced semiconductor manufacturing.

Source

Mechanisms of Area-Selective Atomic Layer Deposition and Their Impact on Feature Sizes | The Journal of Physical Chemistry C (acs.org)

Chipmetrics Launches New Test Chips for Advanced Atomic Layer Processes

Finnish 3D thin film semiconductor metrology specialist launches new PillarHall LHAR5 test chip with 100 nanometer gap height, complements its metrology solution with new ASD-1 chip for Area Selective Deposition.

Joensuu, Finland – July 15th, 2024 – Chipmetrics Oy, an innovative metrology solutions provider to the semiconductor industry, announces the launch of two new test chips, the PillarHall LHAR5 and the ASD-1. The PillarHall LHAR5 silicon test chip builds on the success of its predecessor PillarHall LHAR4, with the new LHAR5 test chips being better suited for the most advanced 3D semiconductor device high aspect ratio structures with a gap height as low as 100 nm. Fitting seamlessly into Chipmetrics’ pocket wafer concept, it also allows for fast and accurate process control with full 300-millimeter compatibility.

The PillarHall LHAR5 test chip comes in two variations, with a 100-nanometer and a 500-nanometer gap height. The new 100-nanometer gap height allows engineers to research and compare possible dimensional effects in film penetration depth in line with 500-nanometer gap chips. This allows for new insights into film conformality control and a deeper understanding of 3D NAND, DRAM and other nanoelectronics containing high aspect ratio structures.

“With the launch of PillarHall LHAR5, ASD-1 and the 300-millimeter pocket wafer concept our product line is compatible with the most advanced and challenging semiconductor deposition and etch technologies like ALD, ALE and ASD. The Chipmetrics test chips with our pocket wafer concept is directly compatible with and ready to be used in all existing deposition tools,” says Mikko Utriainen, CEO of Chipmetrics.

The Chipmetrics ASD-1: Prototyping and Process Control for Area Selective Deposition workflows

Launched concurrently with the PillarHall LHAR5 is the Chipmetrics ASD-1 test chip, for prototyping and process control of Area Selective Deposition (ASD) workflows. As the name implies, ASD allows for selective growth of thin films on specific substrate areas, while avoiding it on others, with the ASD-1 test chip aiming to give customers easy access to high-quality data for process control and R&D.

The ASD-1 test chip features a high surface planarity, low line edge roughness, and small line widths which are crucial for ASD applications in advanced semiconductor manufacturing. The ASD-1 test chip features arrays of sub-100 nanometer narrow line structures with alternating materials aligned on the planar silicon substrate for accurately characterizing self-aligned area selective depositions through either Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD) and related processes. The Chipmetrics ASD-1 helps engineers to accelerate ASD process development to meet challenges in miniaturizing and scaling, as well as in reducing defects and improving yield.

Both the PillarHall LHAR5 and ASD-1 test chips are available immediately. For more information on the products, please visit Chipmetrics.com.

About Chipmetrics

Chipmetrics Oy develops and delivers metrology solutions for manufacturing processes for the semiconductor industry, focusing on innovative metrology chips and ALD measurement services. Its main product is the PillarHall® metrology chip for near-instantaneous thin film process conformality measurement. Founded in 2019, its head office is in Joensuu, Finland, with employees and sales partners in Japan, South Korea, USA, and Germany.

For more information, visit www.chipmetrics.com.

Press contact:

Jonas Klar

Chipmetrics Oy

jonas.klar@chipmetrics.com

pr@chipmetrics.com

Editor’s note on ALD:

Atomic Layer Deposition (ALD) is a precision thin-film deposition technique crucial for semiconductor manufacturing, enabling the production of uniform and conformal layers essential for microelectronic devices. Through alternating exposure to precursor gases that react with the substrate in a self-limiting manner, ALD achieves atomic-level control over film thickness and composition. This method ensures exceptional uniformity across complex geometries, vital for the miniaturized, multi-layered structures such as the future’s 3D chips in advanced semiconductor devices, keeping Moore’s Law alive.

Finland plays a key role in the ALD landscape, having pioneered the process in the 1970s. Finland’s contribution to ALD includes significant advancements in materials science, equipment design, and the exploration of new applications ranging from electronics to renewable energy sectors. The country’s strong emphasis on research and development in nanotechnology has positioned it as a hub for ALD innovation, fostering collaborations between academia, industry, and research organizations worldwide.

Boosting the Future: Increased ALD Use Paves the Way for Advanced GAAFET Technology

The Biden administration is considering a complete ban on the export of chips utilizing Gate All-Around Field Effect Transistor (GAAFET) technology to China, Bloomberg reports (LINK). The rationale behind this potential ban is the concern that such advanced transistors could be leveraged for military applications and artificial intelligence (AI) advancements by China. This move follows previous restrictions from 2022, when the U.S. barred its Electronic Design and Automation (EDA) companies from selling tools necessary for GAAFET development to China. In addition, advanced chip exports from companies like Nvidia were restricted, with these measures being progressively tightened and expanded over time.

Atomic Layer Deposition (ALD) is celebrating its 50th anniversary in 2024. The anniversary marks 50 years since Dr. Tuomo Suntola and his colleagues filed the first patent for Atomic Layer Epitaxy in 1974, which laid the foundation for ALD technology. This milestone will be celebrated at various events, including the ALD 2024 conference, where Dr. Suntola is expected to deliver the opening remarks .

ASM International, a leader in Atomic Layer Deposition (ALD), plays a crucial role in enabling Gate-All-Around Field Effect Transistors (GAAFETs) and continued semiconductor scaling. ALD's precision in depositing ultra-thin, uniform films is essential for creating the high-performance, low-power structures required by GAAFETs. This technology, along with other advanced processes such as epitaxy and selective etching, supports the intricate fabrication steps needed for these next-generation transistors.

The production of GAAFETs requires a significant increase in the use of ALD technology - maybe up to 40% more according to ASM. ALD is essential for creating the ultra-thin, uniform films needed for GAAFET structures, ensuring high-quality, defect-free layers that are critical for advanced transistor performance. This technology enables precise control over the deposition process, crucial for developing high-k dielectrics and other materials that enhance GAAFET performance and efficiency. As the semiconductor industry now transitions from FinFET to GAAFET technology, leveraging ALD's capabilities is vital for maintaining and advancing Moore's Law, enabling more powerful and energy-efficient chips using existing manufacturing infrastructure

Applied Materials has outlined next-generation tools essential for producing 3nm and GAA transistors, such as those in Samsung's upcoming 3GAE and 3GAP technologies. These advanced tools address the complexities of GAA transistor manufacturing, including precise lithography, epitaxy, and selective materials removal. Applied's Producer Selectra Selective Etch IMS tool is pivotal in defining channel width without damaging surrounding materials, while the Centura Prime Epi tool ensures clean deposition of Si and SiGe nanosheets. Additionally, their Integrated Materials Solution (IMS) systems integrate atomic layer deposition (ALD), thermal steps, and plasma treatments to optimize the gate oxide stack, enhancing performance and reducing gate leakage. These innovations are crucial as they enable higher performance, lower power consumption, and greater transistor density, aligning with the industry's move from FinFET to GAA technology.

Today GAA transistors are currently in mass production only by Samsung, which offered the technology to customers with its 3-nanometer process in 2022. Intel is set to follow, producing GAAFET on its 2-nanometer process expected to be available in its products later this year. TSMC, the market leader, plans to introduce GAAFET with its own 2 nm process in 2025. The GAAFET technology itself is not inherently suited for AI or military applications but represents an evolution in transistor design, enabling denser packing of transistors as lithography equipment and manufacturing processes advance. This technology shift, akin to transitioning to a new node, typically results in either reduced power consumption or improved performance by 15-25%.

The improvements facilitated by GAAFET could significantly enhance the capabilities available to China. SMIC, China's largest contract manufacturer, currently produces chips on a 7 nm process and is believed to be capable of reaching at least 5 nanometers with existing tools. The combination of this process with GAAFET could theoretically prevent China from falling too far behind Western advancements. However, China has been effectively shut out from developing GAAFET using tools from leading EDA companies, all of which are American. Additionally, the Dutch company ASML, dominant in the lithography equipment market, has not sold its EUV (Extreme Ultraviolet) machines to China and faced further restrictions in 2023 on selling its advanced DUV (Deep Ultraviolet) equipment. In April 2024, ASML took another step in the tech war against China by announcing that it would no longer service existing equipment in China, potentially crippling the country's semiconductor manufacturing capabilities. The specific details of the new export bans are still unclear, but Reuters notes that initial proposals have faced criticism from the U.S. semiconductor industry for being overly broad and extensive.

Source: USA överväger ytterligare GAAFET-sanktioner mot Kina – Semi14, www.ASM.com, Applied Materials Outlines Next-Gen Tools for 3nm and GAA Transistor Era (anandtech.com), Atomic layer deposition, next-gen transistors, and ASM (techfund.one)

Jusung Engineering to Spin Off Semiconductor Business, Aiming for Market Revaluation and Strategic Growth

Jusung Engineering, a a first in Korea’s chipmaking equipment industry, has announced a significant restructuring aimed at enhancing its market valuation and navigating geopolitical risks. The company will spin off its highly successful semiconductor division into a new entity, marking a strategic move to unlock greater value for its shareholders and position itself for future growth.

Chairman Hwang Chul-ju highlighted the undervaluation of Jusung despite its proprietary technologies and leading market position. By creating a new entity for its semiconductor business, Jusung aims to elevate its market cap, which currently lags behind international competitors. The new semiconductor entity, tentatively named Jusung Engineering, will operate independently, allowing it to focus solely on expanding its technological capabilities and market presence.

The spin-off comes as Jusung's semiconductor division continues to excel with its advanced film deposition technologies, including selective semi-spheric silicon deposition and atomic layer deposition (ALD). These technologies are pivotal in the production of DRAM memory, NAND flash, and logic chips. As the demand for more integrated and smaller semiconductor devices grows, Jusung's ALD equipment is set to become increasingly crucial. Additionally, Jusung’s poly etchers, applicable across various semiconductor products, will play a significant role in diversifying the company’s offerings.

Despite achieving annual sales of 200 billion won ($146 million) and holding a market cap of 1.6 trillion won, Jusung's valuation remains significantly lower than its global peers. For instance, Dutch competitor ASM boasts a market cap of 47.3 trillion won. The spin-off is expected to narrow this gap, potentially achieving comparable sales records within five years. 

The decision also aims to mitigate risks from the ongoing US-China rivalry. By separating the semiconductor business, Jusung can better shield its other divisions, including display and solar panel equipment, from potential geopolitical fallout. This strategic insulation ensures that the company’s diverse operations remain resilient in the face of international tensions.

There is speculation about Hwang Eun-seok, the chairman’s son, taking the helm of the new semiconductor entity. With a doctorate in material science and experience at Samsung Semiconductors, Eun-seok is well-prepared for leadership, though Chairman Hwang emphasizes that any succession will be merit-based.

Jusung Engineering's spin-off of its semiconductor business represents a bold move to enhance its market valuation and strategically position itself for sustained growth. By creating a focused, independent entity, Jusung aims to capitalize on its technological strengths and navigate the complexities of the global semiconductor market more effectively. This restructuring is set to unlock new opportunities and reinforce Jusung's standing as a key player in the tech industry.

Sources: Jusung, Undervalued no more: Jusung Engineering to spin off chip business (naver.com)

Surfs are going to be up at the PRiME Symposium G01 on ALD & ALE Applications 20, in Honolulu | Oct. 6-12, 2024

Every four years, the PRiME Joint International Meeting is held under the auspices of the Electrochemical Society (ECS), joint with its sister Societies of Japan and Korea. This fall, PRIME 2024 will be held on Oct. 6-11, 2024 in Honolulu, Hawaii, and is expected to gather over 4000 participants and 40 exhibitors from both academia and industry.

The conference has a strong focus on emerging technology and applications in both solid-state science & technology and electrochemistry.

General information and the Meeting Program can be found here: CALL FOR PAPERS.

The organizers of symposium G01 on “Atomic Layer Deposition & Etching Applications, 20” encourage you to submit your abstract(s) on topics, comprising but not limited to:

1. Semiconductor CMOS applications: development and integration of ALD high-k oxides and metal electrodes with conventional and high-mobility channel materials;

2. Volatile and non-volatile memory applications: extendibility, Flash, MIM, MIS, RF capacitors, etc.;

3. Interconnects and contacts: integration of ALD films with Cu and low-k materials;

4. Fundamentals of ALD processing: reaction mechanisms, in-situ measurement, modeling, theory;

5. New precursors and delivery systems;

6. Optical, photonic and quantum applications; applications aiming at Machine Learning, Artificial Intelligence

7. Coating of nanoporous materials by ALD;

8. Molecular Layer Deposition (MLD) and hybrid ALD/MLD;

9. ALD for energy conversion applications such as fuel cells, photovoltaics, etc.;

10. ALD for energy storage applications;

11. Productivity enhancement, scale-up and commercialization of ALD equipment and processes for rigid and flexible substrates, including roll-to-roll deposition;

12. Area-selective ALD;

13. Atomic Layer Etching (‘reverse ALD’) and related topics aiming at self-limited etching, such as atomic layer cleaning, etc.

FYI: Last year in Gothenburg, our symposium G01 on ALD & ALE Applications 19 attracted a record number of 78 presentations, composing a full 4-day schedule of 66 oral (of which 18 invited), plus 12 poster presentations.

We will traditionally attract more attendants from Far East and expect to be as successful this fall in Hawaii.

Abstract submission

Meeting abstracts should be submitted not later than the deadline of April 12, 2024 via the ECS website: Submission Instructions

Invited speakers

List of confirmed invited speakers (from North America, Asia and Europe):

1. Bart Macco, TU Eindhoven, Netherlands, Review of ALD for solar cells

2. Maarit Karppinen, Aalto University, Finland, ALD/MLD for energy / membrane technology

3. Chad Brick, Gelest, USA, Silanes and silazanes precursors for Area Specific Deposition

4. Makoto Sekine, Nagoya Univ., Japan, Low damage ALE of AlGaN

5. Rong Chen, HUST Univ. Wuhan, China, ALD for Cataysis and other applications

6. Mikhael Bechelany, IEM, Montpellier, France, Recent Advancements and Emerging Applications in ALD on High-Porosity Materials

7. Miika Mattinen, Univ Helsinki, Finland, ALD of dichalcogenides for electrocatalysis

8. Bonggeun Shong, Hongik University, Korea, Theory of area-selective ALD

9. Miin-Jang Chen, National Taiwan Univ., Inhibitor-free Area-Selective ALD

10. Hyungjun Kim, Yonsei University, Korea, ALD of “Group 16 Compounds” for Emerging Applications (2D TMDCs)

11. Agnieszka Kurek, Oxford Instruments, United Kingdom, Faster ALD for Emerging Quantum Applications

12. Matthew Metz, Inte, USA, Keynote on "Materials Challenges in Future Semiconductor Devices"

13. Junling Lu, University of Science and Technology of China, ALD for Catalysis

14. Sung Gap Im, KAIST, Korea, Vapor-phase Deposited Functional Polymer Films for Electronic Device Applications

15. Jason Croy, Argonne National Lab, USA, Next-gen batteries & ALD

16. Mark Saly, Applied Materials, USA, Key Challenges in Area Selective Deposition: from R&D Scale to High Volume Manufacturing

Visa and travel

For more information, see: VISA AND TRAVEL INFORMATION

In addition, Mrs. Francesca Spagnuolo at the ECS (Francesca.Spagnuolo@electrochem.org) can provide you with an official participation letter issued by the Electrochemical Society.

For (limited) general travel grant questions, please contact travelgrant@electrochem.org.

We are looking forward to meeting you all at our symposium G01 on ALD & ALE Applications 20, in Honolulu | Oct. 6-12, 2024 !

ASM International: Spearheading Semiconductor Innovation in ALD, Epitaxy, and CVD Markets

ASM International N.V. (Euronext Amsterdam: ASM) yesterday reported its fourth quarter 2023 operating results (unaudited). Double-digit full-year revenue growth, outperforming softer WFE market in 2023

Investor presentation: 2023_q4_investor-presentation.pdf (asm.com)

“2023 was another successful year for ASM. Sales increased by 13% at constant currencies, despite softening market conditions, and marking the seventh consecutive year of double-digit growth.” said Benjamin Loh, CEO of ASM. “Revenue in Q4 2023 amounted to €633 million, in line with our guidance of €600-640 million and down compared to the level in Q4 2022. Revenue in the quarter was supported by strong sales in the power/analog/ wafer segment. Bookings at €678 million were slightly better than our expectation and were driven by GAA pilot- line orders and continued strength in China demand.

ASM's Leadership in the Growing ALD Market

According to ASM, the single wafer Atomic Layer Deposition (ALD) market is experiencing significant growth, with projections indicating an increase from $2.6 billion in 2022 to a range of $4.2 billion to $5.0 billion by 2027. This growth, characterized by a Compound Annual Growth Rate (CAGR) of 10-14% from 2022 to 2027, underscores the expanding role of ALD technology in semiconductor manufacturing. ASM International, a key player in the semiconductor industry, holds a dominant position in this market, commanding a share of over 55% throughout the forecast period.

Please note that this market assessment, most probably originally from TechInsights (prev. VLSI Research) does not include Large Batch furnace ALD, which historically have been about 30% of the total 300 mm ALD equipment market. The leaders in this segment are Tokyo Electron followed by Kokusai and ASM chose not to compete with its A412 ALD product line.

Driving Forces Behind ALD Market Expansion

The expansion of the ALD market is propelled by a series of technological advancements and increasing demands within the semiconductor sector. Key factors contributing to this growth include the industry's shift towards Gate-All-Around (GAA) technology, the necessity for advanced high-k gate dielectrics, and the precision required for threshold voltage tuning. Additionally, the development of sacrificial layers and the use of high aspect ratio Through-Silicon Vias (TSVs) are critical in advancing semiconductor manufacturing techniques. The application of metals and the adoption of selective ALD processes further accentuate the importance of ALD technology in modern semiconductor fabrication.

ASM's Strategic Positioning and Market Opportunities

ASM is well-positioned to capitalize on the opportunities presented by the burgeoning ALD market. The company's strategic emphasis on innovation, coupled with its comprehensive product portfolio, positions ASM as a frontrunner in meeting the evolving needs of the logic/foundry and memory segments of the semiconductor industry. The transition to advanced manufacturing technologies, such as GAA and high-k metal gate applications, presents significant growth avenues for ALD, with ASM at the forefront of this technological evolution.

To be more specific, the transition to GAA technology and the expansion in FinFET applications are set to significantly increase ASM's served available market by approximately US$400 million for every 100,000 wafer starts per month (WSPM). According to ASM, the equipment orders started to come in in the 2nd half of 2023. We can assume that this are orders from Samsung, TSMC and Intel. It is however about peculiar since Samsung had 3 nm GAA going already with yield in August 2023 and ASM is describing it as GAA pilot lines. Anyhow, come 2028 when all leading foundries including Rapidus in Japan are up and running GAAFETs, this additional market will be + USD 1.5 B as compared to if it would have been "only" FinFET technology - according to my back of the envelope calculations. For a company like ASM, with just below USD 3 B (2.6 B EUR) annual Revenue 2023 this is a huge thing. If this is not enough to go woah - add to that the GAAFET market is an upwards moving target and will continue to grow and looking ahead stacking of NMOS/PMOS will drive further demand for this type of ALD and Epi processes.

Expansion into the Epitaxy and CVD Markets

The Silicon Epitaxy (Si epi) market is also on a growth trajectory, with forecasts suggesting it will reach between $2.3 billion and $2.9 billion by 2027. ASM aims for a market share target of over 30%, focusing on both leading-edge and non-leading-edge segments. The leading-edge growth is driven by transitions to GAA technology and advancements in high-performance DRAM, while the non-leading-edge growth is buoyed by wafer power analog and strong momentum from ASM's Intrepid ESA. The epitaxy market is expected to see a Compound Annual Growth Rate (CAGR) of 3-8% from 2022 to 2027, with the leading-edge segment outpacing the overall market with a CAGR of 10-15%.

Regarding the SiC market, the investor presentation highlighted significant growth in power/analog/wafer revenue, almost doubling, primarily driven by robust demand in China. This growth was positively impacted by the consolidation of LPE (SiC Epitaxy), with sales comfortably exceeding the target of more than €130 million in 2023. This indicates ASM's strong performance in the SiC market and its successful integration and expansion in SiC epitaxy, aligning with the broader industry trend towards more advanced and efficient semiconductor materials.

Chemical Vapor Deposition (CVD) technology is another area of focus for ASM, particularly in the context of transitioning to new materials like Molybdenum, which is replacing traditional materials such as CVD Tungsten and PVD Copper in interconnect applications. This shift is indicative of the evolving needs within the semiconductor manufacturing process and highlights ASM's adaptability to changing market dynamics.

In summary, ASM's strategic initiatives in ALD, Epitaxy, and CVD technologies underscore the company's commitment to innovation and leadership within the semiconductor equipment market. Through a combination of market foresight, technological prowess, and strategic investments, ASM is well-positioned to capitalize on the growth opportunities presented by the evolving semiconductor landscape. 

PRiME 2024: A Global Convergence on Atomic Layer Processing Set for Honolulu This October

The PRiME Joint International Meeting, organized by the Electrochemical Society and sister societies from Japan and Korea, will take place from October 6-11, 2024, in Honolulu, Hawaii. Anticipating over 4000 participants, the conference will focus on solid-state science, technology, and electrochemistry. Symposium G01 invites submissions on Atomic Layer Deposition and Etching, covering topics from semiconductor applications to energy storage. The deadline for abstract submission is April 12, 2024. Last year's event saw 78 presentations, indicating a strong interest in the field. For visa, travel information, and participation letters, contact ECS representatives.

Every four years, the PRiME Joint International Meeting is held under the auspices of the Electrochemical Society (ECS), joint with its sister Societies of Japan and Korea.

This fall, PRIME 2024 will be held on Oct. 6-11, 2024 in Honolulu, Hawaii, and is expected to gather over 4000 participants and 40 exhibitors from both academia and industry.

The conference has a strong focus on emerging technology and applications in both solid-state science & technology and electrochemistry.

General information and the Meeting Program can be found here: CALL FOR PAPERS.

The organizers of symposium G01 on “Atomic Layer Deposition & Etching Applications, 20” encourage you to submit your abstract(s) on topics, comprising but not limited to:

1. Semiconductor CMOS applications: development and integration of ALD high-k oxides and metal electrodes with conventional and high-mobility channel materials;

2. Volatile and non-volatile memory applications: extendibility, Flash, MIM, MIS, RF capacitors, etc.;

3. Interconnects and contacts: integration of ALD films with Cu and low-k materials;

4. Fundamentals of ALD processing: reaction mechanisms, in-situ measurement, modeling, theory;

5. New precursors and delivery systems;

6. Optical, photonic and quantum applications; applications aiming at Machine Learning, Artificial Intelligence

7. Coating of nanoporous materials by ALD;

8. Molecular Layer Deposition (MLD) and hybrid ALD/MLD;

9. ALD for energy conversion applications such as fuel cells, photovoltaics, etc.;

10. ALD for energy storage applications;

11. Productivity enhancement, scale-up and commercialization of ALD equipment and processes for rigid and flexible substrates, including roll-to-roll deposition;

12. Area-selective ALD;

13. Atomic Layer Etching (‘reverse ALD’) and related topics aiming at self-limited etching, such as atomic layer cleaning, etc.

FYI: Last year in Gothenburg, our symposium G01 on ALD & ALE Applications 19 attracted a record number of 78 presentations, composing a full 4-day schedule of 66 oral (of which 18 invited), plus 12 poster presentations.

We will traditionally attract more attendants from Far East and expect to be as successful this fall in Hawaii.

Abstract submission

Meeting abstracts should be submitted not later than the deadline of April 12, 2024 via the ECS website: Submission Instructions

Invited speakers

A list of confirmed invited speakers (from North America, Asia and Europe) will soon be available.

Visa and travel

For more information, see: VISA AND TRAVEL INFORMATION

In addition, Mrs. Francesca Spagnuolo at the ECS (Francesca.Spagnuolo@electrochem.org) can provide you with an official participation letter issued by the Electrochemical Society.

For (limited) general travel grant questions, please contact travelgrant@electrochem.org.

We are looking forward to meeting you all at our symposium G01 on ALD & ALE Applications 20, in Honolulu | Oct. 6-12, 2024 !

Symposium organizers:

F. Roozeboom, (lead), University of Twente; e-mail: f.roozeboom@utwente.nl,
S. De Gendt, IMEC & Catholic University Leuven,
J. Dendooven, Ghent University,
J. W. Elam, Argonne National Laboratory,
O. van der Straten, IBM Research,
A. Illiberi, ASM Europe,
G. Sundaram, Veeco,
R. Chen, Huazhong University of Science and Technology,
O. Leonte, Berkeley Polymer Technology,
T. Lill, Clarycon Nanotechnology Research,
M. Young, University of Missouri,
A. Kozen, University of Vermont.

ASD2024: Uniting the World of Area Selective Deposition in Historic Old Montreal

Announcement for ASD2024 Workshop

Dates: April 15-16, 2024

Location: Old Montreal, Canada

Welcome and bienvenue to the exciting Area Selective Deposition (ASD) workshop to be held in the picturesque Old Montreal. This two-day event, scheduled for April 15 and 16, offers an enriching platform for both academic and industry professionals to exchange groundbreaking ideas in the field of ASD.

Special Sessions:

1. Pre-Workshop Tutorial: A comprehensive half-day tutorial on April 14 (Sunday afternoon). Note: This session requires an additional fee.

2. Atomic Layer Processing Showcase: A half-day event on April 17 (Wednesday morning), highlighting Canada's advancements in atomic layer processing. This session is included in the conference fee.

Conference Venues:

- Hotel Place d'Armes (55 Rue Saint-Jacques): Main sessions and lunches on Monday and Tuesday will be hosted here. This 4-star hotel is conveniently located near a metro stop.

- Hotel Nelligan (106 Saint-Paul St W): A 4-star boutique hotel, the venue for the opening mixer on Sunday evening and the poster session on Monday evening.

Workshop Highlights:

- Single session format over two days featuring invited and contributed talks.

- A panel discussion focusing on the industrial and academic communication of ASD.

- Networking opportunities with leading experts and peers.

Explore Montreal:

Participants are encouraged to experience the charm of Old Montreal, known for its vibrant restaurants, bars, shopping venues, and historical sites like the Notre Dame Basilica and the port. For sports enthusiasts, the Circuit Gilles Villeneuve offers a unique opportunity for running and cycling.

Organizers:

- Prof. Sean Barry, Carleton University

- Prof. Paul Ragogna, Western University

Scientific Committee:

- Adrie Mackus, Eindhoven University of Technology

- Anjana Devi, Ruhr University Bochum

- Annelies Delabie, IMEC

- Anuja DaSilva, Lam Research

- Dennis Hausmann, Lam Research

- Erwin Kessels, Eindhoven University of Technology

- Gregory Parsons, North Carolina State University

- Han-Bo-Ram Lee, Incheon National University

- Ishwar Singh, IBM

- Keyvan Kashefi, Applied Materials

- Kristen Colwell, Intel

- Mark Saly, Applied Materials

- Marko Tuominen, ASM

- Ralf Tonner-Zech, Wilhelm-Ostwald-Institute für Physikalische und Theoretische Chemie

- Ravi Kanjolia, EMD Electronics

- Robert Clark, TEL

- Sang Hoon Ahn, Samsung Electronics

- Seung Wook Ryu, SK hynix

- Stacey F. Bent, Stanford University

Contact Information:

asd2024.ca

Balancing Fundamental and Applied ALD with Stacey Bent – ALD Stories Ep. 26

In Episode 26, Professor Stacey Bent from Stanford University joins to discuss all aspects of her career, including early area selective deposition work, how her different academic appointments in chemistry and engineering have influenced the direction of her work, and how ALD can be used in energy applications. Stacey and Tyler also chat about how Stacey finds the best paths for her students, how being a professor and Vice Provost feedback to each other, and new programs she has initiated in her Vice Provost position. 

In this episode: 

00:00 Introduction 

03:45 Area Selective Work 

15:40 Chemistry & Engineering Backgrounds 

21:20 ALD for energy applications 

33:54 Stacey as an advisor 

36:19 Vice Provost position

 

The Future of Nanoimprint Lithography: Exploring Possibilities and Challenges for High-Volume Production

Nanoimprint lithography (NIL) has emerged as a promising technique for the replication of intricate nano-scale features, offering higher resolution and uniformity compared to traditional photolithography methods. As semiconductor technology advances towards smaller and more complex structures, NIL holds the potential to revolutionize high-volume production processes. In this blog post, we'll delve into the current status of nanoimprint lithography and the possibilities it presents for future high-volume productions, as well as the main issues and concerns that need to be addressed.

NIL utilizes a process where a patterned mask is brought into contact with a resist-coated substrate. The resist fills the relief patterns in the mask through capillary action, creating precise nano-scale features. With a focus on simplicity and cost-effectiveness, NIL doesn't require the complex optics found in traditional photolithography, making it an attractive option for semiconductor memory applications.

Early work on combining NIL and Atomic Layer Etching by AlixLabs Founders

AlixLabs (www.alixlabs.com)  founders and Lund Nano Lab (Lund University, Sweden) collaborated 2018 to exploit Atomic Layer Etching (ALE) for improved NIL quality and resolution. ALE involved Cl2 monoatomic layer adsorption on silicon, followed by controlled Cl2-modified silicon layer removal using argon bombardment. This precision process allowed diverse nanopatterns to be etched onto silicon wafers with electron beam lithography. The treated wafers served as robust nanoimprint stamps in a thermal process, transferring features as small as 30 nm into a poly(methyl methacrylate) layer. ALE's potential for ultrahigh-resolution nanoimprint stamp fabrication advances nanofabrication techniques significantly.

Most Recent Achievements:

Recent study by TEL and Canon have demonstrated NIL's resolution capabilities of better than 10 nm, positioning the technology as a candidate for printing multiple generations of critical memory levels using a single mask. The potential to eliminate material waste by applying resist only where necessary adds to its appeal. Moreover, the simplicity and compactness of NIL equipment allow for clustered setups, enhancing productivity.

NIL Addressing Challenges in DRAM Scaling:

Dynamic Random Access Memory (DRAM) memory faces the challenge of continued scaling, with roadmap targets aiming at half pitches of 14 nm and beyond. The complexities of achieving tighter overlays, greater precision in critical dimensions, and edge placement errors demand innovative solutions. In DRAM fabrication, overlay requirements are even more stringent than in NAND Flash, with an error budget of 15-20% of the minimum half pitch.

Edge Placement Error (EPE):

EPE, the difference between intended and printed features, poses a significant challenge in modern semiconductor manufacturing. The intricacies of multiple patterning schemes and intricate device layouts contribute to EPE's complexity. Ensuring accurate placement of features is critical for maintaining device yield and performance.

The Quasi-Atomic Layer Etch (Quasi-ALE) process

The process is a specialized etching technique employed in advanced semiconductor manufacturing, particularly in processes like Nanoimprint Lithography (NIL). Quasi-ALE combines elements of Atomic Layer Etching (ALE) and conventional etching methods to achieve precise and controlled material removal. In the context of Nanoimprint Lithography, Quasi-ALE is used to etch materials with exceptional precision, targeting nanoscale features while minimizing damage to the surrounding areas. It involves a cyclic process where alternating etching and passivation steps are applied to the substrate. Each cycle removes a controlled layer of material, ensuring highly uniform etching and minimal lateral etch. One can discribe Quasi-ALE as a more productive way of performing ALE.

The key steps of the Quasi-ALE process typically involve:

1. Etch Step: During this step, a reactive gas is introduced into the etch chamber, which chemically reacts with the material to be removed. This reaction results in the selective removal of the material layer.

2. Passivation Step: In this step, a passivating species is introduced, forming a protective layer on the substrate surface. This layer prevents further etching and preserves the material beneath.

3. Purge and Repeat: The chamber is purged to remove any excess gases, and the process is repeated in a cyclical manner. Each cycle removes a controlled atomic layer of material.

Quasi-ALE is particularly advantageous for applications requiring high precision and control, such as in Nanoimprint Lithography, where maintaining accurate pattern dimensions and minimizing damage is critical. By combining the benefits of both ALE and traditional etching, Quasi-ALE enables advanced semiconductor manufacturing processes to achieve unprecedented levels of accuracy and uniformity.

Addressing EPE with Nanoimprint Lithography:

Researchers are actively exploring techniques to mitigate edge placement errors in nanoimprint lithography. This includes focusing on overlay accuracy, critical dimension uniformity (CDU), and local CDU. Compensatory methods such as dose control and reverse tone pattern transfer are being investigated to improve CDU and minimize errors.

The Role of Dose Control:

Varying the exposure dose offers a means of achieving small shifts in critical dimensions. Initial studies suggest that dose variations could lead to CD shifts of one to 2 nm. This strategy holds promise for enhancing CDU in the imprint process.

Reverse Tone Pattern Transfer:

Reverse tone processes, involving spin-on hard mask (SOHM) application and etch-back, offer an alternative approach to pattern transfer. While this method provides advantages such as reduced resist erosion and improved wall angles, trade-offs between CDU and line width roughness (LWR) need to be addressed.

Looking Ahead: The Possibilities and Challenges:

While NIL exhibits impressive potential, there are key challenges to overcome before it can be effectively integrated into high-volume semiconductor manufacturing. Ensuring precise overlay accuracy, managing complex CDU requirements, and effectively addressing edge placement errors remain pivotal. As the industry strives to achieve the roadmap's aggressive scaling targets, the evolution of nanoimprint lithography will undoubtedly play a crucial role.

Nanoimprint lithography is poised to reshape the semiconductor manufacturing landscape, offering higher resolution and cost-efficiency compared to traditional methods. With ongoing research and development, addressing challenges such as overlay accuracy, CDU, and EPE, the path to successful high-volume production through NIL seems promising. As technology continues to advance, the journey towards perfecting nanoimprint lithography is an exciting one, holding the potential to shape the future of chip fabrication.

Tokyo Electron (TEL): 

TEL specializes in Nanoimprint Lithography (NIL) technology, offering precision equipment, advanced etching solutions, and expertise in process control. They excel in alignment, overlay correction, CDU management, and etching technology.

TEL has previously demonstrated that for sub 7  nm CMOS technology, ALE and ALD integration improves SAC and patterning processes, achieving precise CD shrinking and enhanced selectivity.

Canon: 

Canon contributes to Nanoimprint Lithography (NIL) advancement by leveraging TEL's strengths in alignment, overlay correction, CDU management, and advanced etching solutions. They integrate these capabilities with the Reverse Tone Pattern Transfer, ensuring precise pattern replication and fidelity. Canon's focus on innovation drives high-resolution, cost-effective solutions for semiconductor manufacturing.

Canon has introduced a groundbreaking solution in the field of semiconductor technology with the development of the world's first mass-production equipment called the "FPA-1200NZ2C." This innovative tool utilizes nanoimprint lithography, a cutting-edge technique that involves imprinting nanometer-scale mask patterns onto substrates. By adopting this novel approach, Canon aims to overcome the limitations of conventional miniaturization methods. The FPA-1200NZ2C is already in use by Toshiba Memory, a prominent semiconductor memory manufacturer. This advancement marks a significant step forward in semiconductor manufacturing, enabling the creation of more intricate and advanced circuit patterns.

Sources:

High-Definition Nanoimprint Stamp Fabrication by Atomic Layer Etching — Lund University

Nanoimprint post processing techniques to address edge placement error (spiedigitallibrary.org)

Nanoimprint Lithography | Canon Global

FPD Lithography Equipment | Canon Global

Benefits of atomic-level processing by quasi-ALE and ALD technique - IOPscience

www.alixlabs.com

Acknowledgement :

Thanks for sharing the SPIE article on LinkedIn and giving insights Frederick Chen!