Atomic Layer Etching as a Scaling Enabler: From Isotropic Chemistry to Selective, Directional, and Geometry-Driven Patterning

Continued scaling in semiconductor manufacturing increasingly relies on atomic-scale control of etching for complex 3D material stacks, making patterning precision a growing industrial bottleneck. Atomic layer etching (ALE) has emerged as a key enabler, with plasma-driven anisotropy and surface-chemistry control allowing improved selectivity and profile fidelity for advanced logic and memory integration. Current approaches emphasize decoupling surface modification from material removal to enable low-temperature, highly controlled processes.

From an industry perspective, the focus is shifting toward systematic ALE process development frameworks that combine thermodynamic screening, tailored half-cycle chemistries, and experimental verification of etch rates and selectivity. These strategies are increasingly relevant as device architectures push beyond conventional materials and dimensions. At the same time, ALE is gaining attention for its potential to reduce process complexity, energy use, and chemical consumption, positioning it as both a scaling and sustainability enabler for future semiconductor manufacturing.

In a recent paper by Smith et al (reference below), Thermal ALE is described as a purely chemical, vapor- or gas-phase process in which both the surface modification and removal steps are self-limiting and thermally activated. Volatile products are typically formed through ligand-exchange reactions that generate metalorganics. Because no ions are involved, this mode of ALE is intrinsically isotropic, leading to uniform material removal in all directions. This makes thermal ALE attractive for conformal trimming, lateral recessing, and highly selective etches, but fundamentally limits its ability to produce vertical, profile-controlled features.

(a) Periodic table of the elements showing which metals, metal oxides, and metal nitrides have had ALE processes developed for them. In developing a new ALE process, determining the nature of the volatile etch product is critical, with some metals proving more favorable to etching via the formation of volatile metalorganics and others via volatile metal halides. Data compiled from the ALE Database [reference]. (b) An outline of the pathways by which reported ALE processes can proceed. Metals, metal oxides, and metal nitrides can be halogenated, with the modified layer removed by subsequent Ar⁺ sputtering or ligand exchange. Metals can be oxidized or nitrided, and the metal oxide or nitride subsequently etched. (c) Gibbs free energy minimization and volatility diagram analysis can be used to theoretically screen possible etch processes. (d) Various surfaces of Ni modified with (1) surface O, (2) mixed surface and subsurface O, and (3) subsurface O. The Gibbs free energy of reaction showed the importance of having an oxidized sublayer to achieve favorable thermodynamic etching. Adapted from ref [reference]. (e) Analysis of Gibbs free energy of reaction: nitridation of nickel could form metastable Ni3N, which can be etched through favorable reactions with formic acid, forming dimers of nickel formates. by Smith et al (reference below)

In contrast, plasma ALE introduces ions as an active control parameter, most commonly during the removal step. A plasma first forms a chemically modified surface layer, such as a halogenated or oxidized film, which is then selectively removed by directional ion bombardment within a narrow ALE energy window. The momentum of the ions provides anisotropy, enabling vertical etching with atomic-scale precision while suppressing continuous sputtering. This directionality comes at the cost of tighter process windows and increased sensitivity to ion-induced damage.

A hybrid plasma–thermal ALE approach is presented as a way to decouple anisotropy from volatilization chemistry. In this scheme, plasma exposure is used to directionally modify the surface or precisely control the thickness of the modified layer, while removal proceeds via isotropic, thermally driven ligand-exchange reactions. This allows anisotropy to be engineered through selective surface modification rather than sputtering alone. Overall, the key conclusion is that isotropic versus directional behavior in ALE is determined by how and where ions are used, not simply by whether the process is labeled thermal or plasma.

Comment on Geometry

From an industrial standpoint, atomic layer etching is emerging as a core patterning technology as device scaling shifts toward complex 3D architectures and heterogeneous material stacks where conventional plasma etching reaches its limits. Smith et al. highlight that future adoption will be driven by selective ALE, enabled by surface-chemistry engineering, controlled anisotropy, and precise balance between etching and deposition rather than brute-force sputtering. In this landscape, AlixLabs’ use of geometrical selectivity extends the ALE paradigm by exploiting feature pitch and local geometry as an additional selectivity axis, enabling pattern multiplication and critical dimension scaling without added lithography complexity. The convergence of chemical, directional, and geometrical selectivity positions ALE not as a niche technique, but as a scalable, cost- and sustainability-aligned solution for next-generation semiconductor manufacturing.

The relevance of these advances is underscored by their recent and upcoming exposure at major industry forums. Results demonstrating sub-10 nm, high-aspect-ratio patterning with APS™ were presented at the 248th Electrochemical Society (ECS) Meeting in October 2025, marking an important milestone in validating the technology on bulk silicon using mature lithography. This momentum continues at SPIE Advanced Lithography + Patterning 2026, where AlixLabs will present new APS™ results spanning nanoimprint lithography and simplified self-aligned quadruple patterning, including joint work with UMC. Together, these events signal APS™ and geometrically selective ALE moving from concept and lab validation toward broader industrial evaluation and integration.

AlixLabs announced that Dr. Dmitry Suyatin, CIPO and Co-Founder, presented new APS™ (Atomic Layer Etching Pitch Splitting) results at the 248th ECS Meeting in Chicago (October 12–16, 2025), demonstrating high-aspect-ratio, narrow-fin patterning on bulk silicon with critical dimensions below 10 nm using standard 193-nm immersion lithography. The results reinforce APS™ as a viable path to advanced logic patterning without next-generation scanners, enabling reduced process complexity and cost. Supported by recent patent milestones and progress toward a beta tool planned for operation in fall 2026, APS™ is positioned to move from lab-scale validation toward production-grade refinement, aligning with AlixLabs’ goal of making advanced semiconductor manufacturing more accessible and sustainable.

AlixLabs announced its participation at SPIE Advanced Lithography + Patterning in San Jose, where two abstracts by Reza Jafari Jam et al and Robin Athlé et al have been accepted for oral presentation, including one in collaboration with United Microelectronics Corporation (UMC). The presentations will showcase recent progress in APS™ (Atomic Layer Etching Pitch Splitting), demonstrating sub-13 nm half-pitch patterning on silicon and a simplified alternative to self-aligned quadruple patterning that delivers a 4× density increase using a streamlined three-step process. Together, the talks highlight APS™ as a precise, cost-effective, and more sustainable approach to advanced nano-patterning that reduces complexity compared with conventional multi-patterning schemes.

Reference:

AlixLabs – News

Adapted from Smith, T. G. and Chang, J. P., Atomic Layer Etching in Patterning Materials: Anisotropy, Selectivity, Specificity and Sustainability, Plasma Chemistry and Plasma Processing, 46:9 (2026), © The Author(s) 2026. Published by Springer Nature and licensed under CC BY 4.0.

Smith, T. G., Chang, J. P., Atomic Layer Etching in Patterning Materials: Anisotropy, Selectivity, Specificity and Sustainability, Plasma Chemistry and Plasma Processing, 2026, 46:9.

Atomic Layer Etching in Patterning Materials: Anisotropy, Selectivity, Specificity and Sustainability | Plasma Chemistry and Plasma Processing

Intel Foundry Advances Future Logic Scaling with Manufacturable 2D Transistors and High NA EUV Integration

Intel Foundry has demonstrated concrete momentum in de-risking 2D field-effect transistors as a future scaling path beyond silicon, through long-term collaboration with Imec. Results presented at IEDM show a world-first, 300 mm fab-compatible integration of key 2DFET modules, including source/drain contacts and gate stacks, using transition-metal dichalcogenide channels (WS₂ and MoS₂ for n-type, WSe₂ for p-type devices). The core innovation is a selective oxide etch applied to high-quality Intel-grown 2D layers capped with AlOx/HfO₂/SiO₂, enabling damascene-style top contacts while preserving the integrity of atomically thin channels. 

Fab-compatible 2D FET process integration on 300 mm wafers, demonstrating selectively recessed oxide caps that enable damascene-style top contacts on WS₂, MoS₂, and WSe₂ channels, along with replacement-oxide gate stacks and interlayer-selective removal that scales gate CET from 2.5 nm to 1.5 nm. The work establishes manufacturable contact and gate modules as fundamental building blocks for future 2D transistor integration (IEDM Paper 10.1, Q. Smets et al.).

By validating these processes in production-class integration flows, Intel Foundry is addressing two of the most critical barriers to 2D transistor adoption—contact resistance and gate integration—while enabling realistic benchmarking, modeling, and design pathfinding. This work showcases Intel Foundry’s strategy of emphasizing manufacturability early in research, positioning 2D transistors as a credible, scalable option for future logic nodes and stacked transistor architectures.

Fab-compatible 2D FET process integration demonstrated on 300 mm wafers. An imec-led research team reports new manufacturable process modules enabling scalable integration of 2D field-effect transistors in a 300 mm pilot line. Exploiting the strong chemical selectivity and anisotropic van der Waals structure of transition-metal dichalcogenides, the work demonstrates for the first time a selectively recessed oxide cap that enables damascene-style top contacts on monolayer WS₂, MoS₂, and multilayer WSe₂ channels, resulting in improved contact resistance. A replacement-oxide gate stack with scaled equivalent oxide thickness is also shown. In addition, a novel interlayer-selective removal process based on liquid intercalation reduces the top-gate capacitance-equivalent thickness from 2.5 nm to 1.5 nm. Together, these modules form fundamental building blocks for future 2D integration technologies. Top row: epitaxial TiN growth enabled by a 2D template (left, center) and chemical confirmation of a Ru top contact on a multilayer WSe₂ channel (right). Bottom row: schematic comparison of the baseline top-gate stack comprising interlayer, cap, and top-up oxides; full replacement-oxide process; and selective lateral interlayer removal from contact trenches. Based on Paper 10.1, “Selective Etch Process for Fab-Compatible Top Contacts, Replacement Oxide and Interlayer Removal in 2D FETs,” Q. Smets et al., presented at IEDM.

In parallel with its 2D transistor research, Intel Foundry has made significant progress in High Numerical Aperture EUV lithography as a cornerstone enabler for future device scaling. In close collaboration with ASML, Intel Foundry has completed acceptance testing of the TWINSCAN EXE:5200B, the most advanced High NA EUV scanner currently available. This system builds on the first-generation EXE:5000 platform while extending productivity to 175 wafers per hour and achieving overlay performance of 0.7 nm, metrics that are directly relevant to high-volume manufacturing rather than purely experimental use. Intel’s early access to High NA EUV, beginning with the first commercial installation in its Oregon R&D fab in 2023, positions the company as a lead development partner shaping how High NA lithography is qualified, integrated, and eventually deployed in production logic nodes.

From a technology perspective, the EXE:5200B introduces several enabling innovations that are critical for advanced transistor architectures, including gate-all-around and future stacked devices. A higher-power EUV source supports practical exposure doses and improved resist process windows, helping control line edge and line width roughness at extremely small critical dimensions. A redesigned wafer stocker architecture improves lot logistics and thermal stability, which is especially important for multipass and multiexposure flows anticipated with High NA patterning. Finally, tighter alignment control reflects advances in stage mechanics, sensing, and environmental isolation, all of which become essential as overlay tolerances approach the sub-nanometer regime. For Intel Foundry customers, these capabilities translate into more flexible design rules, reduced reliance on complex multi-patterning schemes, fewer masks and process steps, and faster yield learning. Together, Intel’s High NA EUV progress and its 2D transistor integration work reflect a coherent strategy: pairing next-generation lithography with manufacturable device innovations to ensure that future scaling paths are both technically viable and production-ready.

Sources:

How Collaboration in High NA EUV and Transistor R&D Are Shaping Future Waves of Device Innovation

IEEE IEDM 2025 | 10-1 | Selective Etch Process for Fab-compatible Top Contacts, Replacement Oxide and Interlayer Removal in 2D FETs

JSR, Lam Research, and SK hynix Push the Boundaries of ASML´s EUV Semiconductor Manufacturing

JSR Corporation, including its subsidiary Inpria Corporation, and Lam Research have entered into a cross-licensing and collaboration agreement to accelerate the development of next-generation semiconductor manufacturing technologies. The partnership combines JSR’s expertise in photoresists and advanced materials—anchored by Inpria’s metal-oxide resists (MORs) for extreme ultraviolet (EUV) lithography—with Lam’s leadership in wafer fabrication equipment and process technology. By sharing intellectual property and integrating complementary capabilities, the companies aim to address scaling and patterning challenges as chipmakers pursue smaller, denser, and more energy-efficient devices for advanced logic and memory applications.

Inpria’s MORs, based on spin-on tin-oxide materials, provide high EUV photon absorption, excellent etch resistance, and reduced line edge roughness compared with conventional organic resists. These materials are fully compatible with existing lithography systems, making them attractive for high-volume production. To meet growing demand, JSR is expanding its global footprint with new R&D facilities in Japan and a production plant in Korea set to begin operations in 2026. Lam Research complements this with its Aether® dry resist technology, which replaces wet spin-coating and development with fully dry, vapor-phase processes. This innovation improves uniformity, reduces stochastic defects, and strengthens EUV absorption, enabling higher resolution and sensitivity. Aether has demonstrated direct-print 28 nm pitch patterning for logic and is already being adopted by leading memory manufacturers, offering both performance advantages and sustainability gains through reduced chemical and energy use.

These advances align with a broader industry shift toward tighter integration of materials and equipment solutions, exemplified by SK hynix’s installation of the world’s first commercial High-NA EUV lithography tool, ASML’s TWINSCAN EXE:5200B, at its M16 fab in Icheon, South Korea. Featuring a numerical aperture of 0.55—compared with 0.33 in current Low-NA EUV systems—the High-NA platform boosts resolution by 40%, enabling transistors about 1.7× smaller and wafer transistor densities nearly 2.9× higher. For SK hynix, this milestone supports the development of next-generation DRAM, reduces process complexity, lowers costs, and strengthens competitiveness in AI memory and advanced compute markets.

As one of the “big three” memory makers alongside Samsung and Micron, SK hynix has established itself as the leader in high-volume DRAM manufacturing. It was the first to mass-produce DDR5 and high-bandwidth memory (HBM3), both essential for AI and high-performance computing. Its early adoption of EUV lithography for DRAM production—and now the industry-first deployment of ASML’s High-NA EUV system—underscores its position at the forefront of DRAM scaling and density. Together, the innovations from JSR, Inpria, Lam Research, and SK hynix illustrate how collaboration across the semiconductor ecosystem is driving the breakthroughs required to sustain Moore’s Law in the era of AI and advanced computing.

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Do you want me to keep the headline-style opening as above, or make it read more like a press release introduction with a formal lead sentence?

Sources:

JSR Corporation/Inpria Corporation and Lam Research Enter Cross Licensing and Collaboration Agreement to Advance Semiconductor Manufacturing

Dry Resist Patterning Progress and Readiness Towards High NA EUV Lithography

INPRIA | A world leader world leader in metal oxide photoresist design, development and manufacturing

Inpria Co-Developing Metal Oxide Resist with SK hynix to Reduce Complexity of Patterning for Next-Generation DRAM | 2022 | News | JSR Corporation

SK hynix Introduces Industry’s First Commercial High NA EUV

ASML Posts Strong Q1 2025 Results Amid AI-Driven Demand and Tariff Uncertainty

ASML kicked off 2025 with solid first-quarter performance, beating expectations on both earnings and revenue as demand for advanced lithography tools—driven by AI and next-generation semiconductor nodes—remained robust. While the company reaffirmed its growth outlook for 2025 and 2026, it also flagged increasing geopolitical uncertainty, particularly around US-China tariffs, as a risk factor for the months ahead.

ASML delivered strong Q1 2025 results, with earnings per share of $6.82 and revenue of $8.80 billion, reflecting a 56% year-over-year increase. The company met or exceeded guidance across major financial metrics, with gross margins at 54%, supported by favorable EUV system configurations and higher average selling prices. Net system sales reached €5.7 billion—€3.2 billion from EUV and €2.5 billion from non-EUV—while Installed Base Management sales added €2 billion. Bookings totaled €3.9 billion, mostly from logic customers. Despite a seasonal dip in free cash flow due to payment timing and capital investments, ASML remains financially strong with €9.1 billion in cash.

CEO Christophe Fouquet and CFO Roger Dassen emphasized the ongoing strength of AI as a demand driver, particularly in advanced logic and memory, while acknowledging growing macroeconomic and geopolitical uncertainties—especially around tariffs. They reiterated revenue expectations for 2025 between €30 billion and €35 billion, with 2026 also anticipated to be a growth year. However, they cautioned that new tariff dynamics introduce significant unknowns for both ASML and its customers, which may affect gross margins and the broader supply chain.

On the technology front, ASML made progress with both its Low NA and High NA EUV systems. The NXE:3800E tool is now shipping at full spec and is seeing strong adoption among logic and memory customers aiming for single-expose EUV. Meanwhile, the High NA NXE:5000 has demonstrated better maturity compared to the Low NA at a similar stage, with customers like Intel and Samsung reporting substantial gains in productivity and process simplification. ASML shipped its fifth NXE:5000 in Q1 and is beginning shipments of the NXE:5200, which will be critical for phase two customer evaluations. Full-scale adoption is expected from 2026–2028, contributing to ASML’s long-term revenue forecast of €44 billion to €60 billion by 2030.

ASML addressed growing concerns over US and China tariffs, highlighting the high level of uncertainty surrounding their scope and impact. The company is actively assessing both direct and indirect consequences, including tariffs on system sales, parts imports, and servicing operations. ASML emphasized that it is working closely with customers and suppliers to mitigate disruptions and ensure that tariff-related costs are fairly distributed across the value chain, rather than being absorbed solely by ASML. While management acknowledged that these discussions are still evolving and outcomes remain unclear, they cautioned that tariffs could introduce volatility in margins, supply chain planning, and customer delivery schedules. Despite this, ASML noted that the current business conversations with customers remain unchanged and the long-term strategic investment momentum—especially in logic and AI-related capacity—appears resilient.

Sources:

ASML Holding N.V. 2025 Q1 - Results - Earnings Call Presentation (NASDAQ:ASML) | Seeking Alpha

ASML Holding N.V. (ASML) Q1 2025 Earnings Call Transcript | Seeking Alpha

JSR Expands Global Semiconductor Material Capabilities with New Photoresist Facilities, Advanced MOR Variants, and Strategic Acquisition of CVD/ALD Precursor Firm

JSR Corporation is expanding its global development and production of advanced photoresists by establishing a new R&D center in Japan and constructing a semiconductor photoresist plant in Korea. Since acquiring Inpria Corporation in 2021, JSR has been commercializing Metal Oxide Resist (MOR) for EUV lithography. The new R&D center in Japan’s Kanto region will enhance collaboration with global customers and partners, while the Korean plant, expected to begin operations in 2026, will handle the final production process for MOR to support local adoption. JSR aims to drive innovation in photoresists and help customers establish commercial production processes worldwide.

JSR's MOR, developed through its 2021 acquisition of Inpria Corporation, is a next-generation photoresist designed for EUV lithography. MOR is based on metal oxide nanoparticles, offering superior etch resistance and improved pattern resolution compared to traditional chemically amplified resists (CARs). This allows for finer feature definition and reduced line-edge roughness, critical for advanced semiconductor manufacturing below 10 nm. JSR has been scaling MOR for commercial adoption, with major semiconductor manufacturers evaluating its use in high-volume production. The company is expanding its R&D and manufacturing capacity, including a new R&D center in Japan and a production facility in Korea, to support global adoption of MOR.

JSR have investigated different flavors of MOR for EUV lithography, primarily focusing on variations in metal cores and process optimizations. Initially, zirconium (Zr) and hafnium (Hf) based MORs were explored, but their relatively low EUV absorption led researchers to investigate alternative metal cores such as titanium (Ti), zinc (Zn), indium (In), and tin (Sn). These new metal cores exhibited improved lithographic performance, achieving higher EUV absorption, smaller particle size, and better scum reduction. Additionally, process optimizations such as using higher dissolution rate photoacid generators (PAGs), new organic solvent developers, and lower soft bake temperatures were tested to improve scum removal and resolution. The new metal core variants demonstrated resolutions down to 13 nm with reduced defects, suggesting their potential for advanced semiconductor manufacturing.

In August 2024, JSR Corporation completed the acquisition of Yamanaka Hutech Corporation (YHC), a Kyoto-based manufacturer specializing in high-purity chemicals for semiconductor manufacturing. This strategic move allows JSR to expand its product portfolio to include Chemical Vapor Deposition (CVD) and Atomic Layer Deposition (ALD) precursors, which are essential for forming advanced and complex semiconductor device structures. YHC, established in 1960, has over 60 years of experience in advanced molecular design, synthesis technology, and quality control systems, supplying high-quality CVD/ALD precursors to leading-edge semiconductor device manufacturers. The acquisition aligns with JSR's strategy to strengthen its position as a global supplier of semiconductor materials, enhancing its capabilities in both miniaturization and device structure innovation.

Sources:

JSR Expands Global Development and Production Functions for Leading-Edge Photoresists | 2024 | News | JSR Corporation

tec125-4.pdf

Lam Research’s Dry Resist: A Breakthrough in EUV Lithography for Next-Generation Logic and Memory Manufacturing

Lam Research’s dry resist technology represents a major shift in EUV lithography and semiconductor patterning, addressing critical challenges such as stochastic defectivity, resolution limitations, and cost-efficiency. With recent qualifications for advanced DRAM and 2nm logic manufacturing, along with a growing ecosystem for high-volume production, dry resist is positioned to disrupt traditional chemically amplified resists (CARs) and enable future High-NA EUV adoption.

One of the most significant recent developments is Lam’s qualification of dry resist for 28nm pitch BEOL logic at 2nm and below in collaboration with imec. This qualification confirms that dry resist can eliminate multi-patterning steps, reducing complexity and improving EUV throughput. The process is designed to work with both low-NA and high-NA EUV scanners, ensuring its relevance for sub-2nm logic scaling. This represents a key milestone in extending direct EUV printing to future logic nodes, an approach that could significantly lower lithography costs while improving pattern fidelity.

In addition, a leading DRAM manufacturer has selected Lam’s Aether dry resist technology as its production tool of record for advanced DRAM nodes. This decision highlights dry resist’s low-defect, high-fidelity patterning capabilities, which are essential for scaling memory architectures. The technology enables lower exposure doses while reducing stochastic defects, which are a major concern in EUV-based DRAM production. Given that Samsung, SK Hynix, and Micron are all increasing their reliance on EUV for next-generation DRAM, Lam’s dry resist is well-positioned for widespread adoption in the memory sector.

To ensure a stable supply chain for dry resist materials, Lam Research has partnered with Entegris and Gelest, a Mitsubishi Chemical Group company. This collaboration ensures reliable dual-source precursor production, providing chipmakers with long-term process stability. The partnership also focuses on the development of next-generation high-NA EUV precursors, further strengthening dry resist’s role in future sub-2nm manufacturing.

SEM images of 28 nm pitch line/space patterns imaged with 0.33NA EUV in dry resist from Entegris precursor.

A critical enabler of dry resist technology is its atomic layer deposition (ALD) process, which replaces traditional spin-coating used in CARs. ALD-based vapor-phase deposition offers higher uniformity, eliminating polymer chain variations found in conventional resists. It also allows precise thickness control, which is essential for optimizing EUV photon absorption and etch selectivity. Unlike CARs, which rely on a complex mixture of polymers, dry resist materials are based on single-component metal-organic precursors such as organo-tin oxides. These materials provide higher EUV photon absorption, improving sensitivity and pattern resolution.

Another key advantage of dry resist is its anisotropic dry development process, which replaces wet solvent-based development. Traditional CAR-based EUV resists require organic solvents or aqueous bases, leading to stochastic defects, material loss, and waste. Dry resist, by contrast, is developed entirely in the gas phase, selectively removing unexposed regions and forming a negative-tone image. This eliminates line collapse and delamination issues, improving yield stability. Additionally, the elimination of wet chemistries significantly reduces chemical waste, making dry resist a more sustainable solution with five to ten times lower material consumption compared to traditional resists.

Lam’s dry resist technology is poised to disrupt traditional CAR-based EUV lithography, particularly as the industry moves toward High-NA EUV adoption. By reducing multi-patterning dependency, the technology enhances cost-effective EUV scaling, making it an attractive solution for both logic and memory manufacturers. This positions Lam as a key leader in next-generation EUV resist solutions, challenging conventional resist suppliers like JSR, TOK, and Inpria.

From a sustainability perspective, dry resist significantly lowers EUV exposure dose requirements, leading to higher scanner throughput and lower energy consumption. Its reduced defectivity translates to higher yield per wafer, further enhancing cost-efficiency. The collaboration with Entegris and Gelest ensures supply-chain stability, making dry resist a viable and scalable technology for sub-2nm nodes.

The patent US20220020584A1 mentions several Lam Research tools that play a role in the dry resist deposition, patterning, and development process for EUV lithography. The Altus system is referenced for deposition, likely for metal or dielectric films in the dry resist stack, while the Striker plasma-enhanced atomic layer deposition (PEALD) system may be used for precise resist or underlayer deposition. The Versys platform, known for plasma processing, is relevant to the dry development process, and the Syndion system, typically used for deep silicon etching, may have applications in pattern transfer. Additionally, the Reliant tool is designed for volume manufacturing, possibly adapted for integrating dry resist technology, and the Kiyo plasma etch system is likely involved in etching after the dry resist development stage. These tools collectively enable Lam’s dry resist process to achieve improved resolution, defect reduction, and cost efficiency in advanced EUV lithography.

The patent US20220020584A1, filed by Lam Research Corporation, describes an innovative dry development process for EUV photoresists, which eliminates the need for traditional wet chemical development methods. The patent details a dry resist system deposited via vapor-phase precursors, forming a highly uniform, single-component material that enhances EUV photon absorption and sensitivity. The dry development process selectively removes unexposed resist regions using plasma-based or plasma-free chemical methods, significantly reducing line collapse and defectivity while improving resolution at sub-2nm nodes. By integrating dry resist deposition, EUV exposure, and dry development into a single cluster tool, the patented technology enables scalable, high-volume EUV manufacturing with lower chemical consumption and improved process sustainability, positioning it as a key enabler for High-NA EUV lithography.

Lam Research’s dry resist technology represents a significant development in EUV lithography by addressing key challenges in stochastic defectivity, process cost, and sustainability. Its qualification for 2nm logic and advanced DRAM manufacturing confirms its readiness for high-volume production. By utilizing ALD for precise resist deposition and securing a stable precursor supply through partnerships with Entegris and Gelest, Lam has established a strong foundation for scaling the technology. 

Sources:

Lam Research Press Release on DRAM Adoption (Jan 2025): Lam Research

imec Qualification of Dry Resist for 2nm Logic (Jan 2025): imec

Entegris and Gelest Collaboration Announcement (July 2022): Entegris

Overview of Dry Resist ALD and Precursor Chemistry: SemiAnalysis

ASML High-NA EUV Roadmap and Implications for Dry Resist: ASML

Lam Reserach patent application US20220020584A1: US20220020584A1.pdf

Integrating Metal-Oxide EUV Resists with Directed Self-Assembly for High-Resolution Chemical Patterning

Extreme ultraviolet (EUV) lithography struggles with resist materials that can deliver both high resolution and acceptable throughput, often resulting in rough patterns and printing defects that degrade semiconductor performance. To overcome this, researchers are exploring directed self-assembly (DSA) of block copolymers (BCPs), which can naturally rectify pattern defects when aligned to EUV-defined chemical guides. However, metal-oxide EUV resists (MORs), which provide high resolution, face challenges in converting their patterns into effective chemical guides for DSA integration.

This study presents a novel method using hydrogen silsesquioxane (HSQ), a negative tone resist, to create chemical patterns for integrating MORs with DSA. The process involves forming a sacrificial chromium pattern from HSQ, which is later replaced with a polyethylene oxide brush layer and a nonpolar polystyrene brush. These steps allow the successful assembly of polystyrene-block-poly(methyl methacrylate) BCPs, achieving 24 nm full-pitch resolution. This approach shows potential for producing sub-10 nm patterns by combining high-χ BCPs with MOR-based EUV lithography, advancing next-generation semiconductor fabrication.

DSA of BCPs is a promising nanofabrication technique that utilizes the phase separation properties of BCPs to create highly ordered nanoscale patterns with feature sizes below 10 nm. In DSA, BCPs self-organize into distinct microdomains, forming well-defined structures that can be guided using chemoepitaxy or graphoepitaxy. Chemoepitaxy involves chemically patterned surfaces that influence the alignment and orientation of BCP domains, while graphoepitaxy uses topographical features to achieve similar control. High-χ (chi) BCPs are often used to achieve finer pattern resolutions, and material optimizations such as selecting appropriate substrates and brush layers are crucial to improving pattern quality and reducing defects. DSA has been explored for various semiconductor applications, including the creation of dense line-space arrays, hole shrink patterns, and advanced memory devices, offering significant potential to enhance pattern fidelity, reduce defectivity, and lower manufacturing costs.

Sources:

High-resolution chemical patterns from negative tone resists for the integration of extreme ultraviolet patterns of metal-oxide resists with directed self-assembly of block copolymers | Journal of Vacuum Science & Technology B | AIP Publishing

https://www.spiedigitallibrary.org/conference-proceedings-of-spie/12956/3010817/Material-and-process-optimization-for-EUV-pattern-rectification-by-DSA/10.1117/12.3010817.full

https://journals.spiedigitallibrary.org/conference-proceedings-of-spie/12497/124970K/EUV-lithography-line-space-pattern-rectification-using-block-copolymer-directed/10.1117/12.2657990.full
https://www.mdpi.com/2073-4360/12/10/2432

https://www.spiedigitallibrary.org/conference-proceedings-of-spie/PC12054/PC1205402/Exploring-the-synergy-between-EUV-lithography-and-directed-self-assembly/10.1117/12.2622565.full
https://journals.aps.org/prb/abstract/10.1103/PhysRevB.101.085407

ASML's 2024 Investor Day Highlights EUV-Driven Revenue Projections of €44-60 Billion by 2030 Amid AI, DRAM Scaling, and Advanced Semiconductor Growth

At its 2024 Investor Day, ASML projected annual revenue of €44 billion to €60 billion with gross margins of 56% to 60% by 2030, driven by double-digit growth in EUV lithography spending for Logic and DRAM, AI-driven semiconductor demand, and scalable EUV technology enabling cost-effective solutions for advanced nodes.

(Full video available here: Investor Day 2024)

DRAM scaling is undergoing a transformation fueled by the adoption of EUV lithography and the architectural shift to 3D DRAM, spearheaded by industry leaders Samsung, SK Hynix, and Micron. EUV lithography extends traditional DRAM scaling, enabling smaller cell sizes and higher densities. Micron plans to integrate EUV into DRAM production by 2025, marking a significant step toward cost-effective scaling. Samsung and SK Hynix are pioneering 3D DRAM architectures, which stack memory cells vertically to enhance density, performance, and energy efficiency. Samsung aims to commercialize 3D DRAM by 2030, while SK Hynix is targeting 2027-2028 for the introduction of vertical channel transistors (VCTs) with compact 4F² cell designs. These advancements represent a leap forward, with EUV lithography ensuring 2D scaling and 3D DRAM addressing physical and economic scaling limitations, paving the way for higher capacities and improved performance.

The progress and benefits of High-NA EUV lithography, with over 10,000 wafers exposed, including 1,300 DRAM and foundry customer wafers, and a target of 2,000 wafers by the end of 2024. Leading semiconductor companies like Micron, Intel, Samsung, SK Hynix, TSMC, and IBM are leveraging High-NA systems to enhance precision and scaling. Mark Philips from Intel highlights the readiness of High-NA EUV with robust tool availability and ecosystem support, enabling advancements like RibbonFETs, PowerVia, and "6x12" masks, which offer 23-50% productivity improvements over previous platforms. These developments underscore the role of High-NA EUV in enabling cost-effective scaling for DRAM and logic manufacturing.

ASML is pivotal in advancing EUV lithography for DRAM manufacturing. By 2024, memory manufacturers such as Samsung and SK Hynix had begun integrating EUV into production to enhance patterning precision and enable further scaling. ASML’s High-NA EUV systems, like the TWINSCAN EXE:5000, are expected to be production-ready by 2025, meeting stringent requirements for higher density and performance in memory technologies. Collaborations like the High-NA EUV Lithography Lab with imec have successfully demonstrated patterning for DRAM and logic structures, showcasing readiness for high-volume manufacturing by 2025-2026.

EUV lithography spending for DRAM is projected to grow at a CAGR of 15-25% through 2030. This growth is driven by the adoption of EUV for enhancing patterning precision and enabling further scaling in DRAM manufacturing. Key advancements include the integration of High-NA EUV systems, like ASML’s TWINSCAN EXE:5000, which is expected to be production-ready by 2025. These technologies support the development of 2D scaling and the transition to 3D DRAM architectures, addressing the physical and economic scaling challenges. Industry leaders Samsung, SK Hynix, and Micron are at the forefront of these efforts, incorporating EUV to achieve smaller cell sizes, higher densities, and improved energy efficiency.

Obviously, advanced logic drives EUV adoption. Spending in this sector is expected to grow at a CAGR of 10-20% through 2030, with High-NA systems playing a critical role in scaling logic nodes. Meanwhile, NAND benefits from advanced lithography solutions addressing the complexity of 3D NAND structures. Though it relies heavily on deposition and etch technologies, advanced DUV and EUV systems provide critical support for these applications.

The global semiconductor market is expected to grow significantly, driven by factors such as AI, high-performance computing, and 5G, which are fueling demand for advanced chips. Semiconductor sales are projected to reach $1 trillion by 2030, supported by the rapid adoption of AI technologies, growing automotive semiconductor needs for electric and autonomous vehicles, and the expansion of 5G networks and connected devices. Additionally, exponential growth in data generation is driving demand for robust data storage solutions, while continuous innovations in manufacturing, such as EUV lithography, enable smaller and more efficient chips. 

The global semiconductor market is expected to grow significantly, driven by AI, high-performance computing, and 5G. Sales are projected to reach $1 trillion by 2030, with wafer demand growing by 780,000 wafer starts per month annually. Strategic considerations, including geopolitical factors, are adding 5-8% extra wafer capacity by 2030. China’s role in the semiconductor industry remains vital, as the country invests heavily in advanced technologies to strengthen its manufacturing capabilities. However, due to export restrictions, China does not have access to ASML's EUV lithography tools. Instead, Chinese manufacturers focus on DUV technology and other innovative approaches to enhance their capabilities in advanced logic and DRAM production. Despite these limitations, China’s expanding wafer capacity contributes significantly to global growth projections, ensuring its relevance in the industry. The region’s efforts to integrate cutting-edge technologies, supported by partnerships with global leaders, highlight its ambitions to remain competitive and innovative in the semiconductor market.

ASML’s holistic lithography approach integrates computational models, metrology, and scanner optimization to maximize accuracy and yield. Innovations target reducing Edge Placement Errors (EPE) and enhancing defect inspections for 2D and 3D structures. The holistic lithography market is expected to grow at a CAGR exceeding 15% through 2030. Holistic lithography also plays a critical role in supporting front-end 3D integration by ensuring overlay control throughout pre-bonding, bonding, and post-bonding processes. Pre-bonding achieves <5 nm overlay error using scanner and offline metrology for correction and control, while bonding addresses large wafer deformation with extensive metrology (50-100 nm overlay error with over 5000 measurements per wafer). Post-bonding refines overlay error to <5 nm with over 2000 measurements per wafer, leveraging scanner actuators and lithography adjustments to bring errors within specifications.

ASML’s holistic lithography approach integrates computational models, metrology, and scanner optimization to maximize accuracy and yield. Innovations target reducing Edge Placement Errors (EPE) and enhancing defect inspections for 2D and 3D structures. The holistic lithography market is expected to grow at a CAGR exceeding 15% through 2030.

In conclusion, ASML’s strategy leverages its installed base, drives EUV and DUV advancements, and capitalizes on AI-driven demand. With projected annual revenue of €44-60 billion by 2030 and gross margins between 56% and 60%, ASML remains at the forefront of semiconductor innovation, enabling transformative progress in DRAM, logic, and NAND technologies.

Sources:

Investor Day 2024

Tokyo Electron Introduces Acrevia Tool to Enhance EUV Lithography

Tokyo Electron has introduced Acrevia, a state-of-the-art gas cluster beam (GCB) system aimed at refining patterns created by EUV lithography. This advanced tool is set to reduce the necessity for EUV double patterning, thereby improving chipmaking yields and lowering production costs. Acrevia addresses critical challenges such as line edge roughness (LER), a common issue in lithography that affects the precision of pattern edges and overall chip performance. By optimizing pattern sidewalls through precise etching, Acrevia promises to significantly enhance within-wafer uniformity and mitigate LER, contributing to higher yield and better chip reliability. While not replacing High-NA EUV lithography, Acrevia marks a substantial leap forward in semiconductor manufacturing innovation.

Sources:

Tokyo Electron's new tool can reduce the necessity for EUV double patterning and improve yield | Tom's Hardware (tomshardware.com)

Tokyo Electron Launches Acrevia™, a Gas Cluster Beam System for Ultra-Fine Patterning in EUV Lithography | News Room | Tokyo Electron Ltd. (tel.com)

ASML Unveils Hyper-NA EUV: Pioneering New Frontiers in Chip Innovation and Efficiency

ASML, the leader in lithography technology for semiconductor manufacturing, has launched its latest breakthrough: the Hyper-NA EUV tool and Intel being the first customer getting its first machine earlier this year. This leading-edge technology, which boosts the numerical aperture (NA) from 0.55 to 0.75, is poised to revolutionize chip design by enabling unprecedented levels of transistor density. Scheduled for introduction around 2030, Hyper-NA promises to extend the capabilities of chipmakers far beyond current limits, opening up new possibilities for intricate and powerful chip designs.

The presentation announcing ASML's Hyper-NA EUV technology was delivered by the company's former president, Martin van den Brink, at imec's ITF World event in Antwerp. 

Reduction in Double Patterning Complexity: Hyper-NA EUV technology simplifies the lithography process by reducing the need for double patterning, i.e., like Litho-Etch-Litho-Etch (LELE) etc., a method that involves aligning two masks perfectly to create intricate chip designs. By providing higher resolution and precision, Hyper-NA EUV minimizes the challenges and costs associated with double patterning, streamlining production and enhancing overall efficiency for chipmakers. However, there are a myriad of multi-patterning technologies deployed out there and SMIC, the main Chinese foundry, is reportedly using sextuple-patterning for its 5 nm technology.

Hyper-NA EUV technology is designed to significantly increase the productivity of semiconductor manufacturing, enabling the processing of 400 to 500 wafers per hour. This improvement will help chipmakers meet the growing demand for high-performance chips more efficiently, reducing production time and costs while maintaining high precision and quality.

The adoption of Hyper-NA EUV presents a myriad of opportunities for the semiconductor industry. As Intel has already installed the first High-NA systems, showcasing the potential of these advanced tools to enhance processor performance. As other industry leaders like TSMC, Samsung, Micron, and SK Hynix explore the adoption of High-NA and eventually Hyper-NA, the competitive landscape is set for a dynamic transformation. Innovations such as advanced polarizers to overcome light polarization issues and improvements in resist materials and etch selectivity will enable more precise and efficient chip manufacturing.

ASML’s Hyper-NA EUV technology is not just a short-term solution but part of a long-term roadmap that will sustain chip innovation for the next decade and beyond. Collaborative research and development efforts, including Imec’s simulations and Zeiss’s lens designs, highlight the cooperative spirit driving this technological advancement. As chip designers like Nvidia, Apple, and AMD leverage these tools at leading foundries such as TSMC, the future of chip design looks brighter than ever, promising enhanced productivity, technological leadership, and sustained growth. Hyper-NA EUV is set to redefine what is possible in the world of semiconductors, driving the industry towards new heights of efficiency and performance.

Sources: ASML Aims for Hyper-NA EUV, Shrinking Chip Limits - EE Times

Intel's Strategic Leap with 14A Node and DSA: Pioneering Next-Gen Semiconductor Manufacturing

Semi Analysis recently published a deeper dive into of Directed Self Assembly (DSA) and prospects of Intel using it at their 14A node (Link below). Intel's latest efforts in semiconductor manufacturing have brought considerable attention to its 18A node, yet it's the 14A node that is most important according to the analysis for the success of Intel Foundry's IDM 2.0 strategy. While the industry watches the ongoing discussions around the merits of TSMC's N2 and Intel’s 18A technologies, Intel is quietly setting a foundational stage with its 14A node, aiming to solidify customer trust and secure critical, high-value chip projects for the future. A key element in Intel's strategy may be the adoption of DSA that could significantly reduce lithography costs. DSA utilizes the self-organizing properties of block copolymers (BCPs) that assemble into predetermined patterns when guided by an underlying template. This approach promises to lower the doses required in extreme ultraviolet (EUV) lithography, allowing for more efficient patterning at reduced costs.

However, integrating DSA into commercial manufacturing involves challenges such as defectivity and pattern limitations, which could hinder its adoption. So I looked more into historical patent filings and found that reveal a typical hype cycle with increased filings during periods of peak expectations, followed by a decline as practical challenges emerged. Intel and TSMC have been consistently filing DSA patents, indicating sustained investment and belief in DSA's potential. Merck, among other chemical suppliers, has significantly increased patent filings, aligning with technological advancements in DSA. Please find on overview below.

It is well known that Intel plans to be the first major company to implement ASML’s high-NA EUV lithography scanners in high volume, despite the higher costs associated with single exposure high-NA systems compared to low-NA double patterning. It was also recently reported on X and other places that ASML is delivering a High-NA System to another player. SemiAnalysis argues that, the economic challenge posed by high-NA technology is addressed through the integration of DSA, which can improve the final pattern quality and dramatically reduce the necessary dose, thus potentially making high-NA economically more viable.

The benefits of DSA are significant: 

• The ability to produce finer features with lower line edge roughness and increased throughput, thanks to its ability to heal discrepancies in the EUV guide patterns. 
• Substantial cost savings and improved yield, especially for layers critical to the performance of advanced logic chips (bigger dies like AI accelerators).

However, DSA's integration into a commercial manufacturing environment is not without risks. The risks associated with Intel's adoption of DSA include:

• The primary risk with any new patterning technology is defectivity, for DSA it is linked to the chemical purity of the block copolymers (BCP). Synthesizing BCP to extremely high purities is challenging, and any inhomogeneity directly impacts the critical dimension (CD), leading to defects. Trace metals need to be below 10 parts-per-trillion, and filtering out organic impurities is difficult, impacting the viability of DSA for mass production. My assessment - Expect this to come from a MERCK or a Japanese chemical vendor.
• DSA is inherently limited to producing 1D line/space patterns or contact hole arrays, restricted to a single pitch per layer. This complicates the integration with other process technologies that might require more diverse patterning capabilities. However, these issues have potential solutions similar to those used in multi-patterning schemes.
• Despite the theoretical benefits and recent advances in DSA, it remains largely untested in high-volume, leading-edge manufacturing. Intel is pioneering the use in high-NA scenarios, but the broader adoption across the industry, including by competitors like TSMC who are also developing DSA, remains uncertain. 

Source: Intel’s 14A Magic Bullet: Directed Self-Assembly (DSA) (semianalysis.com)

So let´s do the Patbase Test - how does this hold out if we dig into historical and current patent filing by the suspects!

Yes indeed, we have seen much increased filing the past decade or so representing a typical hype cycle. The hype cycle is a model developed by Gartner that describes the progression of a technology from inception to widespread adoption and maturity. It typically consists of five phases: the Technology Trigger, Peak of Inflated Expectations, Trough of Disillusionment, Slope of Enlightenment, and Plateau of Productivity. So for DSA in semiconductor manufacturing, the technology first garnered attention when its potential applications in advanced lithography were identified (2000-2010), marking the Technology Trigger. Interest surged about 2011, leading to a Peak of Inflated Expectations around 2016/2017, evidenced by a spike in patent filings as companies raced to capitalize on the emerging technology. However, as practical and economic challenges such as defectivity and integration complexities became evident, the enthusiasm waned, and DSA entered the Trough of Disillusionment. During this phase, the technology's limitations led to a decline in interest as initial expectations were not met. Over time, as more sustainable applications and improvements are developed, DSA may progress into the Slope of Enlightenment, where understanding and optimization occur as described in the assessment by SemiAnalysis, before finally reaching the Plateau of Productivity in the years to come, where it becomes a standard part of semiconductor manufacturing processes. This progression through the hype cycle reflects the typical maturation path of innovative technologies in the industry. Please note that there is a delay in patent filing data of up to 18 months so 2022, 2023 and 2024 are not complete yet.

Patent filing since 2000 in DSA (Patbase, 2024-04-19)

2. Yes, Intel is actively filing DSA patents and in the lead, and so is TSMC, along with other key players in the ecosystem. Over the past decade, the pattern of DSA patent filings has been quite revealing. Initially, GlobalFoundries and IBM in Upstate New York were early filers. GlobalFoundries ceased their filings around the time they decided not to pursue 7 nm and nodes below. IBM also stopped filing after completing their 2 nm demonstration on 300 mm wafers in 2021. Main contenders Intel and TSMC have been consistently filing DSA patents throughout the hype cycle and have continued to do so. Notably, there has been a clear acceleration in Intel's patent filings since 2019, although there was a slight drop during the COVID-19 lockdowns. Looking at chemical suppliers, Merck has taken the lead, with increased filings beginning in parallel with Intel from 2019 onwards, and accelerating until today. Other suppliers such as JSR, Shin-Etsu, and Brewer Science are also active in the DSA space. In the segment of wafer equipment OEMs, Tokyo Electron and SCREEN have been dominant. However, SCREEN appears to have recently exited the game.

DSA Patent filing last decade (Patbase , 2024-04-19)

In Summary - good assessment by SemiAnalysis and i passes the Patbase Test!

SK hynix to Lead in Advanced DRAM Production, Overtaking Samsung with Earlier Start

Korean SK hynix is set to initiate mass production of its advanced 6th generation 10nm class DRAM (node 1c) in the third quarter of this year, ahead of its competitor Samsung Electronics. The move positions SK hynix to potentially lead in the DDR5 server memory market, which is needed for data centers operated by major tech companies. SK hynix has outlined a strategic internal roadmap that includes achieving necessary customer certifications in anticipation of a surge in demand, especially following compatibility approval with Intel's server platforms. This certification is crucial as Intel holds a dominant share in the global server CPU market. 

The DDR5 DRAM from SK hynix is designed to be compatible with Intel CPUs, a significant advantage given Intel’s extensive market presence. Meanwhile, Samsung plans to start its mass production of similar DRAM by the end of the year, having shared its development roadmap at the recent MemCon 2024 conference. Both companies are using leading-edge Extreme Ultraviolet (EUV) lithography in their processes, which enhances chip yield and power efficiency over previous generations.

SK hynix's new M16 DRAM plant in Icheon, Gyeonggi Province / Courtesy of SK hynix

Source: SK hynix Leads with ‘6th Generation 10 nm’ DRAM Production Ahead of Samsung - Businesskorea

Applied Materials Pioneer® CVD film for EUV Sculpta and DRAM Sym3 Etch applications

Applied Materials continues to lead in semiconductor technology with its introduction of the Producer® XP Pioneer® CVD patterning film at the SPIE Advanced Lithography + Patterning conference. This latest innovation is critical for DRAM scaling and EUV lithography, offering improved etch selectivity and pattern fidelity due to enhanced film density and stiffness. Optimized for use with the Sculpta® pattern-shaping system, Pioneer allows for advanced patterning capabilities, crucial for maintaining precise feature dimensions. With its adoption by leading foundry-logic and memory manufacturers, the Pioneer system is set to significantly enhance Applied Materials' portfolio and revenue, affirming its leadership in CVD technologies.

Applied Materials' Draco™ hard mask and Sym3® Y HT etch system have revolutionized DRAM production by enabling the etching of perfectly cylindrical capacitor holes, significantly enhancing etch selectivity and improving critical dimension uniformity, which contributes to a notable increase in the company's market share in DRAM.

Demand for DRAM innovation continues to grow to feed the insatiable need for memory bandwidth in the AI era. The recently launched Pioneer CVD patterning film has already been adopted by leading memory manufacturers for DRAM patterning. Pioneer is a completely new CVD architecture based on a unique high-density carbon formula that is more resilient to etch chemistries used in the most advanced process nodes, permitting thinner film stacks with superior sidewall feature uniformity.

A thinner hard mask means less vertical distance is required for etch, resulting in a lower aspect ratio. This allows use of lower-power plasma and offers better control of the ratio of ions to radicals. A higher concentration of ions produces more efficient etches with better control, allowing desired patterns to be transferred to the wafer with exceptional fidelity. Pioneer is also being co-optimized with Applied’s new Sym3® Y Magnum® etch system to provide better control over conventional carbon films for critical etch applications in memory processing.

For EUV Lithography the Pioneer CVD patterning film developed by Applied Materials addresses the stringent demands of EUV lithography by increasing film density and stiffness, which enhances etch selectivity and allows for finer pattern control, vital for the ultra-fine dimensions required in advanced chip manufacturing.

Source: Building on an Unmatched Foundation of CVD Innovation (appliedmaterials.com)

Intel Receives ASML's First High-NA EUV Lithography Scanner, Pioneering Next-Gen Semiconductor Manufacturing

ASML has delivered its groundbreaking High-NA EUV lithography scanner, the Twinscan EXE:5000, to Intel Oregon. Marking a significant technological leap, this first-of-its-kind scanner boasts a 0.55 NA lens, enabling 8nm resolution for advanced semiconductor manufacturing. Designed for process technologies beyond 3nm, it promises to enhance chip production efficiency and reduce costs. Intel's early adoption of this state-of-the-art equipment, valued between $300-$400 million, positions them at the forefront of the industry, potentially setting new standards in High-NA manufacturing. This development represents a major milestone in semiconductor technology, signaling a new era of innovation and capability in chip production.

ASML's New Chapter: Navigating Tech Innovation and Geopolitical Shifts Under Christophe Fouquet's Leadership

In an era of significant technological and geopolitical changes, ASML, the number one player in the semiconductor industry, stands at a crossroads. The forthcoming retirement of Martin van den Brink and Peter Wennink, who have jointly steered ASML for over a decade, signals the end of a dynamic period. Van den Brink's leadership in technology development propelled ASML to unparalleled heights in the lithography sector, while Wennink’s diplomatic and financial acumen solidified its market dominance. ASML's impact extends beyond technology; it has become a geopolitical force, enhancing the Netherlands and Europe's strategic significance in global politics.

The appointment of Christophe Fouquet as the incoming CEO heralds a new era. Fouquet faces the challenge of maintaining ASML's technological edge while adapting to a market nearing the limits of Moore's Law. 

As ASML approaches its 40th anniversary in April 2024, it confronts a changing landscape. The company has weathered various phases – from early struggles to market leadership, marked by innovations like the PAS 5500 and immersion lithography. Under Van den Brink, ASML prioritized technological advancement, often at the expense of other factors like reliability.

The appointment of Christophe Fouquet as the incoming CEO heralds a new era. Fouquet faces the challenge of maintaining ASML's technological edge while adapting to a market nearing the limits of Moore's Law. The shift in focus from chip performance to system-level advancements requires a nuanced approach. Additionally, as technology matures, reliability and predictability become crucial for maintaining ASML's competitive edge.

The transition from a "firefighter" engineering culture to one emphasizing process and reliability won't be easy. Fouquet must balance innovation with operational efficiency, ensuring ASML remains responsive to market and geopolitical dynamics. This requires a departure from the legacy of Van den Brink, focusing instead on a holistic, structured approach to development and engineering.

Fouquet's tenure will be pivotal in shaping ASML's future. His leadership must navigate the complexities of a highly competitive industry, geopolitical pressures, and the evolving technological landscape. The challenge lies in fostering a culture that values reliability and process without stifling the innovative spirit that has been ASML's hallmark. As the company moves into its fifth decade, its ability to adapt and evolve under Fouquet's guidance will determine its continued success in a rapidly changing world.

Advancing the Microchip Revolution: EUV Lithography's Challenges and Future Outlook

Extreme Ultraviolet (EUV) lithography represents a significant advancement in semiconductor manufacturing, enabling the production of more compact and efficient integrated circuits, particularly for 7 nm Logic process nodes and below and leading edge DRAM. This technology, developed and marketed primarily by ASML Holding, uses a highly specialized process involving laser-pulsed tin droplet plasma to etch patterns onto substrates at the 13.5 nm wavelength scale. The progression from early prototypes to more efficient models has been remarkable, with modern EUV systems capable of handling 200 wafers per hour, a substantial improvement from initial prototypes.

Looking into the future, EUV lithography is expected to play a critical role in advancing semiconductor technology, especially as the demand for smaller and more powerful chips increases. However, several technological challenges need addressing continiously to fully harness EUV's potential:

1. Optical Component Durability: The EUV process requires highly specialized and sensitive optical components, including mirrors and photomasks. These components are prone to degradation from exposure to high-energy photons and contaminants. Improving their durability and developing efficient cleaning and maintenance processes are crucial.

2. Throughput Efficiency: While significant improvements have been made, further enhancing the throughput of EUV systems is vital. This includes reducing setup times, increasing the speed of the lithography process, and minimizing downtime due to maintenance or component replacement.

3. Pattern Fidelity and Defect Reduction: As circuit patterns become increasingly smaller, maintaining pattern fidelity and reducing defects is challenging. This involves improving the resolution of EUV systems, enhancing photoresist materials to better respond to EUV exposure, and developing more effective methods to mitigate the impact of secondary electrons generated during the lithography process.

EUV Lithography - Balancing Technological Advancements with Energy Challenges

EUV lithography, pivotal in advanced semiconductor manufacturing, faces significant energy consumption challenges. The generation of EUV light, typically via laser-pulsed tin plasma, is inherently energy-intensive. Additionally, maintaining the necessary vacuum environment and cooling systems for these high-precision machines further escalates energy use. As EUV technology becomes more prevalent, especially for producing smaller, more efficient chips, optimizing energy efficiency is critical. Future developments are expected to focus on more efficient light sources, improved system design for energy conservation, and advanced thermal management, aiming to reduce the overall energy footprint of EUV lithography processes.

The semiconductor industry, traditionally known for its high environmental impact, is increasingly embracing sustainability. With the global demand for semiconductors rising, manufacturers face the challenge of scaling up production while addressing substantial water and electricity usage and managing hazardous waste from gases used in manufacturing. Historically, the focus has been on balancing power, performance, and cost. Recently, however, sustainability has emerged as a crucial consideration, with many facilities actively working to decarbonize their supply chains and reduce overall environmental impact (data from imec)

EUV Lithography's Hydrogen Demand: A Growing Concern in Chip Manufacturing

EUV Lithography, also raises concerns regarding its significant hydrogen consumption. The EUV process relies heavily on hydrogen gas to maintain the cleanliness of the optical elements, particularly for preventing tin deposition on the mirrors. The need for a continuous supply of hydrogen to facilitate this cleaning process contributes to the overall operational costs and resource demands of EUV systems. As EUV technology becomes more widespread in chip manufacturing, addressing the sustainability and efficiency of hydrogen usage will be essential, both from an environmental and economic perspective.

In EUV lithography, managing hydrogen usage presents distinct challenges. The technology requires hydrogen for removing contaminants from critical mirrors, demanding systems capable of handling high volumes while maintaining vacuum integrity. This necessity places a premium on innovative system designs that minimize the footprint and energy consumption associated with hydrogen management, directly impacting the cost and efficiency of semiconductor manufacturing. Safety considerations, given hydrogen's flammability, are paramount. Advanced, fuel-free hydrogen management strategies are employed to ensure safety and environmental compliance. These strategies focus on reducing flammability risks and eliminating the need for additional fuels, thereby minimizing carbon emissions and contributing to sustainable manufacturing practices.

Continued research and development in these areas are essential for the advancement of EUV lithography, ensuring it meets the rapidly evolving demands of the semiconductor industry.

Sources: 

Christophe Fouquet’s ASML must reinvent itself – Bits&Chips (bits-chips.nl)

www.imec.be

www.edwards.com

Wikipedia

2023 update to IRDS roadmap reminds key EUV issues.

1. EUV dose triples every four nodes => increasing electron blur?
2. EUV cannot replace multiple patterning, even with higher NA.https://t.co/hZzkfKGfyr

— Fred Chen (@DrFrederickChen) December 28, 2023