Wednesday, June 20, 2018

Plasma ALD and ALE Tutorial at PSE 2018, 16th of September in Garmisch-Partenkirchen

Plasma ALD and ALE Tutorial will be given at the 16th International Conference on Plasma Surface Engineering, September 17 - 21, 2018, in Garmisch-Partenkirchen, Germany.

 
Sunday, September 16, 2018
The focus will be on atomic level processing technologies, such as Plasma Enhanced Atomic Layer Deposition (PEALD) and Atomic Layer Etching (ALE). The tutorial will provide the basics of the processes, but also  insights into the fundamentals of processes, as well as an overview of the processing equipment and applications of these leading edge technologies.

The tutorial will be organized by Adriana Creatore, TU Eindhoven, the Netherlands, in cooperation with Jonas Sundqvist, Fraunhofer IKTS, Dresden, Germany.

Program [PDF]
9:00 - 9:30

Introduction
Adriana Creatore, Eindhoven University of Technology, the Netherlands
Jonas Sundqvist, Fraunhofer Institute for Ceramic Technologies and Systems IKTS, Germany
9:30 - 11:00

“Overview of thin film deposition and nanofabrication by atomic layer deposition”
Adrie Mackus, Department of Applied Physics, Eindhoven University of Technology, the Netherlands
11:00 - 11:30 Break
11:30 - 13:00

“Plasma atomic layer deposition: basics, mechanisms and applications”
Harm Knoops, Oxford Instruments Plasma Technology, United Kingdom and Department of Applied Physics, Eindhoven University of Technology, the Netherlands
13:00 - 14:00 Lunch
14:00 - 15:30

“Principles, basics and practical examples of Plasma Atomic Layer Etching”
Sabbir Khan, Department of Physics, Lund University, Sweden
15:30 - 16:00 Break
16:00 - 17:30

“Plasma-ALD and ALE processes in high volume manufacturing and emerging applications”
Jonas Sundqvist, Fraunhofer Institute for Ceramic Technologies and Systems IKTS, Germany
17:30 End of the tutorial



Sunday, June 17, 2018

HERALD SUMMIT 2018 25-28 September Barga Portugal - Open for registrations

Registration to HERALD SUMMIT 2018 is open. The HERALD Summit will be the premier European conference in 2018 devoted solely to atomic level processing, covering atomic layer deposition (ALD), atomic layer etch and related nano fabrication techniques.  As the final meeting of the HERALD COST Action, the three-day Summit will include detailed discussions on the research achievements of HERALD and on future opportunities for collaboration, both within Europe and worldwide.  Ongoing projects and new funding proposals will be promoted so as to continue to build the ALD community.  The HERALD Summit will take place in Braga, Portugal from 25-28 September 2018.
Those receiving a travel grant from HERALD for this conference may claim reimbursement of the meals fee, but not of the registration fee (early bird registration fee € 120).
There is a list of hotels with special prices for the event. Information at https://www.european-ald.net/events/herald-summit-2018.

Venue - International Iberian Nanotechnology Laboratory (INL) 

http://inl.int/
The International Iberian Nanotechnology Laboratory (INL) is the result of a joint decision of the Governments of Portugal and Spain, whereby the two Governments made clear their commitment to a strong cooperation in ambitious science and technology joint ventures for the future. INL has 47 000 m2 campus area, about 26 000 m2, providing 22 000 m2 of laboratory space and state-of-art equipment for various research areas. A guided visit to the INL is included in the Program.

Friday, June 15, 2018

Cobalt and Ruthnium confirmed in Intel 10nm Cannon Lake BEOL

TechInsights has found the long-awaited Cannon Lake - the Intel 10 nm logic process inside the i3-8121U CPU, used in the Lenovo IdeaPad330.
 
This innovation boasts the following:

  • Logic transistor density of 100.8 mega transistors per mm2, increasing 10nm density 2.7X over the 14nm node
  • Utilizes third generation FinFET technology
  • Minimum gate pitch of Intel’s 10 nm process shrinks from 70 nm to 54 nm
  • Minimum metal pitch shrinks from 52 nm to 36 nm
Process Highlights:

  • Deepest scaled pitches of current 10 nm and upcoming 7 nm technologies
  • First Co metallization and Ru usage in BEOL
  • New self-aligned patterning schemes at contact and BEOL
Source: TechInsight (LINK)

By reading this it is not possible to determine exactly how Ruthenium is used or how it has been deposited and there are several options like barrier and seed layer for plating Copper or Cobalt. What is known is that Intel presented already at IEDM2017 the use of cobalt in their 10 nm MOL/BEOL process flow as contacts and M0/M1 lines as well as barrier/seed for copper and copper cap for complete encapsulation of copper up to M5.


Intel 10nm mid end of line cobalt and copper metallization as presented at IEDM 2017.

Wednesday, June 13, 2018

Advanced Materials Special Issue dedicated to current research activities on Materials Science in Finland

This Special Issue is dedicated to current research activities on Materials Science in Finland (LINK), providing a collection of outstanding contributions from diverse research groups on the recent progress regarding silicon and silica nanomaterials, DNA nanotechnology, micro/nano‐motors, biomass‐based nanostructures, nanocellulose, 2D layered materials, atomic layer deposition, superhydrophobic surfaces, and microrobots, from the University of Helsinki, Aalto University, VTT, the University of Turku, Åbo Akademi University, Tampere University of Technology, and the University of Eastern Finland


 Including off course an ALD contribution from Helsinki University!

Atomic Layer Deposition of Rhenium Disulfide


Jani Hämäläinen, Miika Mattinen, Kenichiro Mizohata, Kristoffer Meinander, Marko Vehkamäki, Jyrki Räisänen, Mikko Ritala, Markku Leskelä

First Published: 05 January 2018
 Growth of rhenium disulfide by atomic layer deposition is studied. ReS2 is a 2D material that is not limited to the monolayer thickness because of effective decoupling of the monolayers in bulk. The ReS2 films are deposited from ReCl5 and H2S at up to 500 °C, also on a 3D structure, and the films are characterized.

Tuesday, June 12, 2018

Australian researcher Martin Green awarded Global Energy Prize for PERC solar cells

[PV Magazine] UNSW’s Martin Green pioneering work in developing crystalline silicon solar has now gained global recognition in the energy sector – after being awarded Russia’s Global Energy Prize.

Green, the Director of the UNSW’s Australian Centre for Advanced Photovoltaics was awarded the Russian Global Energy Prize last week. He was selected by a committee of peers ahead of 44 contenders from 14 countries.
 
 
Green has long been credited as being the creator of the Passivated Emitter Rear Contact (PERC) solar cell, which continues to be adopted as a mainstream technology by manufacturers in 2018. Additionally, he has also spearheaded work into perovskites, selective emitter technology, and is now leading research into whole new areas of semiconductor material, for silicon-tandem cells that could potentially push efficiencies up to 30% and beyond.

Martin Green and fellow UNSW scientists were prominent at the recent SNEC trade show and conference in China, both progressing their work with industry partners on the advanced hydrogenation process, but also in collaborations ranging across PV cell production including Atomic Layer Deposition processes for PERC cell production.

Report from the 3rd Area Selective Deposition Workshop (ASD 2018) at North Carolina State University

In late April (April 29 – May 1, 2018) the 3rd Area Selective Deposition Workshop (ASD 2018), was held at North Carolina State University in Raleigh North Carolina USA (LINK). This years workshop was organized with full support from AVS and as for ALD and ALE Della Miller was in charge.

The Workshop brought together leading international scientists and engineers from academia and industry from all regions to share results and insights into: 1) fundamental principles and barriers to area selective deposition; 2) technological needs and challenges of ASD; 3) new chemical approaches and processes to address the expanding needs; and 4) surface characterization techniques and metrology innovation for ASD.

This third year the program was expanded to two days, including 11 invited presentations, an invited panel discussion, 18 contributed talks, and 15 posters and in between there was plenty of time for interaction over meals and social events.

ASD2018 brought together leading experts from 10 countries in Asia, Europe and America, to deliver and discuss more than 45 presentations. As the chart shows, this constitutes significant growth since the first ASD Workshop in 2016 (ASD2018 Book of Abstracts).

As a particular focus this year, the committee had chosen to highlight the challenge of selective deposition metrology, including an invited panel to discuss particular issues and techniques related to selectivity measurement and selective defect quantification.

It is clear that ASD is a fast growing field and may at some point in time reach the status as a stand alone segment with respect to processing, chemicals and equipment. Another indication can be seen that at the SPIE in February there was a high number of presentations and posters on combining ALD and ALE or just Area Selective Deposition.

Program Char Prof. Gregory N. Parsons of North Carolina State University, USA has asked to share some photos form the successful event (below). In addition, an article covering the event was just published by Chemical & Engineering News (LINK) including interviews and the latest insights from Dennis M. Hausmann (Lam Research), Gregory N. Parsons, Silvia Armini (invited speaker, imec), Dara Bobb-Semple and Stacey F. Bent (Stanford University), and Steven M. George (Colorado Boulder University).

Studying the Book of Abstract, my personal favorite is the atmospheric pressure micro-plasma printer for area-selective ALD presented by Prof. Kessels (TU Eindhoven). This technology is being commercialized by the Dutch company with InnoPhysics (LINK) and you can expect to hear more details about this exciting technology soon.

Rear view from the The StateView Hotel conference room (Photo: Gregory N. Parsons).
Junling Lu from University of Science and Technology of China, Hefei presenting "Bottom-up Engineering Catalyst Nanostructures using Area-Selective Atomic Layer Deposition" (Photo: Gregory N. Parsons).

Wednesday, June 6, 2018

Achieving ultrahigh etching selectivity of SiO2 over Si3N4 and Si in atomic layer etching

JVST A Featured Article: Achieving ultrahigh etching selectivity of SiO2 over Si3N4 and Si in atomic layer etching by exploiting chemistry of complex hydrofluorocarbon precursors by Kang-Yi Lin, Chen Li. Sebastian Engelmann, Eric A. Joseph, Dominik Metzler and Gottlieb Oehrlein a collaboration between University of Maryland and IBM 
 
 

 
 

Imec Extends Damascene Metallization Towards the 3nm Technology Node

LEUVEN, June 4, 2018 – At this week’s 2018 IEEE International Interconnect Technology Conference (IITC 2018), imec, the world-leading research and innovation hub in nanoelectronics and digital technology, will present 11 papers on advanced interconnects, ranging from extending Cu and Co damascene metallization, all the way to evaluating new alternatives such as Ru and graphene. After careful evaluation of the resistance and reliability behavior, imec takes first steps towards extending conventional metallization into to the 3nm technology node.

For almost two decades, Cu-based dual damascene has been the workhorse industrial process flow for building reliable interconnects. But when downscaling logic device technology towards the 5nm and 3nm technology nodes, meeting resistance and reliability requirements for the tightly pitched Cu lines has become increasingly challenging. The industry is however in favor of extending the current damascene technology as long as possible, and therefore, different solutions have emerged. 
Via resistance for Co, Cu, Ru (left); and comparison of damascene line resistance versus total conductor cross-sections area of Ru, Co and Cu nanowires (right)
To set the limits of scaling, imec has benchmarked the resistance of Cu with respect to Co and Ru in a damascene vehicle with scaled dimensions, demonstrating that Cu still outperforms Co for wire cross sections down to 300nm2 (or linewidths of 12nm), which corresponds to the 3nm technology node. To meet reliability requirements, one option is to use Cu in combination with thin diffusion barriers such as tantalum nitride (TaN)) and liners such as Co or Ru. It was found that the TaN diffusion barrier can be scaled to below 2nm while maintaining excellent Cu diffusion barrier properties.

For Cu linewidths down to 15–12nm, imec also modeled the impact of the interconnect line-edge roughness on the system-level performance. Line-edge roughness is caused by the lithographic and patterning steps of interconnect wires, resulting in small variations in wire width and spacing. At small pitches, these can affect the Cu interconnect resistance and variability. Although there is a significant impact of line-edge roughness on the resistance distribution for short Cu wires, the effect largely averages out at the system level.

An alternative solution to extend the traditional damascene flow is replacing Cu by Co. Today Co requires a diffusion barrier – an option that recently gained industrial acceptance. A next possible step is to enable barrierless Co or at least sub-nm barrier thickness with careful interface engineering. Co has the clear advantage of having a lower resistance for smaller wire cross-secions and smaller vias. Based on electromigration and thermal storage experiments, imec presents a detailed study of the mechanisms that impact Co via reliability, showing the abscence of voids in barrierless Co vias, demonstrating a better scalability of Co towards smaller nodes. The research is performed in cooperation with imec’s key nano interconnect program partners including GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, SanDisk/Western Digital, Sony Semiconductor Solutions, TOSHIBA Memory and TSMC.

Applied Materials enables cobalt contact & interconnect for 7nm with pre-clean, PVD, ALD and CVD – on the Endura® platform

At IEDM 2017 in December both Intel and Globalfoundries presented cobalt encapsulation (liner and cap) for copper local interconnects as well as Co fill contacts for their 10nm resp 7nm technologies. Since then many have wondered about the unit process details behind the new cobalt integration and here we have it - The Applied Materials  complete cobalt solution as announced yesterday. Especially interesting that TiN ALD also is used as a cobalt seed/adhesio/dufusion barrier for cobalt contacts. The most interesting stuff you will finde here: LINK
[SANTA CLARA, Calif., June 05, 2018]  Applied Materials, Inc. today announced a breakthrough in materials engineering that accelerates chip performance in the big data and AI era.

In the past, classic Moore’s Law scaling of a small number of easy-to-integrate materials simultaneously improved chip performance, power and area/cost (PPAC). Today, materials such as tungsten and copper are no longer scalable beyond the 10nm foundry node because their electrical performance has reached physical limits for transistor contacts and local interconnects. This has created a major bottleneck in achieving the full performance potential of FinFET transistors. Cobalt removes this bottleneck but also requires a change in process system strategy. As the industry scales structures to extreme dimensions, the materials behave differently and must be systematically engineered at the atomic scale, often under vacuum. 
To enable the use of cobalt as a new conducting material in the transistor contact and interconnect, Applied has combined several materials engineering steps – pre-clean, PVD, ALD and CVD – on the Endura® platform. Moreover, Applied has defined an integrated cobalt suite that includes anneal on the Producer® platform, planarization on the Reflexion® LK Prime CMP platform and e-beam inspection on the PROVision™ platform. Customers can use this proven, Integrated Materials Solution to speed time-to-market and increase chip performance at the 7nm foundry node and beyond. 

“Five years ago, Applied anticipated an inflection in the transistor contact and interconnect, and we began developing an alternative materials solution that could take us beyond the 10nm node,” said Dr. Prabu Raja, senior vice president of Applied’s Semiconductor Products Group. “Applied brought together its experts in chemistry, physics, engineering and data science to explore the broad portfolio of Applied’s technologies and create a breakthrough Integrated Materials Solution for the industry. As we enter the big data and AI era, there will be more of these inflections, and we are excited to be having earlier and deeper collaborations with our customers to accelerate their roadmaps and enable devices we never dreamed possible.”

While challenging to integrate, cobalt brings significant benefits to chips and chip making: lower resistance and variability at small dimensions; improved gapfill at very fine dimensions; and improved reliability. Applied’s integrated cobalt suite is now shipping to foundry/logic customers worldwide.

Applied Materials, Inc. (Nasdaq:AMAT) is the leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. Our expertise in modifying materials at atomic levels and on an industrial scale enables customers to transform possibilities into reality. At Applied Materials, our innovations make possible the technology shaping the future. Learn more at www.appliedmaterials.com.

Friday, June 1, 2018

ShenZhen Association for Vacuum Technology Industries visits ALD lab at Fraunhofer IKTS

Today we at the Thin Film Technology group of Fraunhofer IKTS in Dresden were honored to be the 2nd stop for the delegation from the ShenZhen Association for Vacuum Technology Industries from China on their European Trip. We presented the latest research and industrialization of Atomic Layer Deposition technology and discussed new opportunities for ALD industrial application.

Shenzhen is one of the most dynamic cities in China. It is located in the southern part of Guangdong Province, next to Hong Kong. Shenzhen is famous for its rapid economic development since the establishment of the special economic zone in 1980. Over the past several decades, Shenzhen has been developed from a small fishing village to currently a modern city featured for innovation and high-tech. Many renowned high-tech companies such as Huawei, Tencent, and BYD are located in Shenzhen.

The next China ALD Confernce will be held in Shenzhen, China, from October 14 to 17, 2018 (LINK)