Beneq introduces a PEALD process to deposit silicon nitride on 3D structures with excellent uniformity

To yield superior thin film properties on planar as well as complex 3D structures, Beneq is now launching a highly competitive low-temperature, plasma-enhanced atomic layer deposition (PEALD) process for depositing silicon nitride (Si3N4).

The use of silicon nitride is extensive in many high-tech sectors, including the semiconductor industry, for micro-electromechanical systems (MEMS) and in medical applications. Silicon nitride thin films are ideal when used as chemical barriers and insulators in integrated circuits, or as diffusion barriers for microchips, or as dielectrics in capacitors.

Currently, CVD-based processes are largely used to grow silicon nitride (Si3N4) thin films. Due to the intrinsic mechanisms and properties of CVD processes, coating complex 3D structures with conformal and uniform thin films has been impossible. By introducing a robust and up-scalable Si3N4 process, Beneq is again paving the way for new opportunities in ALD.

The newly launched Beneq process now offers the opportunity to use Si3N4 in 3D structures in the semiconductor industry, for MEMS applications and much more. It features low processing temperatures, starting at 250 °C, for ease of production. The main specifications of the process are:

• high uniformity on 3D structures
• low temperature process – starting from 250 °C
• Si3N4 thin film chemical composition
• very low level of contaminants
• safe to use – non-hazardous precursors
• simple to upgrade – available for Beneq TFS 200 and TFS 500

“We’re really pleased to launch this unique Si3N4 depositing technology,” says Markus Bosund, Senior Scientist at Beneq. “Again, we can reach beyond the limitations of conventional thin film processes and offer a competitive ALD solution. Our PEALD process allows outstanding film properties for 3D structures at low temperatures. For Beneq, this is the next milestone in our history of bringing the world’s best ALD expertise to the market.” 

The process will be formally presented during ALD 2015, the 15th International Conference on Atomic Layer Deposition and main annual event for the global ALD community in research and industry. ALD 2015 will be held June 28th - July 1st, 2015, Portland, Oregon, USA, where Senior Scientist Markus Bosund will be presenting work that Beneq has completed together with Hewlett-Packard Co. and the University of Jyväskylä. The topic of his presentation is: “Saturation Behavior and Film Properties of Plasma-Enhanced ALD Grown Silicon Nitride”. 

Beneq is a pioneer in ALD equipment and applications development, with installed equipment serving university labs, research institutes and corporate R&D worldwide. Beneq is the developer of Roll-to-Roll ALD.

Research and Markets: 2015 ALD/CVD High K and Metal Precursors for the Semiconductor IC Market

Pretty impressive to know that "The semiconductor CVD/ALD industry utilizes precursors for over 29 different metals and metal oxides provided globally by 23 suppliers." Thanks Rob for sharing this one in the ALD LinkedIn Group!

Research and Markets has announced the addition of the "2015 ALD/CVD High K and Metal Precursors for the Semiconductor IC Market" report to their offering.

The High K / ALD Precursors report provides information on the applications and markets associated with front end and back end of line precursors used to produce high dielectric constant (K) dielectrics and atomic layer deposition dielectrics and metals. Market size, growth, and market share statistics are provided.

Rancho Santa Fe, CA, June 15: Use of front-end Ta and W metal gate and Hf gate dielectric precursors will grow over 2.5x by 2020, according to a new report from this research industry, 2015ALD/CVD High K and Metal Precursors for the Semiconductor IC Market. The overall precursor market sits at $185M today, and is expected to grow 18% over the next five years. The advanced metal gate and gate dielectric segments within that market are expected to grow at 168%, more than compensating for the 25% decline anticipated for the high memory precursor segment.

The 2014 market size for CVD/ALD precursors for interconnect applications was approximately $93M, up 19% over 2013. 2015 is forecast to be up another 15%. By 2016, growth in this segment will be dominated by cobalt barrier precursors, as WF for contact and plug applications begins to decline. The 5-year CAGR for this area is forecast to be 9.4% overall.

The precursor market for capacitor CVD/ALD applications, which includes DRAM and a variety of memory devices, is expected to be flat for the next 5 years, fluctuating in the range of $55M to $70M. The difficulties in forecasting conventional memory demand are compounded by the emergence of a host of new memory device structures, not all of which depend on these materials.

The semiconductor CVD/ALD industry utilizes precursors for over 29 different metals and metal oxides provided globally by 23 suppliers. In addition to market analysis, process flow details, precursor candidates and critical supply chain issues, the report includes regional ranking for major suppliers of vapor deposition precursors.

RASIRC to showcase technology leadership in hydrogen peroxide delivery in Portland

OMG it is heating up before the upcoming Atomic Layering weeks in Portland! RASIRC is well prepared. I know by own experience that they have the absolutely best technology there is for delivering hydrogen peroxide. It is sort of embarrassing after having worked and published papers on using a stander bubbler and realizing that I actually did not deliver basically any H2O2 onto the surface back then. Talk to Jeff Spiegelmann at the conferences he will explain it all for you.

RASIRC will showcase technology leadership in hydrogen peroxide gas for next generation semiconductor materials and processes with a poster session and exhibit (booth #39) at the 15th International Conference on Atomic Layer Deposition June 28-July 1 in Portland, Oregon. The company will present a second poster at the Atomic Layer Etching Workshop held immediately following the ALD Conference. The posters are titled “In-Situ Monitoring of Hydrogen Peroxide Vapor Delivery Systems for ALD” and “Novel Hydrogen Peroxide Delivery Systems for Atomic Layer Cleaning and Etch”.

“The ALD Conference and ALE Workshop are great forums for us to discuss our technology around hydrogen peroxide gas, which we believe will be a critical component in enabling next generation ALD and ALE processes,” said Jeffrey Spiegelman, RASIRC President and Founder. “Test results from in-situ monitoring clearly show that H2O2 gas delivery for ALD can be stable with or without water, and that H2O2 gas can remove carbon from ALD pre-initiation layers to eliminate wet cleaning steps.”

In-Situ Monitoring of H2O2 for ALD

H2O2 gas is more reactive with metal precursors than water and less aggressive than ozone. Process engineers can now deliver high concentration H2O2 gas to process with or without water. RASIRC co-developed an analyzer for in-situ monitoring of H2O2 gas to verify the H2O2 gas concentration flowing to process. Test results using the analyzer clearly show stable H2O2 gas concentration over extended periods of time. Tests were performed on both high concentration H2O2 gas delivery systems and anhydrous H2O2 gas delivery systems.

For high concentration systems using 30% H2O2 liquid source, tests showed stable delivery of up to 5% gas by volume. For anhydrous systems, test results showed stable, consistent delivery of virtually water-free H2O2 gas. Test results will be presented at a poster session on June 30 from 5:30pm-7:30pm.

H2O2 Gas for ALE

H2O2 gas for atomic layer etching enables process engineers to eliminate certain cleaning steps in processing next generation semiconductors. Uniform removal of layers is critical to device performance due to layers now being only several atoms thick, and H2O2 gas is ideally suited to this task. RASIRC will present test results showing that high concentration H2O2 gas can be generated and delivered to process at stable concentrations of up to 5% gas by volume. Preliminary test results with new materials and alternative chemistries will also be shown. The poster presentation will be on July 1 from 6:00pm-9:00pm.

ALD Conference Presence

For more information about H2O2 Gas with or without water, ALD Conference attendees are invited to visit RASIRC in booth #39. Representatives will be available to discuss technologies and test results.

Read more: http://www.digitaljournal.com/pr/2596091#ixzz3e7As3hkg

CVD of vertically aligned silicon nanowires in MEMS using silane as a precursor

Here is a very good and detailed paper on CVD of vertically aligned silicon nanowires in MEMS using silane as a precursor by researchers at Catalonia Institute for Energy Research (IREC), Institute of Microelectronics of Barcelona, and ETH Zurich. Pretty high aspect ratio - Open Access - enjoy!

Towards a full integration of vertically aligned silicon nanowires in MEMS using silane as a precursor

G Gadea, A Morata, J D Santos, D Dávila, C Calaza, M Salleras, L Fonseca and A Tarancón

G Gadea et al 2015 Nanotechnology 26 195302

doi:10.1088/0957-4484/26/19/195302

Samples with R = 168 and tdip = 30 s grown during 60 min at 32 mTorr of silane pressure (2.5 Torr total pressure) at different growth temperatures: (a) 520 °C; (b) 630 °C; (c) and (d) 725 °C ((d) shows a 20° tilted view). In (a), (b), and (c) higher-magnification insets show the nanowires at their middle section for diameter comparison. The inset in (d) shows a higher magnification of the nanowire tips from sample (c).

Abstract

Silicon nanowires present outstanding properties for electronics, energy, and environmental monitoring applications. However, their integration into microelectromechanical systems (MEMS) is a major issue so far due to low compatibility with mainstream technology, which complicates patterning and controlled morphology. This work addresses the growth of 〈111〉 aligned silicon nanowire arrays fully integrated into standard MEMS processing by means of the chemical vapor deposition–vapor liquid solid method (CVD–VLS) using silane as a precursor. A reinterpretation of the galvanic displacement method is presented for selectively depositing gold nanoparticles of controlled size and shape. Moreover, a comprehensive analysis of the effects of synthesis temperature and pressure on the growth rate and alignment of nanowires is presented for the most common silicon precursor, i.e., silane. Compared with previously reported protocols, the redefined galvanic displacement together with a silane-based CVD–VLS growth methodology provides a more standard and low-temperature (<650 °C) synthesis scheme and a compatible route to reliably grow Si nanowires in MEMS for advanced applications.

Saxonian President Tillich propose Euro-Chip Foundry in Dresden

News in German : http://computer-oiger.de/2015/06/24/tillich-schlaegt-euro-chip-foundry-vor/140780

The Minister-President of the German Free State of Saxony, Stanislaw Tillich (CDU) propose to the European Commission to build a European Foundry. Obviously he would like to see it built in Dresden.

Today two 300 mm Fabs are operated in Dresden, The Globalfoundries Fab1 running high performance CMOS down to 28 nm and having 22 nm FDSOI in pilot, according to a recent statement made in Grenoble (http://www.eetimes.com/document.asp?doc_id=1326954)

The other 300 mm Fab is the ex-Infineon, ex Qimonda - now Infineon 300 mm DRAM Fab that has been converted to manufacturing power semiconductors on 300mm thin wafers in its CoolMOS family. In addition, XFab has a 200 mm Fab in Dresden

It is not the first time this idea of a European foundry has surfaced in Dresden and it will be interesting to see at SEMICON Europa 6-8 October how serious this bold proposal by Mr. Tillich. We have to remember that it was on his watch when Infineon let Qimonda go down the drain in 2009. One point for discussion will obviously be - if Fab1 is struggling to keep i high utilization today - what products will fill the European Mega Fab. The answer can´t just be IoT and Industrie Vier-Punkt-Null - This would also be a Mega Investment! Let´s be hopeful - Go Tillich!

The Dresden manufacturing site is recognized throughout the industry as among the most successful leading-edge semiconductor production facility in the world. Fab 1 represents one of the biggest international investments in Germany with a total investment to date of more than $7 billion, and about 3,000 world-class engineers, technicians, and specialists. (www.globalfoundries.com)

The Dresden 200 mm site is characterized by a high degree of automation: Fully automated wafer transport, integrated production control and single wafer tracking are central elements. Every week thousands of silicon wafers pass through the highly complex production system in our high end clean room. Infineon Dresden runs production 24-hours a day, seven days a week throughout the year, in a modern and flexible shift system. In July 2011, the Infineon Management Board had decided to establish Dresden as the world's first high-volume production site for power semiconductor devices on 300mm wafers. (www.infineon.com)

The X-FAB Dresden location running analog/mixed-signal CMOS processes (www.xfab.com)

Ultratech-Cambridge NanoTech ships 400th ALD system

Ultratech, Inc., a supplier of lithography, laser­-processing and inspection systems used to manufacture semiconductor devices and high-­brightness LEDs (HB­-LEDs), as well as atomic layer deposition (ALD) systems, announced that its Cambridge NanoTech business unit, Ultratech-CNT, has shipped its 400th ALD system. The system was purchased by the University of Michigan.

Press release: http://electroiq.com/blog/2015/06/ultratech-cambridge-nanotech-ships-400th-ald-system/

Dr. Neil Dasgupta, Assistant Professor of Mechanical Engineering at University of Michigan, whose group received the ALD equipment, said, “Ultratech-CNT’s ALD system has provided a significant boost to our research productivity, enabling us to make rapid advances in the field of surface and interfacial modification of energy conversion devices, including batteries, solar cells, and catalysts. The versatility of the ALD system to address the varied needs of our research program, coupled with the depth of knowledge of their science and engineering team, has enabled us to move very quickly towards producing high-impact research. We are happy to be part of this significant milestone in receiving the 400th system, and we look forward to developing a strong relationship with Ultratech-CNT.”

Ultratech-CNT Vice-President of Research and Engineering, Ganesh Sundaram, Ph.D., said, “It has always been about the scientist and researcher, and about making them successful in achieving their research goals. We are extremely gratified by Professor Dasgupta’s decision to purchase our ALD system. We have known his work since his days as a graduate student at Stanford University, and he has consistently produced noteworthy results using ALD. Looking forward, we are excited by the prospects of the breakthroughs in science that he, along with all other researchers, will be making using our instruments. For our part, we celebrate the shipment of our 400th system and will continue our tradition of providing deep expertise combined with exciting technology.”

Ultratech-CNT’s ALD Systems: 

Savannah G2 ALD System

The Savannah G2 platform incorporates a wide range of advanced field-upgradable options intended to aid serious researchers in expanding their portfolio of available ALD films, as well as allow them to characterize the films in real time.

Phoenix G2 Batch ALD System

Engineered for high throughput, the Phoenix provides maximum uptime in any fabrication environment from pilot production to industrial-grade manufacturing. Technologists and researchers rely on the Phoenix for repeatable, highly-accurate film deposition on flat and 3-D substrates alike for batch production ALD requirements.

Fiji High-Vacuum ALD System

A modular, high-vacuum ALD system, the Fiji series accommodates a wide range of deposition modes using a flexible architecture and multiple configurations of precursors and plasma gases. The result is a next-generation ALD system capable of performing thermal and plasma-enhanced deposition.

Imec expands strategic partnership with Toshiba and SanDisk

Nanoelectronics research center imec, announced today at the Imec Technology Forum 2015 (Brussels) that Toshiba Corporation (Tokyo: 6502), SanDisk Corporation (NASDAQ: SNDK) and imec have expanded their strategic partnership with Toshiba and SanDisk joining imec’s industrial affiliation program on advanced patterning. This program tackles the critical challenges that remain in bringing EUVL to high volume manufacturing. The program also develops other technologies for extending 193nm immersion lithography. Toshiba and SanDisk have been core partners in imec’s industrial affiliation program in Advanced Memory since 2011. 

“This expanded agreement with Toshiba and SanDisk represents the next step in our long-term strategic and fruitful partnership. We are proud to join forces and strengthen our collective research competence in advanced patterning,” said Luc Van den hove, President and CEO at imec. “The agreement is a testament of the industrial value and impact our R&D programs have on advanced semiconductor scaling. To date, this program, supported by our world-class infrastructure, represents the largest investment in advanced lithography equipment in the world.” 

“Our participation in imec’s advanced patterning program provides us access to state-of-the-art lithography infrastructure for EUV technology R&D,” said Dr. Ritu Shrivastava, Vice President, Technology Development, SanDisk. “We look forward to contributing to expanding the knowledge base in this important field.”

“We are pleased to be expanding our successful strategic partnership with imec,” said Susumu Yoshikawa, Technology Executive, Memory Technology of Semiconductor & Storage Products Company, Toshiba Corporation. “This leading-edge lithography technology program should be an important contributor to accelerating scale-up in high volume semiconductor manufacturing.”

Imec’s research into advanced patterning includes GLOBALFOUNDRIES, INTEL, Micron, Panasonic, Samsung, SK Hynix, Sony, Toshiba/SanDisk and TSMC.

Chinese Labs produce Ultraclean and large-area monolayer hexagonal boron nitride on Cu foil by LPCVD

Researchers from The National Center for Nanoscience and Technology and Hubei University People's Republic of China has presented result on synthesis of large-area (4 × 2 cm2) high quality monolayer h-BN with an ultraclean and unbroken surface on copper foil by using LPCVD.

Monolayer h-BN, SAED diffraction and h-BN on SiO2/Si substrate (Source : http://nanotechweb.org/cws/article/lab/61589).

Ultraclean and large-area monolayer hexagonal boron nitride on Cu foil using chemical vapor deposition

Yao Wen, Xunzhong Shang, Ji Dong, Kai Xu, Jun He and Chao Jiang

2015 Nanotechnology 26 275601. doi:10.1088/0957-4484/26/27/275601

Atomically thin hexagonal boron nitride (h-BN) has been demonstrated to be an excellent dielectric layer as well as an ideal van der Waals epitaxial substrate for fabrication of two-dimensional (2D) atomic layers and their vertical heterostructures. Although many groups have obtained large-scale monolayer h-BN through low pressure chemical vapor deposition (LPCVD), it is still a challenge to grow clean monolayers without the reduction of domain size. Here we report the synthesis of large-area (4 × 2 cm2) high quality monolayer h-BN with an ultraclean and unbroken surface on copper foil by using LPCVD. A detailed investigation of the key factors affecting growth and transfer of the monolayer was carried out in order to eliminate the adverse effects of impurity particles. Furthermore, an optimized transfer approach allowed the nondestructive and clean transfer of the monolayer from copper foil onto an arbitrary substrate, including a flexible substrate, under mild conditions. Atomic force microscopy indicated that the root-mean-square (RMS) roughness of the monolayer h-BN on SiO2 was less than 0.269 nm for areas with fewer wrinkles. Selective area electron diffraction analysis of the h-BN revealed a pattern of hexagonal diffraction spots, which unambiguously demonstrated its highly crystalline character. Our work paves the way toward the use of ultraclean and large-area monolayer h-BN as the dielectric layer in the fabrication of high performance electronic and optoelectronic devices for novel 2D atomic layer materials.

Picosun and Nanexa collaborate in ALD for Medical technology in ECSEL InForMed led by Philips

Picosun Oy provides the advanced ALD coating solutions to enable the next generation of cutting-edge medical technology.

ALD’s unique ability to form perfectly hermetic but still ultra-thin encapsulation layers to cover even the smallest, most complex surface details and particles is an invaluable asset to the medical equipment and medicine manufacturers. It increases the operational life, reliability, and safety of the equipment and enables advanced synthesis, delivery, and dosing of medical substances. Several ALDmaterials are naturally biocompatible and, as a gas-phase, low temperature method, ALD allows coating of sensitive substrates such as plastics and polymers – key materials in various medical devices.

“Incorporation of our ALD solutions into the field of medical technology opens up an interesting new market for us. ALD-enabled medical innovations already create growth and success for our customers – an example being recently stock listed Nanexa AB in Sweden, which utilizes our ALD technology in production of nanofabricated drug delivery Systems. In InForMed, one of our new, inter-European ECSEL projects we cooperate with the leading industries in the field. We are excited to see our ALDexpertise realize the most advanced, better, safer, and patient-friendly diagnostics and treatment equipment,” states Juhana Kostamo, Managing Director of Picosun.

Source: PrNewsWire
Picosun ALD Breaks Through in Medical Technology

The InForMed project - ECSEL Joint Undertaking

The project InForMed (An integrated pilot line for micro-fabricated medical devices), running from 1st June 2015 to 31st May 2018 is financed by ECSEL Joint Undertaking.

The InForMed project will establish an industrial integrated micro-fabrication pilot line for medical devices, covering the complete innovation chain from technology concept to system qualification.

The heart of the pilot line is the industrial facility of Philips Innovation Services (PInS), which will serve as a small/medium-scale production and assembly facility, qualified for medical devices. Connected to this infrastructure are European partners who provide complementary capabilities that enable the heterogeneous integration required for these devices.

The pilot line is fed by new concepts, generated by academic and industrial research. For high volume production the pilot line is connected to well established foundries. Protocols have been defined to ensure an efficient transfer of technologies from the concept creation phase (TRL 4/5) to the pilot line, and from the pilot line to high volumes production (TRL 7/8).

The pilot line is demonstrated by six demonstrator products that cover innovations in existing markets, enable emerging markets and pioneer new markets, respectively. The pilot line will help consolidating Europe’s strong position in diagnostic equipment, and it will create innovative value chains in emerging and new markets in medical equipment and even pharmacology.

Pegasus - New UK ALD and CVD Precursor company

Pegasus Chemicals is a privately owned UK company focused on localised support of the European ALD and CVD community with our ability to supply specialist chemicals, packaged for individual applications. We specialise in the high purity transfil and manufacture of small scale products for niche applications. Our product portfolio is wide and varied with specific focus on intrinsic purity and consistency. Our technical and product application knowledge in ALD and CVD has been honed through the manufacture and supply of specialist chemistry with many years experience. Our technical service team is available to discuss your deposition requirements to tailor the product with the application. 

www.pegasuschemicals.com 

Penn State - Diode a few atoms thick shows surprising quantum effect

As publish by Penn State : A quantum mechanical transport phenomenon demonstrated for the first time in synthetic, atomically-thin layered material at room temperature could lead to novel nanoelectronic circuits and devices, according to researchers at Penn State and three other U.S. and international universities.

Atomic multilayer structure of van der Waals solids representing layering with a graphene substrate.

Current-voltage curves of single junction (green) van der Waals solid (no NDR) and multijunction (red, orange) van der Waals solids (NDR). Stacking and choice of materials determines the location and width of peak.

The quantum transport effect, called negative differential resistance (NDR), was observed when a voltage was applied to structures made of one-atom-thick layers of several layered materials known as van der Waals materials. The three-part structures consist of a base of graphene followed by atomic layers of either molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), or tungsten diselenide (WSe2).

NDR is a phenomenon in which the wave nature of electrons allows them to tunnel through any material with varying resistance. The potential of NDR lies in low voltage electronic circuits that could be operated at high frequency.

“Theory suggests that stacking two-dimensional layers of different materials one atop the other can lead to new materials with new phenomena,” said Joshua Robinson, a Penn State assistant professor of materials science and engineering whose student, Yu-Chuan Lin, is first author on a paper appearing online today, June 19, in the journal Nature Communications. The paper is titled “Atomically Thin Resonant Tunnel Diodes Built from Synthetic van der Waals Heterostructures.”

Achieving NDR in a resonant tunneling diode at room temperature requires nearly perfect interfaces, which are possible using direct growth techniques, in this case oxide vaporization of molybdenum oxide in the presence of sulfur vapor to make the MoS2 layer, and metal organic chemical vapor deposition to make the WSe2 and MoSe2.

Full article : Diode a few atoms thick shows surprising quantum effect

A Novel ALD SiBCN Low-k Spacer for FinFETs presented at VLSI 2015 in Kyoto

A key challenge in reducing capacitance around the transistor is incorporating spacer and contact etch stop materials that are simultaneously low-k and robust to processing. One approach is to develop new low-k materials that can withstand the processing conditions [IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 7, JULY 2012]

A Novel ALD SiBCN Low-k Spacer for FinFETs presented at VLSI 2015 in Kyoto by IBM and Globalfoundries. The abstract does not give too many details on the ALD process itself except that it is a "a novel low temperature ALD-based SiBCN material has been identified". However, the conference proceeding states that the SiBCN is deposited in a batch furnace:

• SiBCN low k spacer was deposited in a batch furnace at 600 °C. The referral to low thermal process here may relate to earlier CVD processes at higher process temperatures.
• The process was run in thermal ALD mode with alternating layers of BN and SiCN. 
• The B/C ratio in the film was controlled by adjusting the BN:SiCN cycle ratio

A Novel ALD SiBCN Low-k Spacer for Parasitic Capacitance Reduction in FinFETs

T. Yamashita*, S. Mehta*, V. S. Basker*, R. Southwick*, A. Kumar**, R. Kambhampati*** , R. Sathiyanarayanan**, J. Johnson**, T. Hook*, S. Cohen*, J. Li*, A. Madan*, Z. Zhu*, L. Tai*, Y. Yao*, P. Chinthamanipeta*, M. Hopstaken*, Z. Liu*, D. Lu*, F. Chen**, S. Khan**, D. Canaperi*, B. Haran*, J. Stathis*, P. Oldiges*, C.-H. Lin*, S. Narasimha**, A. Bryant*, W. K. Henson**, S. Kanakasabapathy*, K. V. R. M. Murali**, T. Gow*, D. McHerron*, H. Bu* and M. Khare*, *IBM Research, **IBM SRDC and ***GLOBALFOUNDRIES, USA 

FinFET has become the mainstream logic device architecture in recent technology nodes due to its superior electrostatic and leakage control. However, parasitic capacitance has been a key performance detractor in 3D FinFETs. In this work, a novel low temperature ALD-based SiBCN material has been identified, with an optimized spacer RIE process developed to preserve the low-k value and provide compatibility with the down-stream processes. The material has been integrated into a manufacturable 14nm replacement-metal-gate (RMG) FinFET baseline with a demonstrated ~8% performance improvement in the RO delay with reliability meeting the technology requirement. A guideline for spacer design consideration for 10nm node and beyond is also provided based on the comprehensive material properties and reliability evaluations.

How to make carbon nano particles in the kitchen

Stuff the naked chef Jamie Oliver - Welcome to the first season of The Bald Swedish Chef - humpee, dumpee dump - put the chicken in the pot. In our first show we will take a closer look on how you can make car con nano particles at home in your kitchen.

Some background information - why do we need nano sized carbon particles in the first case? As reported here in Science Daily, researchers have found an easy way to produce carbon nanoparticles that are small enough to evade the body's immune system, reflect light in the near-infrared range for easy detection, and carry payloads of pharmaceutical drugs to targeted tissues. 

University of Illinois postdoctoral researcher Prabuddha Mukherjee, left, bioengineering professors Rohit Bhargava and Dipanjan Pan, and postdoctoral researcher Santosh Misra, right, report the development of a new class of carbon nanoparticles for biomedical use.

The researchers form Illinois at Urbana-Champaign have developed a new approach that generates the particles in a few hours and uses only a handful of ingredients, including store-bought molasses.

"If you have a microwave and honey or molasses, you can pretty much make these particles at home," Pan said. "You just mix them together and cook it for a few minutes, and you get something that looks like char, but that is nanoparticles with high luminescence. This is one of the simplest systems that we can think of. It is safe and highly scalable for eventual clinical use."

The nanoparticles also can be made quite small, less than eight nanometers in diameter.

"Our immune system fails to recognize anything under 10 nanometers," Pan said. "So, these tiny particles are kind of camouflaged, I would say; they are hiding from the human immune system."

So guys, I am off on a camping trip to South of France and if I come across any of that grandma´s Molasses at Carrefour I intend to report back on the experimental procedure. Stay tuned. I did however forget to pack the TEM grids so the verification of the results have to wait until I am back in the lab. Unless there is an optical scattering method that can be used to detect those particles...

The abstract to the paper where the research above has been reported:

Tunable Luminescent Carbon Nanospheres with Well-Defined Nanoscale Chemistry for Synchronized Imaging and Therapy

Prabuddha Mukherjee, Santosh K. Misra, Mark C. Gryka, Huei-Huei Chang, Saumya Tiwari, William L. Wilson,  John W. Scott, Rohit Bhargava and Dipanjan Pan

Article first published online: 20 MAY 2015

DOI: 10.1002/smll.201500728

In this work, we demonstrate the significance of defined surface chemistry in synthesizing luminescent carbon nanomaterials (LCN) with the capability to perform dual functions (i.e., diagnostic imaging and therapy). The surface chemistry of LCN has been tailored to achieve two different varieties: one that has a thermoresponsive polymer and aids in the controlled delivery of drugs, and the other that has fluorescence emission both in the visible and near-infrared (NIR) region and can be explored for advanced diagnostic modes. Although these particles are synthesized using simple, yet scalable hydrothermal methods, they exhibit remarkable stability, photoluminescence and biocompatibility. The photoluminescence properties of these materials are tunable through careful choice of surface-passivating agents and can be exploited for both visible and NIR imaging. Here the synthetic strategy demonstrates the possibility to incorporate a potent antimetastatic agent for inhibiting melanomas in vitro. Since both particles are Raman active, their dispersion on skin surface is reported with Raman imaging and utilizing photoluminescence, their depth penetration is analysed using fluorescence 3D imaging. Our results indicate a new generation of tunable carbon-based probes for diagnosis, therapy or both.

IKEA invests in French GaN on Silicon LED lighting technology

As reported by Electronics Weekly : Ikea’s venture capital arm has invested in a French firm developing and manufacturing 3D LEDs. Grenoble-based Aledia is developing LEDs for lighting based a gallium-nitride-on-silicon technology.

Two years after it began phasing out incandescent bulbs, Swedish retailer Ikea announced that it is taking another step and planning to sell only energy-efficient LED lighting by 2016.

Ikea believes there is this low-price LED lighting technology for residential use has the potential of faster implementation of the LED technology, leading to savings for customers.

Christian Ehrenborg, managing director of Ikea GreenTech AB, said:

“This technology will be one important part in the IKEA Group strategy to supply high-quality, energy-saving lighting products to consumers worldwide.”

Christian Ehrenborg, Bald guy.

Aledia received the investment from IKEA as part of a €28.4m funding round.

“This financing round, abundantly oversubscribed and particularly the presence of two very large potential corporate customers, testifies to the interest that our cost-disruptive nanowire LED technology is generating in the customer base, as well as in the financial community,” said Giorgio Anania, CEO, chairman and co-founder of Aledia.

Aledia is developing LEDs that are manufactured on 200mm diameter GaN-on-silicon wafers to keep cost down.

Anania said:

“We are progressing with the development of the technology and this financing round will allow us to accelerate significantly the speed of development and the customer traction. In Valeo we have a major potential customer in the automotive LED market, generally viewed as the most profitable market segment. Simultaneously with the investment, we have signed a supply agreement with Valeo.”

The technology was originally developed by CEA-Leti

- See more at: http://www.electronicsweekly.com/news/components/led-lighting/ikea-invests-french-gan-based-led-lighting-firm-2015-06/#sthash.gbtq0uPP.dpuf

Fundamental Differences in Planar and 3D LEDs

(Some background information from www.aledia.com)

Conventional LEDs are planar, two-dimensional (2D) devices that emit light from a thin material layer at or near their flat surfaces. They typically are made by depositing multiple layers of various materials, each having different thermal expansion and crystal lattice constants, on small wafers with diameters between 2 inches and 6 inches. The vast majority of LEDs are made of GaN and indium gallium nitride (InGaN) material. Depositing high-quality layers of these materials requires the GaN to be grown on substrate wafers that are made of expensive materials such as sapphire, silicon carbide or gallium nitride, as these materials are closely matched to GaN in terms of thermal expansion coefficient and crystal lattice parameters. Building planar GaN LEDs on larger and less expensive wafers made of silicon – a material that is very different from GaN in terms of thermal expansion and crystal lattice constant – is being tried, but to date this approach has shown only moderate cost savings while often incurring high defect densities, lower performance and lower yields. These factors contribute to the high costs of today’s LEDs.

In contrast, Aledia’s WireLED product technology uses economical silicon wafers with diameters of 8 inches (200 mm) or larger. On each wafer, millions of vertical microwires or microrods of GaN are grown, each with a diameter of less than 1 micron. Each microwire is an LED, capable of emitting light from all sides.

Standard Technology - 2D (Planar) LEDs:
• Small, expensive substrate
• Slow MOCVD growth process (high capital expenditure)
• High materials consumption
• LED-specific manufacturing plants
• Light emission area = at most the 2D area
• Single color on one wafer

3D (Microwire) LEDs:
• Large, economical substrate
• Fast MOCVD growth process (low capital expenditure)
• Low materials consumption
• Existing high-volume silicon wafer fabs
• Light emission area = up to 3X the 2D area = more light/mm2 or less current density, less efficiency droop
• Multiple colors on one wafer or even on one chip

Graphene Benchmarked to TaN as Cu Diffusion Barrier for Ultimate Interconnect Scaling

Here is an interesting paper from VLSI2015 in Kyoto Japan (Symposia of VLSI Technology and Circuits ) from Stanford and Univ. of Wisconsin–Madison wrapping graphene around the Cu lines instead of tantalum nitride barriers for future scaled interconnects. It will be interesting to see more solid data once these become available. As you probably read this many times - graphene sucks as a future channel material for future CMOS since it does not have band gap and there are various attempts to solve this problem - we just have to use graphene for something and especially in semiconductor technology. However, in Cu interconnects you could´t care less about the lack of a bandgap and it would be sort of funny and maybe a bit unexpected if graphene were to be implemented in BEOL instead of FEOL.

H.-S. P. Wong, Professor of Electrical Engineering

“Graphene has been promised to benefit the electronics industry for a long time, and using it as a copper barrier is perhaps the first realization of this promise,” Wong said.

Check out this article in Stanford Engineering for more details and answers from the researchers: http://engineering.stanford.edu/news/stanford-engineers-find-simple-yet-clever-way-boost-chip-speeds

VLSI 2015 Abstract:

Cu Diffusion Barrier: Graphene Benchmarked to TaN for Ultimate Interconnect Scaling

L. Li*, X. Chen*, C.-H. Wang*, S. Lee*, J. Cao*, S. S. Roy**, M. S. Arnold** and H.-S. P. Wong*, *Stanford Univ. and **Univ. of Wisconsin–Madison, USA 

The advantages of graphene diffusion barrier are studied and benchmarked to the industry-standard barrier material TaN for the first time. Even when the wire width is scaled to 10 nm, the effective resistivity of the Cu interconnect is maintained near the intrinsic value of Cu using a 3 Å single layer graphene (SLG) barrier. In the time dependent dielectric breakdown (TDDB) test, 4 nm multi-layer graphene (MLG) gives 6.5X shorter mean time to fail (MTTF) than 4 nm TaN. However when the barrier thickness is reduced, 3 Å single-layer graphene (SLG) gives 3.3X longer MTTF than 2 nm TaN, showing that SLG has better scaling potential. The influences of graphene grain size and various transfer methods are presented for further improving the SLG barrier performance.

Silicon Nanowire Remains Favorite to Replace FinFET

VLSI 2015 is going on and there are a lot of interesting information flowing from there and especially on the future of CMOS scaling. Here is a good article on what´s next after FinFET by Peter Clarke. He is claiming that Silicon Nanowires is the most probable path, i.e., not III/V on silicon: Silicon Nanowire Remains Favorite to Replace FinFET. The article is based on the published information and opinions from ARM, Imec, and Prof. Asenov and tries to give insights to some of the major questions and possible issues:

• Vertical or Lateral?
• With or without EUV?
• What Material?

Below some of the statements made by the experts in the article by Peter Clarke. Please do read the article for the full story here (IHS Electronics360).

Prof. Asen Asenov of Glasgow University and CEO of Gold Standard Simulations

Asenov says, "I do not think that there is a real alternative to NWTs. They are a natural progression to FinFETs. Think of it like this: MOSFET—gate on the side of the channel; FinFET—gate on three sides of the channel; NWT or gate all around—gate on four sides of the channel." In a word, ultimate control of the current.

Aaron Thean, logic research director at IMEC.

"At IMEC we look at silicon, silicon-germanium and III-V channel materials but the preference is silicon." Other materials suffer from immaturity. "You have to ask what is the value proposition for these materials? SiGe improves mobility but there are issues of reliability. It is very difficult to passivate the surface." So for Thean, at least, progress is likely to be based in silicon with first-scaled FinFET. That means a taller fin, then movement to lateral nanowire transistors. But it still needs some level of innovation, he says.

Lucian Shifren, principal engineer at ARM.

"Gate-all-around silicon is most likely for a 'real' 7nm," Shifren says. He adds that the nominal 7nm would likely be a pseudo-scaled FinFET and that the nominal 5nm process would be gate-all-around.

New RASIRC Peroxidizer Delivers High Concentration Hydrogen Peroxide Gas into Semiconductor Processes

Today, RASIRC publicly announced the Peroxidizer, a high concentration hydrogen peroxide (H2O2) vaporizer designed specifically for the needs of next generation semiconductor processes, These include Atomic Layer Deposition (ALD), annealing, cleaning and etching. The Peroxidizer is the first commercial vaporizer capable of delivering concentrations greater than 5% H2O2 gas by volume from 30% H2O2 liquid source. Delivered droplet-free and at temperatures as low as 80C, H2O2 is a superior oxidant for use with new semiconductor materials and processes that are sensitive to high temperature and defects. The Peroxidizer delivers 10 times higher concentration than the previous technology it replaces.

The Peroxidizer eliminates problems associated with other oxidants used in semiconductor fabrication processes. Ozone and oxygen plasma are too aggressive, penetrating below the interface layer and damaging both surface structures and the bottom electrode. Both ozone and water have greater steric hindrance than H2O2, resulting in a less dense interface layer. In addition, plasma cannot deeply penetrate high aspect structures, resulting in non-uniform coatings. Water is less reactive than H2O2 gas. Water requires higher process temperatures, which makes it a poor choice with new materials, new precursors, and lower thermal budgets.

The Internet of Things requires low power and high performance semiconductor devices, which will only be enabled through new materials and 3D architectures, explains Jeffrey Spiegelman, RASIRC Founder and President. However, these new devices can only be processed at lower temperatures and their complicated physical structures make deposition and cleaning a new challenge for the semiconductor industry. The Peroxidizer is the first tool to enable stable and particle-free delivery of high concentration hydrogen peroxide gas, enabling lower process temperatures, greater use of new materials and high process throughput. It is really exciting to bring an old molecule to market in a completely new state.

The Peroxidizer is the latest innovation in high purity gas generating products from RASIRC. Its Stabilized Gas Delivery system was the first in the industry to deliver high purity, stable H2O2 gas by overcoming Raoults Law, which causes preferential selection of water molecules from H2O2 solution. The SGD used pre-humidification to ensure that the liquid H2O2 source remained at constant concentration while delivering H2O2 gas to process at a 50:1 water to H2O2 molar ratio. The Peroxidizer further reduces that ratio to 4:1, allowing as much as 5% H2O2 gas by volume to flow to process. The Peroxidizer eliminates the pre-humidification step by concentrating the liquid source until the molar ratio in the headspace reaches 4:1.

Atomic Layer Deposition (ALD)

H2O2 gas is more reactive than water at low temperatures. The Peroxidizer delivers H2O2 gas at temperatures as low as 80C, well below the H2O2 liquid boiling point. Low delivery temperatures enlarge the available thermal budget.

H2O2 gas achieves higher density nucleation than other oxidants. H2O2 has less steric hindrance than water or ozone because it decomposes into hydroxyls on surfaces. The resulting dense layer of hydroxyls creates an ideal surface for ALD.

High reactivity enables process engineers to use precursors that normally would not react with water or ozone. This reactivity also results in active removal of carbon.

The Peroxidizer delivers at a 4:1 water:H2O2 molar ratio, the most concentrated H2O2 gas delivery available and a 10x improvement over the previous generation from a 30% liquid source. Previous ALD studies frequently assumed that H2O2 was delivered at 4:1 ratio when in fact H2O2 delivery was much lower at 100:1. For the first time, ALD processes can use H2O2 with minimal interference from water vapor.

High concentration H2O2 gas enables lower temperature processing, new precursor choices, better removal of residual carbon from the surface, and better initiation on the surface of the wafer, stated Spiegelman. All these advantages make hydrogen peroxide gas a very exciting new molecule for the ALD community.

Annealing

High concentration H2O2 gas is well-suited for annealing applications where high speed deposition and low operating temperatures are required. H2O2 gas is a good oxidant that can penetrate deep structures. More aggressive oxidants like plasma and ozone can damage surface materials and sensitive structures. H2O2 gas reduces the required thermal budget, protecting against high heat exposure that causes film shrinkage.

The ability to replace water vapor and steam with hydrogen peroxide gas reduces time and operating temperature. This will enable next generation gap fill technology, a critical milestone for success with 3D structures, said Spiegelman.

Surface Preparation and Cleaning

Hydrogen peroxide gas enables dry in situ cleaning and surface preparation, eliminating the need for liquid baths and the contamination risk associated with transfers from bath to chamber. Less chemical is required for this dry process and no drying step is needed.

Hydrogen peroxide gas removes carbon-based contaminants on wafer surfaces while avoiding damage to device structures that can be caused by ozone or liquids. Organic hydrocarbons are oxidized, enabling their removal.

The Peroxidizer gives fabs a great alternative to their current cleaning technologies, said Spiegelman. The ability to deliver hydrogen peroxide as a gas instead of a liquid speeds the move away from wet processing to more effective dry cleaning, which will be needed to support Moores Law.

Versatility

With the Peroxidizer, process engineers can precisely control their processes. The Peroxidizer delivers hydrogen peroxide gas in concentrations from 12,500 to greater than 50,000 parts per million depending on flow rate. This correlates to 1.25 to 5+% gas by volume delivery to process. The Peroxidizer supports carrier gas flows from 5 to 20 SLM in vacuum to atmospheric pressure. The Peroxidizer is available immediately. For details and to order, contact RASIRC.

Original Source: http://www.newswire.com/press-release/new-rasirc-peroxidizer-delivers-high-concentration-hydrogen

Imec presents successors to FinFET for 7nm and beyond at VLSI Technology Symposium 2015

Leuven (Belgium)– June 17, 2015 – At this week’s VLSI 2015 Symposium in Kyoto (Japan), imec reported new results on nanowire FETs and quantum-well FinFETs towards post-FinFET multi-gate device solutions. 

The Technology roadmap as presented recently by Imec at the EWMOVPE workshop in Lund, Sweden.

As the major portion of the industry adopts FinFETs as the workhorse transistor for 16nm and 14nm, researchers worldwide are looking into the limits of FinFETs and potential device solutions for the 7nm node and beyond. Two approaches, namely Gate-All-Around Nanowire (GAA NW) FETs, which offer significantly better short-channel electrostatics, and quantum-well FinFETs (with SiGe, Ge, or III-V channels), which achieve high carrier mobility, are promising options. 

For the first time, imec demonstrated the integration of these novel device architectures with state-of-the-art technology modules like Replacement-Metal-Gate High-k (RMG-HK) and Self (Spacer)-Aligned Double-Patterned (SADP) dense fin structures. By building upon today’s advanced FinFET technologies, the work shows how post-FinFET devices can emerge, highlighting both new opportunities as well as complexities to overcome. 

Imec and its technology research partners demonstrated SiGe-channel devices with RMG-HK integration. Besides SiGe FinFET, a unique GAA SiGe nanowire channel formation during the gate replacement process has been demonstrated. The novel CMOS-compatible process converts fin channels to nanowires by sacrificial Si removal during the transistor gate formation. The process may even enable future heterogeneous co-integration of fins and nanowires, as well as Si and SiGe channels. The work also demonstrates that such devices and their unique processing can lead to a drastic 2x or more improvement in reliability (NBTI) with respect to Si FinFETs. 

Moreover, imec demonstrated Si GAA-NW FETs based on SOI with RMG-HK. The work compares junction-based and junction-less approaches and the role of gate work function for multi-Vt implementations. New insights into the improved reliability (PBTI) with junction-less nanowire devices have been gained.

Extending the heterogeneous channel integration beyond Si and SiGe, imec demonstrated for the first time strained Ge QW FinFETs by a novel Si-fin replacement fin technique integrated with SADP process. Our results show that combining a disruptive approach like fin replacement with advanced modules like SADF-fin, RMG-HK, direct-contacts can enable superior QW FinFETs. The devices set the record for published strained Ge pMOS devices, outperforming by at least 40% in drive current at matched off-currents.

Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GLOBALFOUNDRIES, INTEL, Micron, Panasonic, Samsung, SK hynix, Sony and TSMC.

Video Picosun - PICOPLATFORM™ cluster tools

Picosun represents the cutting-edge in everything ALD – from the world class equipment design to the leading process quality, highest level after sales service and the best customer care.

PICOSUN™ ALD product portfolio provides fully automated, SEMI compliant high throughput production solutions in batch and cluster mode to global industries, and the most versatile and flexible R&D systems to research organizations and pilot manufacturing. 

LAM Research is gearing up for the upcoming Atomic Layering Weeks in Portland!

LAM Research is obviously gearing up for the upcoming Atomic Layering Weeks in Portland!

Every Atom Matters at These Conferences

June 15, 2015 

as posted in the LAM Research Blog : http://blog.lamresearch.com/blog-home/Post/428/Every-Atom-Matters-at-These-Conferences

Experts in the atomic-scale processing community will soon assemble at the AVS ALD 2015 Conference and the ALE Workshop to share advances in fundamental understanding and discuss recent progress in thin film device applications. Atomic layer deposition (ALD) and atomic layer etching (ALE) can provide chipmakers with advanced capabilities and process control that enable next-generation device manufacturing. As a leading provider of atomic-scale deposition and etch capabilities, Lam Research is pleased to be a platinum sponsor of both these AVS-hosted events. We will also share some of our work, as highlighted below.




One of the most important conferences on ALD, the International Conference on Atomic Layer Deposition, will take place this year June 28-July 1 in Portland, Oregon. Lam’s Dr. Adrien LaVoie will give an invited talk on ALD in high-volume manufacturing. Addionally, there will be four oral presentations and four poster presentations featuring work by Lam.

Optimizing Plasma Environment in PEALD to Suppress Parasitics and Enable Production-Worthy Processing

F.L. Pasquale, C. Baldasseroni, E. Augustyniak, S. Swaminathan, P. Ni, K. Leeser, D.C. Smith, S. Varadarajan, A. LaVoie
Monday, June 29, 1:30 PM

(Invited) ALD for High Volume Manufacturing: Latest Trends, Developments, and Market Applications

A. LaVoie

Monday, June 29, 3:00 PM

Plasma Effects on Conformality for Atomic Layer Deposition of Silicon Nitride

K. Kelchner, S. Tang, G. Yuan, D. Hausmann, J. Henri, J. Sims
Monday, June 29, 5:15 PM

Computational Modelling of Atomic Layer Deposition of Silicon Carbide

E. Filatova, S. Elliott (Tyndall National Institute); D. Hausmann (Lam Research)
Monday, June 29, 5:30 poster session

Towards Atomic Layer Deposition of Carbon-Containing Silicon-Based Dielectrics

R.A. Ovanesyan, R.J. Gasvoda (Colorado School of Mines); D.M. Hausmann (Lam Research); S. Agarwal (Colorado School of Mines)
Tuesday, June 30, 3:15 PM

Atomic Layer Deposition of Titanium Nitride Thin Film Using Unsymmetrical Dimethyl Hydrazine

S.V. Thombare, I. Karim, S. Gopinath
Tuesday, June 30, 5:30 PM poster session

Precursor and Process Effects on Conformality for Atomic Layer Deposition of Silicon Nitride Using Nitrogen (N2) Plasma

S. Tang, K. Kelchner, G. Yuan, D. Hausmann, J. Henri, J. Sims
Tuesday, June 30, 5:30 PM poster session

Wafer-Scale Selective Deposition of Nanometer Metal Oxide Features Via Selective Saturated Vapor Infiltration into Pre-Patterned Poly(Methyl Methacrylate) Template

E. Dandley (North Carolina State University); A. Yoon, Z. Zhu, L. Sheet (Lam Research); G. Parsons (North Carolina State University)
Wednesday, July 1, 8:15 AM

Plasma Enhanced Atomic Layer Deposition of SiO2 in Sub-Saturation Regime

P. Kumar, H. Kang, J. Qian, A. LaVoie
Wednesday, July 1, 8:30 AM






In recognition of ALE’s growing importance, an Atomic Layer Etching Workshop dedicated to this topic will be held on July 1-2 in Portland, Oregon, following ALD 2015. Dr. Eric Hudson will give an invited talk on ALE for self-aligned contacts. We will also share our work on the science and applications of atomic layer etching during the poster session.

Selective Removal of Native SiO2 Using XeF2

A. Hinckley, P. Mancheno (Univ. of Arizona); S. Lai (Lam Research); A. Muscat (Univ. of Arizona)
Wednesday, July 1, 6:00 PM poster session

Overview of Atomic Layer Etching

K.J. Kanarik, T. Lill, E.A. Hudson, S. Sriraman, S. Tan, J. Marks, V. Vahedi, R.A. Gottscho
Wednesday, July 1, 6:00 PM poster session

(Invited) Fluorocarbon-Based Atomic Layer Etching of Silicon Dioxide for Self-Aligned Contact

E.A. Hudson, R. Bhowmick, R. Bise, H. Shin, G. Delgadino, B. Jariwala, D. Lambert, S.J. Cho, S. Deshmukh
Thursday, July 2, 2:20 PM

SoLayTec garners repeat ALD orders from China for PERC production

Atomic layer deposition (ALD) equipment specialist SoLayTec, a subsidiary of Amtech Systems has secured orders from two China-based PV manufacturers. Image: SoLayTec.

Atomic layer deposition (ALD) equipment specialist SoLayTec, a subsidiary of Amtech Systems has secured orders from two China-based PV manufacturers.

Critically, SoLayTec has received its first follow-on order for its modular InPassion system from an existing customer, since first evaluating ALD technology in 2011. The customer entered volume production using the technology in 2014, resulting in a repeat order for production later in 2015. The company said that tool delivery was planned for June.

The second order is for an R&D evaluation with a new client with the expectation of taking the technology from lab to fab in the future. SoLayTec said that in principle the new customer would commence R&D activities with one module, which can handle at least 600wph. However, after pilot testing and validation, the tool can be upgraded to mass production by adding the other modules to reach a maximum throughput of 3,600wph.

Roger Görtzen, co-founder of SoLayTec and manager marketing and sales said: “Since 2011 SoLayTec is working very closely with this Tier one customer and SoLayTec is proud that they have accepted our InPassion ALD in full production last year. They started PERC research with our InPassion LAB tool in 2011 and moved towards mass production in 2014, starting with our InPassion ALD system with three modules (1800wph). This was accepted within three months after which they purchased another three modules upgrading the tool to 3600wph and at the same time showing the advantage of our modular tool set-up. So now SoLayTec has reached its next milestone by repeat orders. This clearly shows the equipment readiness for mass production for the PV market.”

ALD competed with PECVD and APCVD deposition techniques to provide tightly specified thicknesses of Al2O3 for surface passivation of both the front and real cell in a PERC configuration. Tighter deposition control can produce higher efficiency cells.

Financial details were not disclosed.

KAIST on BCP lithography for flexible nanoelectronics

Here is an impressive overview from Prof. Keon Jae Lee and co-workers at KAIST on directed block copolymer (BCP) self-assembly for applications for electronic and energy devices.

The semiconductor industry depend on conventional lithography (Optical Lithography) based on a light source, photoresist materials and photo masks. A number of alternative patterning techniques have been developed  to improve the pattern resolution. However, the limitation has been that of light diffraction which is wave length dependent and reducing the wave length has become a major cost issue for the new technologies of the light source. Another major drawback is that the leading technology is wafer based and there is a drive to integrate future device on flexible substrates and reduce the overall cost of lithography and device production by either large area panels (e.g. displays, solar cells) or roll to roll flexible foil production technologies.

The next-generation lithographic techniques on the nanometer scale are:

• electron-beam lithography (EBL) - low throughput
• nanoimprinting lithography (NIL) - requires a costly master template
• directed block copolymer (BCP) self-assembly - relies spontaneous microscopic phase separation of covalently linked polymer blocks

Performance Enhancement of Electronic and Energy Devices via Block Copolymer Self-Assembly

Hyeon  Gyun Yoo, Myunghwan Byun, Chang Kyu Jeong, and Keon Jae Lee 

Adv. Mater. 2015,
DOI: 10.1002/adma.201501592

The use of self-assembled block copolymers (BCPs) for the fabrication of electronic and energy devices has received a tremendous amount of attention as a non-traditional approach to patterning integrated circuit elements at nanometer dimensions and densities inaccessible to traditional lithography techniques. The exquisite control over the dimensional features of the self-assembled nanostructures (i.e., shape, size, and periodicity) is one of the most attractive properties of BCP self-assembly. Harmonic spatial arrangement of the self-assembled nanoelements at desired positions on the chip may offer a new strategy for the fabrication of electronic and energy devices. Several recent reports show the great promise in using BCP self-assembly for practical applications of electronic and energy devices, leading to substantial enhancements of the device performance. Recent progress is summarized here, with regard to the performance enhancements of non-volatile memory, electrical sensor, and energy devices enabled by directed BCP self-assembly.

JUST RELEASED - TEHCHET's 2015 Materials Market and Business Trends, Supply Chain Reports

IoT is growing those materials considered trailing edge. 3D devices is driving growth on the front end. Enabling packaging technologies paving the way for mid-high end device connectivity. Gases, Targets, CMP Consumables, WLP Polymers and Silicon Wafers Reports just released.

SoLayTec InPassion ALD for Al2O3 2015 Promotion Video

The In Passion Spatial ALD tool from SoLayTec is just one of the coolest ALD tools on the martket. These guys also produces the best promotion videos. Check out the latest one! What a concept - swapping chambers in full production.

SoLayTec is a spin-off company of the Dutch research organisation TNO and established in 2010. SoLayTec is part of the Amtech Group (Nasdaq ASYS). The company develops, delivers and services machines for atomic layer deposition (ALD) on solar cells worldwide. The SoLayTec ALD machines are designed for mass production in the solar market. In the field of solar cell ALD equipment, SoLayTec has a leading 

University of Cincinnati and Industry Partners Develop Low-Cost Tunable Window Tintings

As reported by University of Cincinnati - Technology developed by the University of Cincinnati and industry partners can do something that neither blinds nor existing smart windows can do. This patent-pending research, supported by the National Science Foundation, will lead to low-cost window tintings which dynamically adapt for brightness, color temperatures and opacity (to provide for privacy while allowing light in). 

Top view and side-view diagrams of the device construction.

Technology developed by the University of Cincinnati and industry partners can do something that neither blinds nor existing smart windows can do. This patent-pending research, supported by the National Science Foundation, will lead to low-cost window tintings which dynamically adapt for brightness, color temperatures and opacity (to provide for privacy while allowing light in). 

Full story here : http://www.uc.edu/news/NR.aspx?id=21741