Friday, May 22, 2015

Imec 5 day training in Nanoscale CMOS process technology


Imec offers a 5 day training in Nanoscale CMOS process technology 8-12 June in Leuven, Belgium. Here is the full program and for ALD guys there is especially two sessions that must be of interest (below) plus courses  in interconnects, memory and emerging memory.


Material deposition 

Essentially, manufacturing of semiconductor devices is based on the deposition and removal of layers/materials, with intermediate lithographic patterning steps. This lecture gives an overview of the most prevalent layer deposition processes as used in manufacturing of semiconductor circuits. Basically, most of these processes are based on the use of chemical precursors and are therefore called ‘Chemical Vapor Deposition’ processes. Next to the generic thermal and plasma-enhanced CVD processes, there are more specific types of CVD processes such as epitaxy used for the growth of mono-crystalline semiconductor layer structures and Atomic Layer Deposition (ALD) used for the deposition of various materials. A powerful technique based on atomic precursors (Physical Vapor Deposition, PVD) is Molecular Beam Epitaxy, which is mainly used in R&D due to its high flexibility.

By Roger Loo 

Gate stack 

The properties of silicon dioxide are seen as key to the success of the CMOS indus- try due to the high electrical quality of the Si/SiO2 interface, its favorable material properties and reliability. The continued reduction of the physical oxide thickness demanded by the scaling requirements ultimately renders the material unfit for further scaling as it would increase the gate leakage current prohibitively due to fundamental quantum mechanical tunneling. Materials with a higher dielectric con- stant (k-value) maintain channel control for larger thicknesses and reduce the gate leakage current. The introduction of high-k metal gate technology, which resolved the gate leakage issue in 45 nm production MOSFETs is one of the largest recent innovations in CMOS technology. This lecture discusses the properties of SiO2 lay- ers and introduces the high-k and metal gate technology used for advanced CMOS devices. 

By Lars-Ake Ragnarsson

Phosphorene transistors and circuit units for flexible Nanoelectronics

Phosphorene transistors and circuit units feature outstanding electrical performance and strong mechanical robustness and can therefore be used in flexible nanoelectronics for building transistors and other devices. Here is a good paper in SPIE Newsroom from University of Texas at Austin

Phosphorene for flexible nanoelectronics

Weinan Zhu, Maruthi N. Yogeesh and Deji Akinwande



Few-layer black phosphorus (BP) has attracted ever more attention since its debut last year as a new 2D layered semiconductor.1, 2 The puckered crystal structure distinguishes its physical properties from plane-structured graphene with a thickness-tuned bandgap ranging from 0.3 to ∼2eV. Its exceptional electrical properties include high hole mobility (∼1000 cm2/Vs) and high field-effect current modulation (105).2, 3 These properties enable both high-speed and low-power nanoelectronic applications beyond the demonstrated performance capability of graphene or transitional metal dichalcogenides (TMDs).

Intel invests in ALD Precursor Company Digital Specialty Chemicals Limited (DSC)

Digital Specialty Chemicals Limited (DSC), a dual bottom line corporation and leading provider of advanced materials to the semiconductor, pharmaceutical, and specialty chemical markets, announced today that it has received an equity investment from Intel Capital, Intel Corporation’s global investment organization. The investment will enhance the company’s research and development capabilities and will accelerate manufacturing capacity expansion.


DSC specializes in the manufacture of organophosphorus and organometallic chemistries used in both memory and logic thin film atomic layer deposition (ALD) manufacturing processes at leading semiconductor integrated circuit (IC) fabrication sites worldwide. The company is a leader in the manufacturing and handling of both novel specialty chemicals in large volume, high purity air- sensitive chemicals that require nitrogen and vacuum-operated vessels, using high pressure reactors and multiple distillation techniques.



“Since 1987, we have provided custom and high volume high purity chemicals to the semiconductor, pharmaceutical and specialty chemical markets worldwide. Our people, processes and facilities combine to offer the agility of a small, fine- chemical operation with the capacity of a large supplier,” said Dr. Ravi R. Gukathasan, CEO. “We believe that the continuation of Moore’s Law for semiconductor processing will depend greatly on continued innovation of advanced precursors which provides a growth opportunity for DSC. The funding from Intel Capital will help enable us to construct state-of-the-art R&D and manufacturing facilities to meet growing demand for thin film technologies.”

“Materials innovation is critical to enabling new capabilities in semiconductor device design and manufacturing,” said Robert Bruck, corporate vice president and general manager of Global Supply Management at Intel. “We look forward to supporting DSC’s growth including development of new materials technologies for advanced semiconductor manufacturing process technology nodes.”

Thursday, May 21, 2015

Flash-Enhanced Atomic Layer Deposition

Here is a recent review from ALD Lab Dresden - IHM, TU Dresden on Flash-Enhanced Atomic Layer Deposition (FEALD) with Open Access. The paper was presented at the Cancun, Mexico, Meeting of the Society, October 5–9, 2014. Thanks Henrik Pedersen for sharing this one!



The basic principle of Flash-Enhanced Atomic Layer Deposition according to ALD Lab Dresden.


Flash-Enhanced Atomic Layer Deposition: Basics, Opportunities, Review, and Principal Studies on the Flash-Enhanced Growth of Thin Films (Open Access)

Thomas Henke, Martin Knaut, Christoph Hossbach, Marion Geidel, Lars Rebohle, Matthias Albert, Wolfgang Skorupa and Johann W. Bartha

This was Paper 1616 presented at the Cancun, Mexico, Meeting of the Society, October 5–9, 2014.


Within this work, flash lamp annealing (FLA) is utilized to thermally enhance the film growth in atomic layer deposition (ALD). First, the basic principles of this flash-enhanced ALD (FEALD) are presented in detail, the technology is reviewed and classified. Thereafter, results of our studies on the FEALD of aluminum-based and ruthenium thin films are presented. These depositions were realized by periodically flashing on a substrate during the precursor exposure. In both cases, the film growth is induced by the flash heating and the processes exhibit typical ALD characteristics such as layer-by-layer growth and growth rates smaller than one Å/cycle. The obtained relations between process parameters and film growth parameters are discussed with the main focus on the impact of the FLA-caused temperature profile on the film growth. Similar, substrate-dependent growth rates are attributed to the different optical characteristics of the applied substrates. Regarding the ruthenium deposition, a single-source process was realized. It was also successfully applied to significantly enhance the nucleation behavior in order to overcome substrate-inhibited film growth. Besides, this work addresses technical challenges for the practical realization of this film deposition method and demonstrates the potential of this technology to extend the capabilities of thermal ALD.


Wednesday, May 20, 2015

Imec and Tokyo Electron Demonstrate Direct Cu Etch Scheme for Advanced Interconnects

IEEE IITC, Grenoble, (France) – May 20, 2015 – As reported by Imec. Today, at the IEEE IITC conference, nano-electronics research center imec and Tokyo Electron Limited (TEL) presented a direct Cu etch scheme for patterning Cu interconnects. The new scheme has great potential to overcome resistivity and reliability issues that occur while scaling conventional Cu damascene interconnects for advanced nodes.



TEM section of copper etched lines encapsulated by SiN cap layer (Imec news).

Aggressive scaling of damascene Cu interconnects leads to a drastic increase in the resistivity of the Cu wires, due to the fact that grain size is limited by the damascene trenches, which results in increased grain boundary and surface scattering. Additionally, the grain boundary negatively influences electromigration. When scaling damascene Cu interconnects, reliability issues occur because the overall copper volume is reduced and interfaces become dominant. Imec and TEL have demonstrated the feasibility of a direct Cu etch scheme to replace the conventional Cu damascene process. A key advantage of the direct Cu etch process is that it systematically results in larger grain sizes. Moreover, electromigration performance is preserved by applying an in-situ SiN cap layer that protects the Cu wires from oxidation and serves as the Cu interface.

The results were achieved in cooperation with imec’s key partners in its core CMOS programs GLOBALFOUNDRIES, Inc., Intel Corp, Micron Technology, Inc., Panasonic Corporation, Samsung Electronics Co., Ltd.,, Taiwan Semiconductor Manufacturing Co., Ltd., SK hynix Inc., Fujitsu Semiconductor Ltd., and Sony Corporation.


Tuesday, May 19, 2015

Picodeon PLD technology enables microstructural control

Finnish thin film coating specialist Picodeon Ltd Oy has developed* its ultra-short pulsed laser deposition (USPLD) surface coating technology to be able to create either porous or dense aluminium oxide (Al2O3) coatings on heat-sensitive substrates for use in a wide range of industrial metallisation applications. Porous Al2O3 layers are used for instance as filters and electrical insulation layers. Dense Al2O3 is used as a barrier layer and is also an excellent optical coating with high transmittance properties. The Picodeon process enables precise micro-structural control of Al2O3 coatings, and therefore coating characteristics, by the simple management and maintenance of coating process parameters on Coldab® Series4 USPLD batch process coating equipment. 



"This development has enormous potential for new applications of dense and porous aluminium oxide coatings on heat sensitive materials," said Picodeon VP Sales and Business Development Marko Mylläri. "It is currently very difficult to achieve these results using physical vapour deposition (PVD), sputtering or chemical vapour deposition (CVD) surface coating technologies." 

The Coldab® Series4 equipment has built-in online plasma monitoring and laser power measurement that enable very precise management of coating process parameters, as well as a PC controlled automation that records the actions of the coating process. The metrics provided by these systems mean that the coating process, and especially the thin film quality, can be controlled with great accuracy to achieve coating characteristics within highly targeted parameters. Test production runs, for example, showed that the system could improve the porosity of a 3µm Al2O3 coating, for example, from 10 percent to as much as 45 percent by tuning the scanning speed and laser power repetition rate.

The Al2O3 coatings were applied on heat-sensitive polyethylene (PE) and thermoplastic polyurethane (TPU) polymer film substrates. This is possible due to the low process temperatures required for surface coating using Picodeon's Coldab® USPLD system - one of the major benefits of the process.

In addition to Al2O3, the new Picodeon process technology can be used for other coatings as well. Picodeon has produced metallic coatings using Au and Cu, and oxides such as TiO2. Picodeon's recently released ColdAb Series4 equipment is currently being installed in commercial applications, and the company is continuing development to industrialise its USPLD processes and tools towards even larger scale volume production capabilities.


*As far as I know this product comes out of a joint development with PVD Products as stated in earlier    Press releases :

http://www.pvdproducts.com/news/pvd-products-to-build-coldab-series-4-system-for-picodeon-ltd-2

Imec and Lam Research Corporation Develop Novel ELD Metallization

New Approach to Pave the Way for Advanced Interconnects Enabling Future Technology Nodes

IEEE IITC, Grenoble (France)—May 19, 2015— During the IEEE IITC conference in Grenoble, the nanoelectronics research center imec and Lam Research Corporation today presented a novel bottom-up prefill technique for vias and contacts. The technique, based on Electroless Deposition (ELD)* of Cobalt (Co) is a highly selective method resulting in void-free filling of via and contact holes. Potentially increasing the circuit performance, it is a promising path to scaling advanced interconnects and enabling future logic and DRAM nodes at the 7 nm node and below.



Co ELD on Palladium/Tungsten (Pd/W) for different timed stops to yield an (i) under fill, (ii) potential ideal stop or an (iii) overburden in 28nm holes (Aspect Ratio (AR) 4.5).

As logic and memory nodes scale, performance of these advanced interconnects is negatively impacted by increasing interconnect resistance. Furthermore, voids that occur in heavily scaled vias severely impact yield. Imec’s industrial affiliation program on advanced interconnects is exploring novel metallization methods to solve these issues. One way to solve the problem is to identify integration and metallization alternatives that provide resistance benefits over conventional technology without compromising reliability and yield. Together with Lam Research, a Co ELD technique was demonstrated as a feasible method for highly selective bottom-up contact fill and via prefill with Cobalt (Co) as an alternative metal to Copper (Cu). Moreover, the high selectivity of the ELD process, at lower cost compared to Chemical Vapor Deposition (CVD), intrinsically ensures a good metal-to-metal interface and paves the way to void-free via filling and increased yield. Trench fill yield and line resistance may also benefit from the de-coupling of line and via aspect ratios, permitting the design of each for optimum Resistance/Capacitance (RC). Therefore, Co prefill ELD has the potential to enable future scaling of advanced logic and memory technologies.

The results were achieved in cooperation with imec’s key partners as part of its core CMOS programs: GlobalFoundries, Intel, Samsung, SK hynix, Sony, TSMC, Amkor, Micron, Utac, Qualcomm, Altera, Fujitsu, Panasonic, and Xilinx.

* ELD means fire in Swedish, how did I not see this one coming... All these wasted years with ALD... 

Monday, May 18, 2015

ALD boosts efficiency to 22.1% for nano structured Black Silicon solar cells

As reported by The researchers from Finland's Aalto University and Universitat Politècnica de Catalunya have obtained the record-breaking efficiency of 22.1% on nanostructured silicon solar cells as certified by Fraunhofer ISE CalLab. 

An almost 4% absolute increase to their previous record is achieved by applying a thin passivating film on the nanostructures by Atomic Layer Deposition, and by integrating all metal contacts on the back side of the cell.


The surface area of the best cells in the study was already 9 cm2. This is a good starting point for upscaling the results to full wafers and all the way to the industrial scale (Aalto University).


The results were published online 18.5.2015 in Nature Nanotechnology.

Black silicon solar cells with interdigitated back-contacts achieve 22.1% efficiency

Hele Savin, Päivikki Repo, Guillaume von Gastrow, Pablo Ortega, Eric Calle, Moises Garín
& Ramon Alcubilla

Nature Nanotechnology (2015) doi:10.1038/nnano.2015.89


Figure 1: Structure and reflectance of b-Si. a, Scanning electron microscopy (SEM) image (cross-sectional view) of a b-Si surface. Typical height of a silicon pillar, ∼800 nm; diameter at the bottom of the pillar, ∼200 nm. The 20 nm Al2O3 layer can be seen as a brighter layer on t…

The nanostructuring of silicon surfaces—known as black silicon—is a promising approach to eliminate front-surface reflection in photovoltaic devices without the need for a conventional antireflection coating. This might lead to both an increase in efficiency and a reduction in the manufacturing costs of solar cells. However, all previous attempts to integrate black silicon into solar cells have resulted in cell efficiencies well below 20% due to the increased charge carrier recombination at the nanostructured surface. Here, we show that a conformal alumina film can solve the issue of surface recombination in black silicon solar cells by providing excellent chemical and electrical passivation. We demonstrate that efficiencies above 22% can be reached, even in thick interdigitated back-contacted cells, where carrier transport is very sensitive to front surface passivation. This means that the surface recombination issue has truly been solved and black silicon solar cells have real potential for industrial production. Furthermore, we show that the use of black silicon can result in a 3% increase in daily energy production when compared with a reference cell with the same efficiency, due to its better angular acceptance.

Sunday, May 17, 2015

2016 will be another growth year for OEM stocks and Atomic Layer Processing

2016 will be another growth year for OEM stocks and Atomic Layer Processing. In a report recently published by JP Morgan, analysts predicted another growth year in 2016 for Semiconductors stocks, driven by technology transitions in memory and 10nm FinFET. So this is good news for all Tier 1 OEMs with a number of ALD and ALE technologies in the game.

Technology transitions by memory companies :
  • continued 3D NAND ramps
  • additional 20nm conversions
  • initial 1Xnm DRAM deployments
Foundry and logic companies :
  • deploying FinFET technologies (especially 10nm FinFET) 
  • multi-patterning steps and vertical transistors
"In general, we see capital intensity increasing by 10-15% on a per wafer basis when transitioning from 14nm/16nm FinFET to 10nm FF and by 15+% when transitioning to 20nm and below DRAM / 3D NAND. The number of critical patterning layers is increasing dramatically – in the foundry/logic segment, the number of critical layers is increasing by over 3x going from 28 nm node to the 10nm node…a significant increase," the analysts added.
Read more: http://www.benzinga.com/analyst-ratings/analyst-color/15/05/5488523/jp-morgan-sees-another-growth-year-for-semiconductors-th#ixzz3aNRgk5q0

Below is an overview of some of the ALD and ALE technologies offered by the leading OEMs. It is ion sense complete yet so please let me know what is missing (jonas.sundqvist@baldengineering.com).

LAM Research



LAM Research reported in 2014 that "The latest in Lam's market-leading tungsten deposition product line, the ALTUS Max ICEFill system controls variability by providing void-free fill of the geometrically complex 3D NAND wordlines. Using a proprietary filling technique, the new system creates the tungsten wordlines with an inside-out atomic layer deposition (ALD) process. The ICEFill process completely fills the lateral (horizontal) lines without any voids, while at the same time minimizing deposition in the vertical channel area. As a result, both electrical performance and yield are enhanced."


Lam’s ALTUS systems combine CVD and ALD technologies to deposit the highly conformal films needed for advanced tungsten metallization applications (http://www.lamresearch.com/products/deposition-products).

Lam's new ALE capability on the 2300 Kiyo F Series conductor etch system provides both the productivity and technology needed. The product leverages fast gas switching and advanced plasma techniques in the reactor to boost throughput, while dynamic RF bias enables the directional etching required to remove material in high aspect ratio (deep and narrow) features. As the latest offering in Lam's market-leading Kiyo family, the 2300 Kiyo F Series system continues to provide superior uniformity and repeatability enabled by a symmetrical chamber design, advanced electrostatic chuck technology, and independent process tuning features.


  • Shallow trench isolation
  • Source/drain engineering
  • High-k/metal gate
  • FinFET and tri-gate
  • Double and quadruple patterning
  • 3D NAND

To learn how atomic layer deposition (ALD) and atomic layer etch (ALE) processes work, watch this video from LAM Research (www.youtube.com).

Applied Materials

CENTURA® ISPRINT™ TUNGSTEN ALD/CVD - The Applied Centura iSprint Tungsten ALD/CVD system provides complete contact/via fill for structures with aspect ratios ranging from 4:1 to 7:1 and extends the capability of tungsten technology to 20nm/16nm for logic and memory applications.


The iSprint system also delivers high throughput and low cost of consumables with an optimized ALD chamber design featuring a proprietary rapid gas delivery system and small chamber volume that enable fast, effective gas purging that uses less gas (www.appliedmaterials.com).

CENTURA® INTEGRATED GATE STACKThe system consists of an ALD HfO2 (hafnium oxide) deposition chamber and specialized chambers for interface layer oxide formation, post high-k nitridation, and post-nitridation anneal


The Centura Integrated Gate Stack system with ALD high-k chamber technology for 22nm and below uses Applied’s production-proven Centura Gate Stack platform to deliver the complete high-k process sequence in a controlled high vacuum environment without an “air break” (www.appliedmaterials.com).


Steven Hung, Ph.D. who specializes in integrating ALD into the transistor manufacturing process, dives deep into the chip to show what tomorrow's transistors look like, how they work, and how Applied can help the industry meet the challenges of fabricating these ultra-tiny structures to make faster, more power-efficient microchips 
(www.youtube.com).

Tokyo Electron

Tokyo electron has a number of ALD technologies and are very strong in batch processing that is used to large extent in DRAM production to get the cost per wafer down since DRAM is a commodity product.
  • TEL Formula - Mini batch, thermal processes including ALD for High-k, SiO2, SiN.
  • TEL INDY Plus - Large batch, thermal processes including ALD for High-k, SiO2, SiN.
  • TEL INDY IRad - Large batch, PEALD for ultra low temperature SiO2 and SiN.
  • TEL NT333 - Single wafer cluster tool for high t-put SiO2.

TEL INDY Large batch furnace for thermal processing and ALD (www.tel.com)


The NT333 applies inherent ALD concepts against conventional ALD processing to address the critical performance needs imposed by aggressive geometries. The NT333 can effectively deposit with a very tight thickness control, a range of less than 1A, while maintaining a productivity of 100+ wafers per hour. With a very unique reactor design, each of the ALD duty cycles enables the NT333 to deliver the high film quality which is typically compromised at low temperature regimes (<400C). (www.tel.com)

ASM International

ASM's ALD technologies, includes thermal ALD (Pulsar) for FinFET high-k metal gate stacks, and various applications of Plasma Enhanced ALD (Emerald) as an enabler for low temperature processing such as multiple patterning on resist and deposition of doped silicon oxide for solid state doping of FinFETs.


ASM’s Pulsar uses ALD to deposit the high-k dielectric materials required for advanced CMOS transistor gates ​and other applications. Pulsar is the benchmark ALD high-k tool for the industry. It was the first ALD system to be used for high-volume production at advanced customers for high-k metal gate transistors (www.asm.com).


EmerALD XP is a process module designed to deposit thin conformal metal and dielectric ​layers by atomic layer deposition (ALD) used for advanced CMOS gate stacks and other applications (www.asm.com).


​​​Eagle XP8 is a high productivity 300mm tool for PEALD applications. The Eagle XP8 PEALD system can be configured with up to four Dual Chamber Modules (DCM), enabling eight chambers in high volume production within a very compact footprint (www.asm.com).


ASM Chip Making Process (www.youtube.com)





Saturday, May 16, 2015

Atomic Layer Deposition of Al2O3 on NF3-pre-treated graphene

Another great publication from ALD Lab Dresden, TU Dresden, Germany, and Marcel Junige and their and scientists at Linköping University of Technology, Sweden, using high resolution in-situ ellipsometer. This time these guys have grown Al2O3 on Graphene, which is very difficult unless you activate the inert grapheme surface. Marcel did this by a NF3 pre-treatment. The work was presented at SPIE micro technologies 2015 in Barcelona.

Atomic Layer Deposition of Al2O3 on NF3-pre-treated graphene

Marcel Junige, Tim Oddoy, Rositsa Yakimova, Vanya Darakchieva, Christian Wenger, Grzegorz Lupina, Matthias Albert, Johann W. Bartha
Conference: SPIE microtechnologies 2015 : Nanotechnology VII, At Barcelona, Spain, Volume: 9519



Optical Al2O3 layer thickness in progression over the ALD process time as observed by in-situ real-time Spectroscopic Ellipsometry, comparing the ALD of Al2O3 starting on a 100 nm thermally grown SiO2 reference versus an exfoliated graphene monolayer after 180 s NF3-pre-treatment.

Graphene has been considered for a variety of applications including novel nanoelectronics device concepts such as the recently reported Graphene Base Transistor (GBT). However, the deposition of ultra-thin films on top of graphene is still challenging: On the one hand, the deposition process must not damage or alter the pristine graphene monolayer; on the other hand, the finally deposited films have to provide appropriate functional properties regarding a specific application. In case of the GBT, a dielectric coating is desired which is both pin-hole free to prevent any short circuits and still thin enough (around 3-5 nm) to enable hot electron tunneling. Hence, the dielectric film closure on graphene needs to occur at an early stage of the deposition process. Atomic Layer Deposition (ALD) has been established as a physicochemical coating technique with excellent thickness control as well as unique conformality over complex three-dimensional-shaped substrates for the last decade. Especially the ALD of oxides has been extensively researched. Accordingly, an ALD process for Al2O3 yet exists that alternates the exposure of trimethylaluminum (TMA) and water (H2O) as the organometallic precursor and co-reactant of two corresponding self-terminating surface reactions, respectively. However, the ALD of Al2O3 has been reported to barely initiate on pristine graphene due to graphene’s lack of dangling bonds. A fluorine functionalization, using XeF2, has been found to provide additional nucleation sites resulting in conformal films without pinholes. Based on this literature finding, we studied the impact of pre-treatments by nitrogen trifluoride (NF3) on exfoliated as well as epitaxial graphene monolayers prior to the ALD of Al2O3. All experiments were conducted in vacuo; i. e. the pristine graphene samples were exposed to NF3 for 180 s in the same reactor immediately before applying 30 ALD cycles and the samples were transferred between the reactor and a surface analysis unit under high vacuum conditions. The ALD growth initiation was observed by in-situ real-time Spectroscopic Ellipsometry (irtSE) with a sampling rate of 1 Hz. The chemical surface composition before and after the ALD as well as the presence of graphene after the coating procedure were revealed by in-vacuo X-ray Photoelectron Spectroscopy (XPS). The morphology of the films was determined by Atomic Force Microscopy (AFM) and Scanning Electron Microscopy (SEM). The defect status was examined by Raman Spectroscopy before and after the coating procedure. Atomic Layer Deposition of Al2O3 on NF3-pre-treated graphene. Available from: https://www.researchgate.net/publication/276242739_Atomic_Layer_Deposition_of_Al2O3_on_NF3-pre-treated_graphene [accessed May 16, 2015].

Silicon nanoneedles used to reprogram cells to develop new blood vessels

Many may wonder why we need to fabricate nano structures and nano devices and things like nano dots, nano wires and nano needles. Here is a recent paper in Nature Materials that demonstrates the use of dense array of silicon nano needles used in medicine research to reprogram cells to develop new blood vessels (thanks Wendy at www.colnatec.com for sharing this one). Just imagine the huge potential for this technology in giving blood in the future! You could just have a constant supply of fresh blood cells added to the system when needed or regenerate faster after giving blood. 

So back to why do we need nano needles in this case? First of all the average person does´t like needles at all it bloody hurts! "In cell perspective needles also do damage and models suggest that the cell membrane cannot recover if it is perforated by anything larger than 500 nm" - that´s half a micron, microtechnology, old technology - Here is a clear call for nanotechnology!

That is why Tascotti and his colleagues had to go through a pretty advanced nano patterning and structuring process flow to create arrays of silicon based nano needles as described by Materials 360 Online and seen in Figure 1 from the publication in Nature Materials below:

"To create their nanoneedles, Tasciotti and his colleagues first deposited silicon nitride onto biodegradable silicon wafers using chemical vapor deposition, and then patterned nanoneedles onto their substrate using photolithography. Next, they formed porous silicon pillars using metal-assisted chemical etching, which they then shaped into nanoneedles with reactive ion etching. Importantly, the porosity of the nanoneedles could be tailored between 45% and 70%, which allows their degradation time, payload volume, and mechanical properties to be fine-tuned. The resulting nanoneedles, which were on 8 × 8 mm2chips, were 5 μm long, 50 nm wide at the apex, and 600 nm at the base. Compared with a solid cylindrical nanowire of equivalent apical diameter, the nanoneedles had more than 300 times the surface area for payload adsorption."

Biodegradable ​silicon nanoneedles delivering nucleic acids intracellularly induce localizedin vivo neovascularization

C. Chiappini,  E. De Rosa, J. O. Martinez,  X. Liu,  J. Steele,  M. M. Stevens & E. Tasciotti

The controlled delivery of nucleic acids to selected tissues remains an inefficient process mired by low transfection efficacy, poor scalability because of varying efficiency with cell type and location, and questionable safety as a result of toxicity issues arising from the typical materials and procedures employed. High efficiency and minimal toxicity in vitro has been shown for intracellular delivery of nuclei acids by using nanoneedles, yet extending these characteristics to in vivo delivery has been difficult, as current interfacing strategies rely on complex equipment or active cell internalization through prolonged interfacing. Here, we show that a tunable array of biodegradable nanoneedles fabricated by metal-assisted chemical etching of ​silicon can access the cytosol to co-deliver DNA and siRNA with an efficiency greater than 90%, and that in vivo the nanoneedles transfect the ​VEGF-165gene, inducing sustained neovascularization and a localized sixfold increase in blood perfusion in a target region of the muscle.





Figure 1 | Porous silicon nanoneedles. a, Schematic of the nanoneedle synthesis combining conventional microfabrication and metal-assisted chemical etch (MACE). RIE, Reactive ion etching. b,c, SEM micrographs showing the morphology of porous silicon nanoneedles fabricated according to the process outlined in a. b, Ordered nanoneedle arrays with pitches of 2 μm, 10 μm and 20 μm, respectively. Scale bars, 2 μm. c, High-resolution SEM micrographs of nanoneedle tips showing the nanoneedles’ porous structure and the tunability of tip diameter from less than 100 nm to over 400 nm. Scale bars, 200 nm. d, Time course of nanoneedles incubated in cell-culture medium at 37 ◦ C. Progressive biodegradation of the needles appears, with loss of structural integrity between 8 and 15 h. Complete degradation occurs at 72 h. Scale bars, 2 μm. e, ICP-AES quantification of Si released in solution. Blue and black bars represent the rate of silicon release per hour and the cumulative release of silicon, respectively, at each timepoint, expressed as a percentage of total silicon released. Error bars represent the s.d. of 3–6 replicates. (Nature Publishing Group, License Number: 3630681325690).

ALD protected Lithium Metal Anodes with improved capacity retention

University of Maryland demonstrate atomic layer deposition (ALD) of protection layers directly on Li metal with exquisite thickness control. They show that 14 nm thick, ALD Al2O3 layer can protect the Li surface from corrosion due to atmosphere, sulfur, and electrolyte exposure. Using Li-S battery cells as a test system, an improved capacity retention using ALD protected anodes over cells assembled with bare Li metal anodes for up to 100 cycles was shown.

Next-Generation Lithium Metal Anode Engineering via Atomic Layer Deposition


Alexander C Kozen, Chuan-Fu Lin, Alexander J Pearse, Marshall A Schroeder, Xiaogang Han, Liangbing Hu, Sang Bok Lee, Gary W. Rubloff, and Malachi Noked
ACS Nano, Just Accepted Manuscript
Publication Date (Web): May 13, 2015

Lithium metal is considered the most promising anode for next-generation batteries due to its high energy density of 3840 mAhg-1. However, the extreme reactivity of the Li surface can induce parasitic reactions with solvents, contamination, and shuttled active species in the electrolyte, reducing performance of batteries employing Li metal anodes. One promising solution to this issue is application of thin chemical protection layers to the Li metal surface. Using a custom made ultrahigh vacuum (UHV) integrated deposition and characterization system, we demonstrate atomic layer deposition (ALD) of protection layers directly on Li metal with exquisite thickness control. We demonstrate as a proof of concept that a 14 nm thick, ALD Al2O3 layer can protect the Li surface from corrosion due to atmosphere, sulfur, and electrolyte exposure. Using Li-S battery cells as a test system, we demonstrate an improved capacity retention using ALD protected anodes over cells assembled with bare Li metal anodes for up to 100 cycles.

Friday, May 15, 2015

New ALD Jobs Updated 16 May

Here are some new ALD Jobs that I just found and updated the job section of the blog.



Unit Process Engineering Professional
IBMHopewell Junction, NY
May 15, 2015


Metal Process Engineering Manager
TSMC
Hsinchu, TW-HSQ
May 14, 2015

Hsinchu, Taiwan
May 14, 2015
Boston area
May 14, 2015
San Jose, Ca.
May 14, 2015
Fremont, CA
May 13, 2015
Boise, ID, US
May 11, 2015

Oak Ridge demonstrates first large-scale graphene fabrication

OAK RIDGE, Tenn., May 14, 2015 -- One of the barriers to using graphene at a commercial scale could be overcome using a method demonstrated by researchers at the Department of Energy's Oak Ridge National Laboratory.




ORNL's ultrastrong graphene features layers of graphene and polymers and is an effective conductor of electricity.

Now, using chemical vapor deposition, a team led by ORNL's Ivan Vlassiouk has fabricated polymer composites containing 2-inch-by-2-inch sheets of the one-atom thick hexagonally arranged carbon atoms.

The findings, reported in the journal Applied Materials & Interfaces, could help usher in a new era in flexible electronics and change the way this reinforcing material is viewed and ultimately used.

"Before our work, superb mechanical properties of graphene were shown at a micro scale," said Vlassiouk, a member of ORNL's Energy and Transportation Science Division. "We have extended this to a larger scale, which considerably extends the potential applications and market for grapheme."

Full Story here.

Thursday, May 14, 2015

Photek Licenses Arradiance Nanofilm Technology Portfolio to Manufacture Next Generation Photodetectors

Market acceptance of Arradiance’s breakthrough nanofilm technology continues to grow following stellar technical results from the High Energy Physics community



Photek, Ltd. of St Leonards on Sea, UK today announced that it is licensing the intellectual property of Arradiance, Inc. of Sudbury, MA for use in nanofilm microchannel plate (MCP) based imagers and detectors. Arradiance’s revolutionary nanofilm technology, covered by 11 issued US patents and several pending US and worldwide patents, has been demonstrated to be the foundational technology for the next generation photomultiplier tubes (PMT) at several high energy physics installations worldwide.

“Phototubes made using Arradiance’s nanofilm technology demonstrate an order of magnitude improvement in MCP-PMT lifetime, enabling the unsurpassed timing resolution of these devices to be used in applications which have not been open to traditional MCP-based imagers and detectors,” said Gareth Jones, MD of Photek.

"Arradiance has invested millions of dollars and years of research in the development of this nanofilm technology. We are witnessing a broad acceptance across the industry as evidenced by partners such as Photek, and Argonne National Laboratory/University of Chicago’s Large Area Picosecond Photo-Detector (LAPPD) project,” explains Ken Stenton, Arradiance CEO, “It is gratifying to see this technology begin to roll out in Photek’s outstanding products.”



Arradiance nanofilms are made possible by their proprietary recipes and unique benchtop GEMStar™ Atomic Layer Deposition (ALD) system. GEMStar employs an innovative hot-wall reactor and precursor delivery system to deposit highly uniform and repeatable films in high aspect ratio, high surface area substrates.

LAM Research MMP Technology Etch for Advanced Memory

"MMP technology enables atomic layer etching (ALE), providing extendibility and repeatability with atomic-scale fidelity"


Atomic-scale fidelity - Can you put it more beautiful?

LAM Research has developed a mixed-mode pulsing (MMP) technology that enables critical conductor etch for advanced memory like 3D NAND and DRAM. The technology is available for their Kiyo Product F Series chambers


LAM Research reports: The Kiyo F Series delivers high productivity while minimizing variability for advanced memory applications. Lam's MMP technology provides advanced profile and CD control for vertical profiles with good selectivity and tuning controls for consistent etch depths. These capabilities enable higher trim rate for 3D NAND staircase etch along with excellent repeatability, which is needed for manufacturing environments. Symmetric chamber design and radial tuning provide best-in-class uniformity, which is essential for minimizing CD variability. 

In addition, for new generations of advanced memory as well as logic devices, MMP technology enables atomic layer etching (ALE), providing extendibility and repeatability with atomic-scale fidelity.

By stacking memory cells vertically, NAND flash manufacturers can pack more storage capacity onto a smaller device, ease lithography requirements, and reduce manufacturing cost per bit. For multilayer 3D NAND structures, critical conductor etch processes include staircase etch and high aspect ratio (HAR) mask open for vertical channels. This mask open is crucial since it defines the CD and CD uniformity for subsequent etching of the vertical transistor channels. For staircase etch, equal-width "steps" are created at the edge of each dielectric-film pair throughout the 3D stack to form a staircase-shaped structure. Because of extensive repetition of these steps during device processing, etching at high throughput with stringent process control is vital. CD variability must be tightly managed since wordline contacts may otherwise miss landing on a step that is too narrow or uneven. 


Just for visualisation for the reader of this blog, here the advance HAR etch that is required and mastered by LAM MMP Technology described in a reverse engineering cross section by Chipworks from a SAMSUNG V-NAND Flash array (published here)

LAM Research further reports with respect to DRAM : For advanced DRAM devices, depth control is a key parameter, particularly for HAR front-end-of-line silicon etch applications. Concerns include aspect ratio loading, where etch rates vary because of differences in feature dimensions, and depth loading, where different etch depths may occur due to pattern density variations.

More detailed information on mixed-mode plasma pulsing (MMP) can be found in this patent by LAM Research:

Mixed mode pulsing etching in plasma processing systems US 20130168354 A1

Samsungs road from HKMG to 14 nm FinFET

Here is an excellent article describing Samsungs road from 32 nm planar high-k first HKMG technology to 14 nm FinFET published in EE Times. The whole article is based in reverse engineering from TECHINSIGHT and recent publications and patents for Samsung and Globalfoundries. According to the article Samsung has lagged behind Intel in release of process nodes. However, remarkably now shrunk the lag for its 14nm to about 6 months. This article verifies the introduction of a HfO2 ALD gate dielectric at 32 nm IBM common platform technology and the ALD cap TiN.



Samsung 32nm NMOS transistor (left) and PMOS transistor (right) from EE Times / TECHINSIGHTS.



Samsung 20nm NMOS transistor (left) and PMOS transistor (right) from EE Times / TECHINSIGHTS. The PMOS showing the use of ALD TiN Work function metal gate and an ALD TaN etch stop, an ALD TiN cap and ALD HfO2 gate oxide. 


Samsung Exynos 7420 FinFET transistors from EE Times / TECHINSIGHTS. Patterning has been down with the Samsung SAPD (Self Aligned Double Patterning) technology which most probably involves a PEALD low temperature SiO2 on resist and as can be seen an ALD High-k metal gates each wrapping around the silicon fins. In addition it is quite possible that the channel doping have been realized by solid state difusion doping by deposition P and B doped silicon oxide by ALD or PEALD and diffusing the dopants into the channel by an RTP step like described here - however this is just speculation from my side.

The 14 nm FinFET is the actual technology that you will get if you buy a Samsung Galaxy S6 today, which uses the Samsung Exynos 7420 SoC - must be one of the most fully loaded ALD enabled products on the market today. Except for the processor, there must be plenty of ALD also for sure in the 3G SDRAM and the 32 GB NAND Flash. You can read more about the teardown here by Chipworks.





Wednesday, May 13, 2015

Meaglow reduces oxygen contaminatiaon in PEALD films


Meaglow Ltd has developed a set of simple designs that have allowed the successful adoption of hollow cathode plasma sources in ALD systems, overcoming some of the limitations of the old technologies. The Meaglow solution is enabling the Next Generation of equipment solutions.

Although it was initially adopted because of the lower oxygen contamination seen in nitride materials, advantages of the HC plasma sources for other materials, including oxides, soon became evident. Higher growth rates and lower plasma damage levels being evident, but the simple design of Meaglow’s HC systems also make these a very cost effective alternative.

Below are new information on the upgrade offering from Meaglow and also a white paper on oxygen contamination reduction in PEALD films.





1. Oxygen Contamination in PE-ALD
2. Plasma Source Conversion – ICP to Hollow Cathode for Ultratech/Cambridge Fiji ALD Systems
3. Savannah thermal ALD to Hollow Cathode plasma operation


Comparison of general properties of Capacitively Coupled Plasma (CCP), Inductively Coupled Plasma (ICP), Microwave Plasma (MP) and Hollow Cathode Plasma Sources (HC).



Bilkent University’s Fiji ALD system, converted to hollow cathode plasma source operation.


Savannah 100 conversion used for improved oxide deposition for US government lab.