Thursday, May 14, 2015

Samsungs road from HKMG to 14 nm FinFET

Here is an excellent article describing Samsungs road from 32 nm planar high-k first HKMG technology to 14 nm FinFET published in EE Times. The whole article is based in reverse engineering from TECHINSIGHT and recent publications and patents for Samsung and Globalfoundries. According to the article Samsung has lagged behind Intel in release of process nodes. However, remarkably now shrunk the lag for its 14nm to about 6 months. This article verifies the introduction of a HfO2 ALD gate dielectric at 32 nm IBM common platform technology and the ALD cap TiN.

Samsung 32nm NMOS transistor (left) and PMOS transistor (right) from EE Times / TECHINSIGHTS.

Samsung 20nm NMOS transistor (left) and PMOS transistor (right) from EE Times / TECHINSIGHTS. The PMOS showing the use of ALD TiN Work function metal gate and an ALD TaN etch stop, an ALD TiN cap and ALD HfO2 gate oxide. 

Samsung Exynos 7420 FinFET transistors from EE Times / TECHINSIGHTS. Patterning has been down with the Samsung SAPD (Self Aligned Double Patterning) technology which most probably involves a PEALD low temperature SiO2 on resist and as can be seen an ALD High-k metal gates each wrapping around the silicon fins. In addition it is quite possible that the channel doping have been realized by solid state difusion doping by deposition P and B doped silicon oxide by ALD or PEALD and diffusing the dopants into the channel by an RTP step like described here - however this is just speculation from my side.

The 14 nm FinFET is the actual technology that you will get if you buy a Samsung Galaxy S6 today, which uses the Samsung Exynos 7420 SoC - must be one of the most fully loaded ALD enabled products on the market today. Except for the processor, there must be plenty of ALD also for sure in the 3G SDRAM and the 32 GB NAND Flash. You can read more about the teardown here by Chipworks.

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